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URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [lm32/] [sw/] [linker.ld] - Blame information for rev 17

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Line No. Rev Author Line
1 17 alirezamon
OUTPUT_FORMAT("elf32-lm32")
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ENTRY(_start)
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__DYNAMIC = 0;
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_RAM_START = 0x0000000;
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_RAM_SIZE  = 0x4000;
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_RAM_END   = _RAM_START + _RAM_SIZE;
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MEMORY {
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  ram    : ORIGIN = 0x00000000, LENGTH = 0x4000          /*  16k */
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}
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SECTIONS
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{
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  .text :
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  {
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    _ftext = .;
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    *(.text .stub .text.* .gnu.linkonce.t.*)
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    _etext = .;
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  } > ram
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  .rodata :
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  {
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        . = ALIGN(4);
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        _frodata = .;
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    *(.rodata .rodata.* .gnu.linkonce.r.*)
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    *(.rodata1)
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        _erodata = .;
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  } > ram
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  .data :
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  {
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        . = ALIGN(4);
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        _fdata = .;
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    *(.data .data.* .gnu.linkonce.d.*)
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    *(.data1)
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    _gp = ALIGN(16);
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    *(.sdata .sdata.* .gnu.linkonce.s.*)
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    _edata = .;
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  } > ram
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  .bss :
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  {
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        . = ALIGN(4);
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    _fbss = .;
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    *(.dynsbss)
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    *(.sbss .sbss.* .gnu.linkonce.sb.*)
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    *(.scommon)
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    *(.dynbss)
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    *(.bss .bss.* .gnu.linkonce.b.*)
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    *(COMMON)
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    _ebss = .;
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    _end = .;
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  } > ram
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}
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PROVIDE(_fstack = ORIGIN(ram) + LENGTH(ram) - 4);

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