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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [lm32/] [verilog/] [src/] [er1.v] - Blame information for rev 17

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1 17 alirezamon 
/*-- ---------------------------------------------------------------------------
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--
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-- Name : ER1.v
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--
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-- Description:
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--
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--    This module is where the ER1 register implemented. ER1 and ER2 registers
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--    can be registers implemented in Lattice FPGAs using normal FPGA's
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--    programmable logic resources.  Once they are implemented, they can be
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--    accessed as if they are JTAG data registers through the FPGA JTAG port.
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--    In order to accessing these registers, JTAG instructions ER1(0x32) or
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--    ER2(0x38) needs to be written to the JTAG IR register for enabling the
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--    ER1/ER2 accessing logic.  The ER1 or ER2 accessing logic can only be
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--    enabled one at a time.  Once they are enabled, they will be disabled if
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--    another JTAG instruction is written into the JTAG instruction register.
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--    The registers allow dynamically accessing the FPGA internal information
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--    even when the device is running.  Therefore, they are very useful for some
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--    of the IP cores.  In order to let ER1/ER2 registers shared by multiple IP
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--    cores or other designs, there is a ER1/ER2 structure patterned by Lattice.
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--    The ER1/ER2 structure allows only one ER1 register but more than one ER2
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--    registers in an FPGA device.  Please refer to the related document for
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--    this patterned ER1/ER2 structure.
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--
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-- $Log: $
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--
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-- $Header: $
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--
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-- Copyright (C) 2004 Lattice Semiconductor Corp.  All rights reserved.
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--
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-- ---------------------------------------------------------------------------*/
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module ER1 (input  JTCK,
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            input  JTDI,
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            output JTDO1,
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            output reg JTDO2,
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            input  JSHIFT,
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            input  JUPDATE,
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            input  JRSTN,
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            input  JCE1,
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            input [14:0] ER2_TDO,
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            output reg [14:0] IP_ENABLE,
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            input  ISPTRACY_ER2_TDO,
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            output ISPTRACY_ENABLE,
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            output CONTROL_DATAN)/* synthesis syn_hier = hard */;
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   wire            controlDataNBit;
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   wire            ispTracyEnableBit;
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   wire [3:0]       encodedIpEnableBits;
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   wire [9:0]       er1TdiBit;
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   wire            captureDrER1;
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   assign          JTDO1 = er1TdiBit[0];
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   TYPEB BIT0 (.CLK(JTCK),
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               .RESET_N(JRSTN),
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               .CLKEN(JCE1),
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               .TDI(er1TdiBit[1]),
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               .TDO(er1TdiBit[0]),
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               .DATA_IN(1'b0),
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               .CAPTURE_DR(captureDrER1));
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   TYPEB BIT1 (.CLK(JTCK),
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               .RESET_N(JRSTN),
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               .CLKEN(JCE1),
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               .TDI(er1TdiBit[2]),
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               .TDO(er1TdiBit[1]),
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               .DATA_IN(1'b0),
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               .CAPTURE_DR(captureDrER1));
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   TYPEB BIT2 (.CLK(JTCK),
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               .RESET_N(JRSTN),
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               .CLKEN(JCE1),
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               .TDI(er1TdiBit[3]),
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               .TDO(er1TdiBit[2]),
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               .DATA_IN(1'b1),
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               .CAPTURE_DR(captureDrER1));
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   TYPEA BIT3 (.CLK(JTCK),
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               .RESET_N(JRSTN),
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               .CLKEN(JCE1),
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               .TDI(er1TdiBit[4]),
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               .TDO(er1TdiBit[3]),
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               .DATA_OUT(controlDataNBit),
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               .DATA_IN(controlDataNBit),
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               .CAPTURE_DR(captureDrER1),
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               .UPDATE_DR(JUPDATE));
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   assign CONTROL_DATAN = controlDataNBit;
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   TYPEA BIT4 (.CLK(JTCK),
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               .RESET_N(JRSTN),
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               .CLKEN(JCE1),
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               .TDI(er1TdiBit[5]),
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               .TDO(er1TdiBit[4]),
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               .DATA_OUT(ispTracyEnableBit),
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               .DATA_IN(ispTracyEnableBit),
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               .CAPTURE_DR(captureDrER1),
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               .UPDATE_DR(JUPDATE)
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               );
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   assign ISPTRACY_ENABLE = ispTracyEnableBit;
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   TYPEA BIT5 (.CLK(JTCK),
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               .RESET_N(JRSTN),
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               .CLKEN(JCE1),
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               .TDI(er1TdiBit[6]),
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               .TDO(er1TdiBit[5]),
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               .DATA_OUT(encodedIpEnableBits[0]),
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               .DATA_IN(encodedIpEnableBits[0]),
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               .CAPTURE_DR(captureDrER1),
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               .UPDATE_DR(JUPDATE));
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   TYPEA BIT6 (.CLK(JTCK),
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               .RESET_N(JRSTN),
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               .CLKEN(JCE1),
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               .TDI(er1TdiBit[7]),
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               .TDO(er1TdiBit[6]),
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               .DATA_OUT(encodedIpEnableBits[1]),
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               .DATA_IN(encodedIpEnableBits[1]),
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               .CAPTURE_DR(captureDrER1),
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               .UPDATE_DR(JUPDATE));
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   TYPEA BIT7 (.CLK(JTCK),
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               .RESET_N(JRSTN),
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               .CLKEN(JCE1),
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               .TDI(er1TdiBit[8]),
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               .TDO(er1TdiBit[7]),
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               .DATA_OUT(encodedIpEnableBits[2]),
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               .DATA_IN(encodedIpEnableBits[2]),
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               .CAPTURE_DR(captureDrER1),
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               .UPDATE_DR(JUPDATE));
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   TYPEA BIT8 (.CLK(JTCK),
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               .RESET_N(JRSTN),
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               .CLKEN(JCE1),
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               .TDI(er1TdiBit[9]),
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               .TDO(er1TdiBit[8]),
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               .DATA_OUT(encodedIpEnableBits[3]),
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               .DATA_IN(encodedIpEnableBits[3]),
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               .CAPTURE_DR(captureDrER1),
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               .UPDATE_DR(JUPDATE)
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               );
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   assign er1TdiBit[9] = JTDI;
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   assign captureDrER1  = !JSHIFT & JCE1;
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   always @ (encodedIpEnableBits,ISPTRACY_ER2_TDO, ER2_TDO)
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   begin
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    case (encodedIpEnableBits)
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      4'h0: begin
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                IP_ENABLE <= 15'b000000000000000;
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                JTDO2 <= ISPTRACY_ER2_TDO;
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            end
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      4'h1: begin
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                IP_ENABLE <= 15'b000000000000001;
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                JTDO2 <= ER2_TDO[0];
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            end
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      4'h2: begin
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                IP_ENABLE <= 15'b000000000000010;
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                JTDO2 <= ER2_TDO[1];
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            end
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      4'h3: begin
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                IP_ENABLE <= 15'b000000000000100;
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                JTDO2 <= ER2_TDO[2];
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            end
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      4'h4: begin
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                IP_ENABLE <= 15'b000000000001000;
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                JTDO2 <= ER2_TDO[3];
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            end
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      4'h5: begin
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                IP_ENABLE <= 15'b000000000010000;
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                JTDO2 <= ER2_TDO[4];
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            end
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      4'h6: begin
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                IP_ENABLE <= 15'b000000000100000;
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                JTDO2 <= ER2_TDO[5];
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            end
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      4'h7: begin
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                IP_ENABLE <= 15'b000000001000000;
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                JTDO2 <= ER2_TDO[6];
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            end
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      4'h8: begin
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                IP_ENABLE <= 15'b000000010000000;
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                JTDO2 <= ER2_TDO[7];
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            end
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      4'h9: begin
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                IP_ENABLE <= 15'b000000100000000;
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                JTDO2 <= ER2_TDO[8];
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            end
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      4'hA: begin
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                IP_ENABLE <= 15'b000001000000000;
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                JTDO2 <= ER2_TDO[9];
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            end
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      4'hB: begin
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                IP_ENABLE <= 15'b000010000000000;
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                JTDO2 <= ER2_TDO[10];
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            end
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      4'hC: begin
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                IP_ENABLE <= 15'b000100000000000;
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                JTDO2 <= ER2_TDO[11];
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            end
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      4'hD: begin
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                IP_ENABLE <= 15'b001000000000000;
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                JTDO2 <= ER2_TDO[12];
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            end
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      4'hE: begin
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                IP_ENABLE <= 15'b010000000000000;
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                JTDO2 <= ER2_TDO[13];
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            end
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      4'hF: begin
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                IP_ENABLE <= 15'b100000000000000;
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                JTDO2 <= ER2_TDO[14];
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            end
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    endcase
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  end
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endmodule

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