OpenCores
URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [lm32/] [verilog/] [src/] [jtag_cores.v] - Blame information for rev 17

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 17 alirezamon 
// =============================================================================
2 
//                           COPYRIGHT NOTICE
3 
// Copyright 2006 (c) Lattice Semiconductor Corporation
4 
// ALL RIGHTS RESERVED
5 
// This confidential and proprietary software may be used only as authorised by
6 
// a licensing agreement from Lattice Semiconductor Corporation.
7 
// The entire notice above must be reproduced on all authorized copies and
8 
// copies may only be made to the extent permitted by a licensing agreement from
9 
// Lattice Semiconductor Corporation.
10 
//
11 
// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
12 
// 5555 NE Moore Court                            408-826-6000 (other locations)
13 
// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
14 
// U.S.A                                   email: techsupport@latticesemi.com
15 
// =============================================================================/
16 
//                         FILE DETAILS
17 
// Project          : LatticeMico32
18 
// File             : jtag_cores.v
19 
// Title            : Instantiates all IP cores on JTAG chain.
20 
// Dependencies     : system_conf.v
21 
// Version          : 6.0.13
22 
// =============================================================================
23 
 
24 
`include "system_conf.v"
25 
 
26 
/////////////////////////////////////////////////////
27 
// Module interface
28 
/////////////////////////////////////////////////////
29 
 
30 
module jtag_cores#(
31 
        parameter test="ali"
32 
 
33 
)
34 
  (
35 
    // ----- Inputs -------
36 
`ifdef INCLUDE_LM32
37 
    reg_d,
38 
    reg_addr_d,
39 
`endif
40 
`ifdef INCLUDE_SPI
41 
    spi_q,
42 
`endif
43 
    // ----- Outputs -------
44 
`ifdef INCLUDE_LM32
45 
    reg_update,
46 
    reg_q,
47 
    reg_addr_q,
48 
`endif
49 
`ifdef INCLUDE_SPI
50 
    spi_c,
51 
    spi_d,
52 
    spi_sn,
53 
`endif
54 
    jtck,
55 
    jrstn
56 
    );
57 
 
58 
/////////////////////////////////////////////////////
59 
// Inputs
60 
/////////////////////////////////////////////////////
61 
 
62 
`ifdef INCLUDE_LM32
63 
input [7:0] reg_d;
64 
input [2:0] reg_addr_d;
65 
`endif
66 
 
67 
`ifdef INCLUDE_SPI
68 
input spi_q;
69 
`endif
70 
 
71 
/////////////////////////////////////////////////////
72 
// Outputs
73 
/////////////////////////////////////////////////////
74 
 
75 
`ifdef INCLUDE_LM32
76 
output reg_update;
77 
wire   reg_update;
78 
output [7:0] reg_q;
79 
wire   [7:0] reg_q;
80 
output [2:0] reg_addr_q;
81 
wire   [2:0] reg_addr_q;
82 
`endif
83 
 
84 
`ifdef INCLUDE_SPI
85 
output spi_c;
86 
wire   spi_c;
87 
output spi_d;
88 
wire   spi_d;
89 
output spi_sn;
90 
wire   spi_sn;
91 
`endif
92 
 
93 
output jtck;
94 
wire   jtck;    /* synthesis ER1_MARK="jtck" */ /* synthesis syn_keep=1 */
95 
output jrstn;
96 
wire   jrstn; /* synthesis ER1_MARK="jrstn" */ /* synthesis syn_keep=1 */
97 
 
98 
 
99 
/////////////////////////////////////////////////////
100 
// Internal nets and registers
101 
/////////////////////////////////////////////////////
102 
 
103 
wire rtiER1;
104 
wire rtiER2;
105 
wire tdi;/* synthesis ER1_MARK="jtdi" */ /* synthesis syn_keep=1 */
106 
wire tdoEr1;/* synthesis ER1_MARK="jtdo1" */ /* synthesis syn_keep=1 */
107 
wire tdoEr2;
108 
wire jtdo2_mux;/* synthesis ER1_MARK="jtdo2" */ /* synthesis syn_keep=1 */
109 
wire spi_tdo2;
110 
wire shiftDr;/* synthesis ER1_MARK="jshift" */ /* synthesis syn_keep=1 */
111 
wire updateDr;/* synthesis ER1_MARK="jupdate" */ /* synthesis syn_keep=1 */
112 
wire enableEr1;/* synthesis ER1_MARK="jce1" */ /* synthesis syn_keep=1 */
113 
wire enableEr2;/* synthesis ER1_MARK="jce2" */ /* synthesis syn_keep=1 */
114 
wire [14:0] ipEnable;/* synthesis ER1_MARK="ip_enable" */ /* synthesis syn_keep=1 */
115 
wire controlDataN;/* synthesis ER1_MARK="control_datan" */ /* synthesis syn_keep=1 */
116 
wire lm32_isptracy_enable;/* synthesis ER1_MARK="isptracy_enable" */ /* synthesis syn_keep=1 */
117 
 
118 
 
119 
/////////////////////////////////////////////////////
120 
// Instantiations
121 
/////////////////////////////////////////////////////
122 
 
123 
generate
124 
   if (lat_family == "EC" || lat_family == "ECP" || lat_family == "XP") begin
125 
     JTAGB jtagb (.JTCK           (jtck),
126 
                  .JRTI1          (rtiER1),
127 
                  .JRTI2          (rtiER2),
128 
                  .JTDI           (tdi),
129 
                  .JSHIFT         (shiftDr),
130 
                  .JUPDATE        (updateDr),
131 
                  .JRSTN          (jrstn),
132 
                  .JCE1           (enableEr1),
133 
                  .JCE2           (enableEr2),
134 
                  .JTDO1          (tdoEr1),
135 
                  .JTDO2          (jtdo2_mux)) /* synthesis ER1="ENABLED" */ /* synthesis ER2="ENABLED" */ /* synthesis JTAG_FLASH_PRGRM="DISABLED" */;
136 
   end else if (lat_family == "ECP2" || lat_family == "ECP2M") begin
137 
     JTAGC jtagc (.JTCK           (jtck),
138 
                  .JRTI1          (rtiER1),
139 
                  .JRTI2          (rtiER2),
140 
                  .JTDI           (tdi),
141 
                  .JSHIFT         (shiftDr),
142 
                  .JUPDATE        (updateDr),
143 
                  .JRSTN          (jrstn),
144 
                  .IJTAGEN        (1'b1),
145 
                  .JCE1           (enableEr1),
146 
                  .JCE2           (enableEr2),
147 
                  .JTDO1          (tdoEr1),
148 
                  .JTDO2          (jtdo2_mux)) /* synthesis ER1="ENABLED" */ /* synthesis ER2="ENABLED" */ /* synthesis JTAG_FLASH_PRGRM="DISABLED" */;
149 
   end else if (lat_family == "SC" || lat_family == "SCM") begin // if (lat_family == "ECP2" || lat_family == "ECP2M")
150 
      JTAGA jtaga(.JTCK           (jtck),
151 
                  .JRTI1          (rtiER1),
152 
                  .JRTI2          (rtiER2),
153 
                  .JTDI           (tdi),
154 
                  .JSHIFT         (shiftDr),
155 
                  .JUPDATE        (updateDr),
156 
                  .JRSTN          (jrstn),
157 
                  .JCE1           (enableEr1),
158 
                  .JCE2           (enableEr2),
159 
                  .JTDO1          (tdoEr1),
160 
                  .JTDO2          (jtdo2_mux)) /* synthesis ER1="ENABLED" */ /* synthesis ER2="ENABLED" */ /* synthesis JTAG_FLASH_PRGRM="DISABLED" */;
161 
   end
162 
endgenerate
163 
 
164 
ER1 er1 (
165 
    .JTCK           (jtck),
166 
    .JTDI           (tdi),
167 
    .JTDO1          (tdoEr1),
168 
    .JTDO2          (jtdo2_mux),
169 
    .JSHIFT         (shiftDr),
170 
    .JUPDATE        (updateDr),
171 
    .JRSTN          (jrstn),
172 
    .JCE1           (enableEr1),
173 
    .ER2_TDO        ({13'b0,tdoEr2,spi_tdo2}),
174 
    .IP_ENABLE      (ipEnable),
175 
    .ISPTRACY_ENABLE(lm32_isptracy_enable),
176 
    .ISPTRACY_ER2_TDO(lm32_isptracy_enable),
177 
    .CONTROL_DATAN  (controlDataN));
178 
 
179 
`ifdef INCLUDE_LM32
180 
jtag_lm32 jtag_lm32 (
181 
    .JTCK           (jtck),
182 
    .JTDI           (tdi),
183 
    .JTDO2          (tdoEr2),
184 
    .JSHIFT         (shiftDr),
185 
    .JUPDATE        (updateDr),
186 
    .JRSTN          (jrstn),
187 
    .JCE2           (enableEr2),
188 
    .JTAGREG_ENABLE (ipEnable[1]),
189 
    .CONTROL_DATAN  (controlDataN),
190 
    .REG_UPDATE     (reg_update),
191 
    .REG_D          (reg_d),
192 
    .REG_ADDR_D     (reg_addr_d),
193 
    .REG_Q          (reg_q),
194 
    .REG_ADDR_Q     (reg_addr_q)
195 
    );
196 
`endif
197 
 
198 
`ifdef INCLUDE_SPI
199 
SPIPROG spiprog_inst (
200 
     .JTCK           (tck),
201 
         .JTDI           (tdi),
202 
         .JTDO2          (spi_tdo2),
203 
         .JSHIFT         (shiftDr),
204 
         .JUPDATE        (updateDr),
205 
         .JRSTN          (resetN),
206 
         .JCE2           (enableEr2),
207 
         .SPIPROG_ENABLE (ipEnable[0]),
208 
         .CONTROL_DATAN  (controlDataN),
209 
         .SPI_C          (spi_c),
210 
         .SPI_D          (spi_d),
211 
         .SPI_SN         (spi_sn),
212 
         .SPI_Q          (spi_q)
213 
         );
214 
`endif
215 
 
216 
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.