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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [lm32/] [verilog/] [src/] [jtag_lm32.v] - Blame information for rev 17

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1 17 alirezamon 
// =============================================================================
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//                           COPYRIGHT NOTICE
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// Copyright 2006 (c) Lattice Semiconductor Corporation
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// ALL RIGHTS RESERVED
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// This confidential and proprietary software may be used only as authorised by
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// a licensing agreement from Lattice Semiconductor Corporation.
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// The entire notice above must be reproduced on all authorized copies and
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// copies may only be made to the extent permitted by a licensing agreement from
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// Lattice Semiconductor Corporation.
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//
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// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
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// 5555 NE Moore Court                            408-826-6000 (other locations)
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// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
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// U.S.A                                   email: techsupport@latticesemi.com
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// =============================================================================/
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//                         FILE DETAILS
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// Project          : LatticeMico32
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// File             : jtag_lm32.v
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// Title            : JTAG data register for LM32 CPU debug interface
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// Version          : 6.0.13
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// =============================================================================
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/////////////////////////////////////////////////////
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// Module interface
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/////////////////////////////////////////////////////
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module jtag_lm32 (
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        input JTCK,
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        input JTDI,
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        output JTDO2,
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        input JSHIFT,
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        input JUPDATE,
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        input JRSTN,
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        input JCE2,
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        input JTAGREG_ENABLE,
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        input CONTROL_DATAN,
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        output REG_UPDATE,
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        input [7:0] REG_D,
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        input [2:0] REG_ADDR_D,
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        output [7:0] REG_Q,
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        output [2:0] REG_ADDR_Q
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        );
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/////////////////////////////////////////////////////
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// Internal nets and registers
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/////////////////////////////////////////////////////
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wire [9:0] tdibus;
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/////////////////////////////////////////////////////
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// Instantiations
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/////////////////////////////////////////////////////
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   wire clk_enable,captureDr;
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TYPEA DATA_BIT0 (
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    .CLK(JTCK),
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    .RESET_N(JRSTN),
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    .CLKEN(clk_enable),
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    .TDI(JTDI),
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    .TDO(tdibus[0]),
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    .DATA_OUT(REG_Q[0]),
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    .DATA_IN(REG_D[0]),
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    .CAPTURE_DR(captureDr),
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    .UPDATE_DR(JUPDATE)
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    );
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TYPEA DATA_BIT1 (
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    .CLK(JTCK),
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    .RESET_N(JRSTN),
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    .CLKEN(clk_enable),
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    .TDI(tdibus[0]),
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    .TDO(tdibus[1]),
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    .DATA_OUT(REG_Q[1]),
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    .DATA_IN(REG_D[1]),
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    .CAPTURE_DR(captureDr),
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    .UPDATE_DR(JUPDATE)
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    );
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TYPEA DATA_BIT2 (
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    .CLK(JTCK),
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    .RESET_N(JRSTN),
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    .CLKEN(clk_enable),
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    .TDI(tdibus[1]),
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    .TDO(tdibus[2]),
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    .DATA_OUT(REG_Q[2]),
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    .DATA_IN(REG_D[2]),
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    .CAPTURE_DR(captureDr),
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    .UPDATE_DR(JUPDATE)
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    );
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TYPEA DATA_BIT3 (
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    .CLK(JTCK),
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    .RESET_N(JRSTN),
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    .CLKEN(clk_enable),
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    .TDI(tdibus[2]),
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    .TDO(tdibus[3]),
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    .DATA_OUT(REG_Q[3]),
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    .DATA_IN(REG_D[3]),
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    .CAPTURE_DR(captureDr),
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    .UPDATE_DR(JUPDATE)
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    );
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TYPEA DATA_BIT4 (
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    .CLK(JTCK),
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    .RESET_N(JRSTN),
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    .CLKEN(clk_enable),
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    .TDI(tdibus[3]),
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    .TDO(tdibus[4]),
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    .DATA_OUT(REG_Q[4]),
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    .DATA_IN(REG_D[4]),
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    .CAPTURE_DR(captureDr),
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    .UPDATE_DR(JUPDATE)
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    );
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TYPEA DATA_BIT5 (
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    .CLK(JTCK),
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    .RESET_N(JRSTN),
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    .CLKEN(clk_enable),
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    .TDI(tdibus[4]),
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    .TDO(tdibus[5]),
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    .DATA_OUT(REG_Q[5]),
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    .DATA_IN(REG_D[5]),
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    .CAPTURE_DR(captureDr),
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    .UPDATE_DR(JUPDATE)
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    );
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TYPEA DATA_BIT6 (
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    .CLK(JTCK),
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    .RESET_N(JRSTN),
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    .CLKEN(clk_enable),
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    .TDI(tdibus[5]),
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    .TDO(tdibus[6]),
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    .DATA_OUT(REG_Q[6]),
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    .DATA_IN(REG_D[6]),
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    .CAPTURE_DR(captureDr),
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    .UPDATE_DR(JUPDATE)
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    );
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TYPEA DATA_BIT7 (
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    .CLK(JTCK),
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    .RESET_N(JRSTN),
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    .CLKEN(clk_enable),
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    .TDI(tdibus[6]),
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    .TDO(tdibus[7]),
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    .DATA_OUT(REG_Q[7]),
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    .DATA_IN(REG_D[7]),
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    .CAPTURE_DR(captureDr),
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    .UPDATE_DR(JUPDATE)
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    );
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TYPEA ADDR_BIT0 (
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    .CLK(JTCK),
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    .RESET_N(JRSTN),
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    .CLKEN(clk_enable),
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    .TDI(tdibus[7]),
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    .TDO(tdibus[8]),
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    .DATA_OUT(REG_ADDR_Q[0]),
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    .DATA_IN(REG_ADDR_D[0]),
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    .CAPTURE_DR(captureDr),
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    .UPDATE_DR(JUPDATE)
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    );
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TYPEA ADDR_BIT1 (
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    .CLK(JTCK),
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    .RESET_N(JRSTN),
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    .CLKEN(clk_enable),
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    .TDI(tdibus[8]),
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    .TDO(tdibus[9]),
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    .DATA_OUT(REG_ADDR_Q[1]),
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    .DATA_IN(REG_ADDR_D[1]),
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    .CAPTURE_DR(captureDr),
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    .UPDATE_DR(JUPDATE)
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    );
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TYPEA ADDR_BIT2 (
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    .CLK(JTCK),
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    .RESET_N(JRSTN),
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    .CLKEN(clk_enable),
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    .TDI(tdibus[9]),
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    .TDO(JTDO2),
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    .DATA_OUT(REG_ADDR_Q[2]),
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    .DATA_IN(REG_ADDR_D[2]),
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    .CAPTURE_DR(captureDr),
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    .UPDATE_DR(JUPDATE)
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    );
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/////////////////////////////////////////////////////
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// Combinational logic
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/////////////////////////////////////////////////////
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assign clk_enable = JTAGREG_ENABLE & JCE2;
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assign captureDr = !JSHIFT & JCE2;
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// JCE2 is only active during shift
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assign REG_UPDATE = JTAGREG_ENABLE & JUPDATE;
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endmodule

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