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// =============================================================================
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// COPYRIGHT NOTICE
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// Copyright 2006 (c) Lattice Semiconductor Corporation
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// ALL RIGHTS RESERVED
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// This confidential and proprietary software may be used only as authorised by
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// a licensing agreement from Lattice Semiconductor Corporation.
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// The entire notice above must be reproduced on all authorized copies and
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// copies may only be made to the extent permitted by a licensing agreement from
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// Lattice Semiconductor Corporation.
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//
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// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
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// 5555 NE Moore Court 408-826-6000 (other locations)
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// Hillsboro, OR 97124 web : http://www.latticesemi.com/
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// U.S.A email: techsupport@latticesemi.com
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// =============================================================================/
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// FILE DETAILS
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// Project : LatticeMico32
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// File : lm32_icache.v
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// Title : Instruction cache
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// Dependencies : lm32_include.v
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// Version : 6.1.17
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// =============================================================================
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`include "lm32_include.v"
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`define LM32_IC_ADDR_OFFSET_RNG addr_offset_msb:addr_offset_lsb
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`define LM32_IC_ADDR_SET_RNG addr_set_msb:addr_set_lsb
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`define LM32_IC_ADDR_TAG_RNG addr_tag_msb:addr_tag_lsb
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`define LM32_IC_ADDR_IDX_RNG addr_set_msb:addr_offset_lsb
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`define LM32_IC_TMEM_ADDR_WIDTH addr_set_width
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`define LM32_IC_TMEM_ADDR_RNG (`LM32_IC_TMEM_ADDR_WIDTH-1):0
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`define LM32_IC_DMEM_ADDR_WIDTH (addr_offset_width+addr_set_width)
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`define LM32_IC_DMEM_ADDR_RNG (`LM32_IC_DMEM_ADDR_WIDTH-1):0
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`define LM32_IC_TAGS_WIDTH (addr_tag_width+1)
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`define LM32_IC_TAGS_RNG (`LM32_IC_TAGS_WIDTH-1):0
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`define LM32_IC_TAGS_TAG_RNG (`LM32_IC_TAGS_WIDTH-1):1
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`define LM32_IC_TAGS_VALID_RNG 0
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`define LM32_IC_STATE_RNG 3:0
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`define LM32_IC_STATE_FLUSH_INIT 4'b0001
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`define LM32_IC_STATE_FLUSH 4'b0010
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`define LM32_IC_STATE_CHECK 4'b0100
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`define LM32_IC_STATE_REFILL 4'b1000
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/////////////////////////////////////////////////////
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// Module interface
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/////////////////////////////////////////////////////
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module lm32_icache (
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// ----- Inputs -----
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clk_i,
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rst_i,
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stall_a,
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stall_f,
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address_a,
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address_f,
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read_enable_f,
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refill_ready,
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refill_data,
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iflush,
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// ----- Outputs -----
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stall_request,
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restart_request,
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refill_request,
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refill_address,
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refilling,
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inst
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);
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/////////////////////////////////////////////////////
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// Parameters
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/////////////////////////////////////////////////////
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parameter associativity = 1; // Associativity of the cache (Number of ways)
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parameter sets = 512; // Number of sets
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parameter bytes_per_line = 16; // Number of bytes per cache line
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parameter base_address = 0; // Base address of cachable memory
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parameter limit = 0; // Limit (highest address) of cachable memory
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localparam addr_offset_width = 2;
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localparam addr_set_width = 9;
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localparam addr_offset_lsb = 2;
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localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
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localparam addr_set_lsb = (addr_offset_msb+1);
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localparam addr_set_msb = (addr_set_lsb+addr_set_width-1);
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localparam addr_tag_lsb = (addr_set_msb+1);
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localparam addr_tag_msb = 31;
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localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1);
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/////////////////////////////////////////////////////
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// Inputs
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/////////////////////////////////////////////////////
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input clk_i; // Clock
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input rst_i; // Reset
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input stall_a; // Stall instruction in A stage
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input stall_f; // Stall instruction in F stage
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input [`LM32_PC_RNG] address_a; // Address of instruction in A stage
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input [`LM32_PC_RNG] address_f; // Address of instruction in F stage
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input read_enable_f; // Indicates if cache access is valid
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input refill_ready; // Next word of refill data is ready
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input [`LM32_INSTRUCTION_RNG] refill_data; // Data to refill the cache with
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input iflush; // Flush the cache
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/////////////////////////////////////////////////////
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// Outputs
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/////////////////////////////////////////////////////
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output stall_request; // Request to stall the pipeline
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wire stall_request;
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output restart_request; // Request to restart instruction that caused the cache miss
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reg restart_request;
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output refill_request; // Request to refill a cache line
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wire refill_request;
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output [`LM32_PC_RNG] refill_address; // Base address of cache refill
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reg [`LM32_PC_RNG] refill_address;
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output refilling; // Indicates the instruction cache is currently refilling
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reg refilling;
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output [`LM32_INSTRUCTION_RNG] inst; // Instruction read from cache
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wire [`LM32_INSTRUCTION_RNG] inst;
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/////////////////////////////////////////////////////
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// Internal nets and registers
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/////////////////////////////////////////////////////
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wire enable;
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wire [0:associativity-1] way_mem_we;
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wire [`LM32_INSTRUCTION_RNG] way_data[0:associativity-1];
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wire [`LM32_IC_TAGS_TAG_RNG] way_tag[0:associativity-1];
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wire [0:associativity-1] way_valid;
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wire [0:associativity-1] way_match;
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wire miss;
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wire [`LM32_IC_TMEM_ADDR_RNG] tmem_read_address;
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wire [`LM32_IC_TMEM_ADDR_RNG] tmem_write_address;
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wire [`LM32_IC_DMEM_ADDR_RNG] dmem_read_address;
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wire [`LM32_IC_DMEM_ADDR_RNG] dmem_write_address;
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wire [`LM32_IC_TAGS_RNG] tmem_write_data;
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reg [`LM32_IC_STATE_RNG] state;
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wire flushing;
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wire check;
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wire refill;
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reg [associativity-1:0] refill_way_select;
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reg [`LM32_IC_ADDR_OFFSET_RNG] refill_offset;
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wire last_refill;
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reg [`LM32_IC_TMEM_ADDR_RNG] flush_set;
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genvar i;
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/////////////////////////////////////////////////////
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// Functions
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/////////////////////////////////////////////////////
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`define INCLUDE_FUNCTION
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`include "lm32_functions.v"
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/////////////////////////////////////////////////////
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// Instantiations
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/////////////////////////////////////////////////////
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generate
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for (i = 0; i < associativity; i = i + 1)
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begin : memories
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// Way 0 data
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lm32_ram #(
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// ----- Parameters -------
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.data_width (32),
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.address_width (`LM32_IC_DMEM_ADDR_WIDTH)
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) way_0_data_ram (
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// ----- Inputs -------
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.read_clk (clk_i),
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.write_clk (clk_i),
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.reset (rst_i),
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.read_address (dmem_read_address),
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.enable_read (enable),
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.write_address (dmem_write_address),
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.enable_write (`TRUE),
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.write_enable (way_mem_we[i]),
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.write_data (refill_data),
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// ----- Outputs -------
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.read_data (way_data[i])
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);
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// Way 0 tags
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lm32_ram #(
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// ----- Parameters -------
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.data_width (`LM32_IC_TAGS_WIDTH),
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.address_width (`LM32_IC_TMEM_ADDR_WIDTH)
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) way_0_tag_ram (
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// ----- Inputs -------
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.read_clk (clk_i),
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.write_clk (clk_i),
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.reset (rst_i),
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.read_address (tmem_read_address),
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.enable_read (enable),
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.write_address (tmem_write_address),
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.enable_write (`TRUE),
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.write_enable (way_mem_we[i] | flushing),
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.write_data (tmem_write_data),
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// ----- Outputs -------
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.read_data ({way_tag[i], way_valid[i]})
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);
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end
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endgenerate
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/////////////////////////////////////////////////////
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// Combinational logic
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/////////////////////////////////////////////////////
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// Compute which ways in the cache match the address address being read
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generate
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for (i = 0; i < associativity; i = i + 1)
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begin : match
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assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_f[`LM32_IC_ADDR_TAG_RNG], `TRUE});
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end
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endgenerate
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// Select data from way that matched the address being read
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generate
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if (associativity == 1)
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begin : inst_1
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assign inst = way_data[0];
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end
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else if (associativity == 2)
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begin : inst_2
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assign inst = way_match[0] ? way_data[0] : way_data[1];
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end
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endgenerate
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// Compute address to use to index into the data memories
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generate
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if (bytes_per_line > 4)
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begin : wadr1
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assign dmem_write_address = {refill_address[`LM32_IC_ADDR_SET_RNG], refill_offset};
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end
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else
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begin : wadr2
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assign dmem_write_address = refill_address[`LM32_IC_ADDR_SET_RNG];
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end
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endgenerate
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assign dmem_read_address = address_a[`LM32_IC_ADDR_IDX_RNG];
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// Compute address to use to index into the tag memories
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assign tmem_read_address = address_a[`LM32_IC_ADDR_SET_RNG];
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assign tmem_write_address = flushing
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? flush_set
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: refill_address[`LM32_IC_ADDR_SET_RNG];
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// Compute signal to indicate when we are on the last refill accesses
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generate
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if (bytes_per_line > 4)
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begin : lrefil1
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assign last_refill = refill_offset == {addr_offset_width{1'b1}};
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end
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else
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begin : lrefil2
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assign last_refill = `TRUE;
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end
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endgenerate
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// Compute data and tag memory access enable
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assign enable = (stall_a == `FALSE);
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// Compute data and tag memory write enables
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generate
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if (associativity == 1)
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begin : we_1
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assign way_mem_we[0] = (refill_ready == `TRUE);
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end
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else
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begin : we_2
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assign way_mem_we[0] = (refill_ready == `TRUE) && (refill_way_select[0] == `TRUE);
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assign way_mem_we[1] = (refill_ready == `TRUE) && (refill_way_select[1] == `TRUE);
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end
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endgenerate
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// On the last refill cycle set the valid bit, for all other writes it should be cleared
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assign tmem_write_data[`LM32_IC_TAGS_VALID_RNG] = last_refill & !flushing;
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assign tmem_write_data[`LM32_IC_TAGS_TAG_RNG] = refill_address[`LM32_IC_ADDR_TAG_RNG];
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// Signals that indicate which state we are in
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assign flushing = |state[1:0];
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assign check = state[2];
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assign refill = state[3];
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assign miss = (~(|way_match)) && (read_enable_f == `TRUE) && (stall_f == `FALSE);
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assign stall_request = (check == `FALSE);
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assign refill_request = (refill == `TRUE);
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/////////////////////////////////////////////////////
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// Sequential logic
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/////////////////////////////////////////////////////
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// Record way selected for replacement on a cache miss
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generate
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if (associativity >= 2)
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begin : way_select
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always @(posedge clk_i `CFG_RESET_SENSITIVITY)
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begin
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if (rst_i == `TRUE)
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refill_way_select <= {{associativity-1{1'b0}}, 1'b1};
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else
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begin
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if (miss == `TRUE)
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refill_way_select <= {refill_way_select[0], refill_way_select[1]};
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end
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end
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end
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endgenerate
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// Record whether we are refilling
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always @(posedge clk_i `CFG_RESET_SENSITIVITY)
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begin
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if (rst_i == `TRUE)
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refilling <= `FALSE;
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else
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refilling <= refill;
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end
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// Instruction cache control FSM
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always @(posedge clk_i `CFG_RESET_SENSITIVITY)
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begin
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if (rst_i == `TRUE)
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begin
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state <= `LM32_IC_STATE_FLUSH_INIT;
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flush_set <= {`LM32_IC_TMEM_ADDR_WIDTH{1'b1}};
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refill_address <= {`LM32_PC_WIDTH{1'bx}};
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restart_request <= `FALSE;
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end
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else
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begin
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case (state)
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// Flush the cache for the first time after reset
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`LM32_IC_STATE_FLUSH_INIT:
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begin
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if (flush_set == {`LM32_IC_TMEM_ADDR_WIDTH{1'b0}})
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state <= `LM32_IC_STATE_CHECK;
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|
|
flush_set <= flush_set - 1'b1;
|
350 |
|
|
end
|
351 |
|
|
|
352 |
|
|
// Flush the cache in response to an write to the ICC CSR
|
353 |
|
|
`LM32_IC_STATE_FLUSH:
|
354 |
|
|
begin
|
355 |
|
|
if (flush_set == {`LM32_IC_TMEM_ADDR_WIDTH{1'b0}})
|
356 |
|
|
state <= `LM32_IC_STATE_REFILL;
|
357 |
|
|
flush_set <= flush_set - 1'b1;
|
358 |
|
|
end
|
359 |
|
|
|
360 |
|
|
// Check for cache misses
|
361 |
|
|
`LM32_IC_STATE_CHECK:
|
362 |
|
|
begin
|
363 |
|
|
if (stall_a == `FALSE)
|
364 |
|
|
restart_request <= `FALSE;
|
365 |
|
|
if (iflush == `TRUE)
|
366 |
|
|
begin
|
367 |
|
|
refill_address <= address_f;
|
368 |
|
|
state <= `LM32_IC_STATE_FLUSH;
|
369 |
|
|
end
|
370 |
|
|
else if (miss == `TRUE)
|
371 |
|
|
begin
|
372 |
|
|
refill_address <= address_f;
|
373 |
|
|
state <= `LM32_IC_STATE_REFILL;
|
374 |
|
|
end
|
375 |
|
|
end
|
376 |
|
|
|
377 |
|
|
// Refill a cache line
|
378 |
|
|
`LM32_IC_STATE_REFILL:
|
379 |
|
|
begin
|
380 |
|
|
if (refill_ready == `TRUE)
|
381 |
|
|
begin
|
382 |
|
|
if (last_refill == `TRUE)
|
383 |
|
|
begin
|
384 |
|
|
restart_request <= `TRUE;
|
385 |
|
|
state <= `LM32_IC_STATE_CHECK;
|
386 |
|
|
end
|
387 |
|
|
end
|
388 |
|
|
end
|
389 |
|
|
|
390 |
|
|
endcase
|
391 |
|
|
end
|
392 |
|
|
end
|
393 |
|
|
|
394 |
|
|
generate
|
395 |
|
|
if (bytes_per_line > 4)
|
396 |
|
|
begin : refilof1
|
397 |
|
|
// Refill offset
|
398 |
|
|
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
|
399 |
|
|
begin
|
400 |
|
|
if (rst_i == `TRUE)
|
401 |
|
|
refill_offset <= {addr_offset_width{1'b0}};
|
402 |
|
|
else
|
403 |
|
|
begin
|
404 |
|
|
case (state)
|
405 |
|
|
|
406 |
|
|
// Check for cache misses
|
407 |
|
|
`LM32_IC_STATE_CHECK:
|
408 |
|
|
begin
|
409 |
|
|
if (iflush == `TRUE)
|
410 |
|
|
refill_offset <= {addr_offset_width{1'b0}};
|
411 |
|
|
else if (miss == `TRUE)
|
412 |
|
|
refill_offset <= {addr_offset_width{1'b0}};
|
413 |
|
|
end
|
414 |
|
|
|
415 |
|
|
// Refill a cache line
|
416 |
|
|
`LM32_IC_STATE_REFILL:
|
417 |
|
|
begin
|
418 |
|
|
if (refill_ready == `TRUE)
|
419 |
|
|
refill_offset <= refill_offset + 1'b1;
|
420 |
|
|
end
|
421 |
|
|
|
422 |
|
|
endcase
|
423 |
|
|
end
|
424 |
|
|
end
|
425 |
|
|
end
|
426 |
|
|
endgenerate
|
427 |
|
|
|
428 |
|
|
endmodule
|