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Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [lm32/] [verilog/] [src/] [lm32_include.v] - Blame information for rev 17

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// =============================================================================
//                           COPYRIGHT NOTICE
// Copyright 2006 (c) Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// This confidential and proprietary software may be used only as authorised by
// a licensing agreement from Lattice Semiconductor Corporation.
// The entire notice above must be reproduced on all authorized copies and
// copies may only be made to the extent permitted by a licensing agreement from
// Lattice Semiconductor Corporation.
//
// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
// 5555 NE Moore Court                            408-826-6000 (other locations)
// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
// U.S.A                                   email: techsupport@latticesemi.com
// =============================================================================/
//                         FILE DETAILS
// Project          : LatticeMico32
// File             : lm32_include.v
// Title            : CPU global macros
// Version          : 6.1.17
// =============================================================================
 
`ifdef LM32_INCLUDE_V
`else
`define LM32_INCLUDE_V
 
// Configuration options
`include "system_conf.v"
 
`ifdef TRUE
`else
`define TRUE    1'b1
`define FALSE   1'b0
`define TRUE_N  1'b0
`define FALSE_N 1'b1
`endif
 
// Wishbone configuration
`define CFG_IWB_ENABLED
`define CFG_DWB_ENABLED
 
// Data-path width
`define LM32_WORD_WIDTH                 32
`define LM32_WORD_RNG                   (`LM32_WORD_WIDTH-1):0
`define LM32_SHIFT_WIDTH                5
`define LM32_SHIFT_RNG                  (`LM32_SHIFT_WIDTH-1):0
`define LM32_BYTE_SELECT_WIDTH          4
`define LM32_BYTE_SELECT_RNG            (`LM32_BYTE_SELECT_WIDTH-1):0
 
// Register file size
`define LM32_REGISTERS                  32
`define LM32_REG_IDX_WIDTH              5
`define LM32_REG_IDX_RNG                (`LM32_REG_IDX_WIDTH-1):0
 
// Standard register numbers
`define LM32_RA_REG                     `LM32_REG_IDX_WIDTH'd29
`define LM32_EA_REG                     `LM32_REG_IDX_WIDTH'd30
`define LM32_BA_REG                     `LM32_REG_IDX_WIDTH'd31
 
// Range of Program Counter. Two LSBs are always 0. 
`ifdef CFG_ICACHE_ENABLED
// XXX `define LM32_PC_WIDTH                   (clogb2(`CFG_ICACHE_LIMIT-`CFG_ICACHE_BASE_ADDRESS)-2) XXX
`define LM32_PC_WIDTH                   30
`else
`ifdef CFG_IWB_ENABLED
`define LM32_PC_WIDTH                   (`LM32_WORD_WIDTH-2)
`else
`define LM32_PC_WIDTH                   `LM32_IROM_ADDRESS_WIDTH
`endif
`endif
`define LM32_PC_RNG                     (`LM32_PC_WIDTH+2-1):2
 
// Range of an instruction
`define LM32_INSTRUCTION_WIDTH          32
`define LM32_INSTRUCTION_RNG            (`LM32_INSTRUCTION_WIDTH-1):0
 
// Adder operation
`define LM32_ADDER_OP_ADD               1'b0
`define LM32_ADDER_OP_SUBTRACT          1'b1
 
// Shift direction
`define LM32_SHIFT_OP_RIGHT             1'b0
`define LM32_SHIFT_OP_LEFT              1'b1
 
// Currently always enabled
`define CFG_BUS_ERRORS_ENABLED
 
// Derive macro that indicates whether we have single-stepping or not
`ifdef CFG_ROM_DEBUG_ENABLED
`define LM32_SINGLE_STEP_ENABLED
`else
`ifdef CFG_HW_DEBUG_ENABLED
`define LM32_SINGLE_STEP_ENABLED
`endif
`endif
 
// Derive macro that indicates whether JTAG interface is required
`ifdef CFG_JTAG_UART_ENABLED
`define LM32_JTAG_ENABLED
`else
`ifdef CFG_DEBUG_ENABLED
`define LM32_JTAG_ENABLED
`else
`endif
`endif
 
// Derive macro that indicates whether we have a barrel-shifter or not
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
`define LM32_BARREL_SHIFT_ENABLED
`else // CFG_PL_BARREL_SHIFT_ENABLED
`ifdef CFG_MC_BARREL_SHIFT_ENABLED
`define LM32_BARREL_SHIFT_ENABLED
`else
`define LM32_NO_BARREL_SHIFT
`endif
`endif // CFG_PL_BARREL_SHIFT_ENABLED
 
// Derive macro that indicates whether we have a multiplier or not
`ifdef CFG_PL_MULTIPLY_ENABLED
`define LM32_MULTIPLY_ENABLED
`else
`ifdef CFG_MC_MULTIPLY_ENABLED
`define LM32_MULTIPLY_ENABLED
`endif
`endif
 
// Derive a macro that indicates whether or not the multi-cycle arithmetic unit is required
`ifdef CFG_MC_DIVIDE_ENABLED
`define LM32_MC_ARITHMETIC_ENABLED
`endif
`ifdef CFG_MC_MULTIPLY_ENABLED
`define LM32_MC_ARITHMETIC_ENABLED
`endif
`ifdef CFG_MC_BARREL_SHIFT_ENABLED
`define LM32_MC_ARITHMETIC_ENABLED
`endif
 
// Derive macro that indicates if we are using an EBR register file
`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
`define LM32_EBR_REGISTER_FILE
`endif
`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
`define LM32_EBR_REGISTER_FILE
`endif
 
// Revision number
`define LM32_REVISION                   6'h11
 
// Logical operations - Function encoded directly in instruction
`define LM32_LOGIC_OP_RNG               3:0
 
// Conditions for conditional branches
`define LM32_CONDITION_WIDTH            3
`define LM32_CONDITION_RNG              (`LM32_CONDITION_WIDTH-1):0
`define LM32_CONDITION_E                3'b001
`define LM32_CONDITION_G                3'b010
`define LM32_CONDITION_GE               3'b011
`define LM32_CONDITION_GEU              3'b100
`define LM32_CONDITION_GU               3'b101
`define LM32_CONDITION_NE               3'b111
`define LM32_CONDITION_U1               3'b000
`define LM32_CONDITION_U2               3'b110
 
// Size of load or store instruction - Encoding corresponds to opcode
`define LM32_SIZE_WIDTH                 2
`define LM32_SIZE_RNG                   1:0
`define LM32_SIZE_BYTE                  2'b00
`define LM32_SIZE_HWORD                 2'b11
`define LM32_SIZE_WORD                  2'b10
`define LM32_ADDRESS_LSBS_WIDTH         2
 
// Width and range of a CSR index
`ifdef CFG_DEBUG_ENABLED
`define LM32_CSR_WIDTH                  5
`define LM32_CSR_RNG                    (`LM32_CSR_WIDTH-1):0
`else
`ifdef CFG_JTAG_ENABLED
`define LM32_CSR_WIDTH                  4
`define LM32_CSR_RNG                    (`LM32_CSR_WIDTH-1):0
`else
`define LM32_CSR_WIDTH                  3
`define LM32_CSR_RNG                    (`LM32_CSR_WIDTH-1):0
`endif
`endif
 
// CSR indices
`define LM32_CSR_IE                     `LM32_CSR_WIDTH'h0
`define LM32_CSR_IM                     `LM32_CSR_WIDTH'h1
`define LM32_CSR_IP                     `LM32_CSR_WIDTH'h2
`define LM32_CSR_ICC                    `LM32_CSR_WIDTH'h3
`define LM32_CSR_DCC                    `LM32_CSR_WIDTH'h4
`define LM32_CSR_CC                     `LM32_CSR_WIDTH'h5
`define LM32_CSR_CFG                    `LM32_CSR_WIDTH'h6
`define LM32_CSR_EBA                    `LM32_CSR_WIDTH'h7
`ifdef CFG_DEBUG_ENABLED
`define LM32_CSR_DC                     `LM32_CSR_WIDTH'h8
`define LM32_CSR_DEBA                   `LM32_CSR_WIDTH'h9
`endif
`ifdef CFG_JTAG_ENABLED
`define LM32_CSR_JTX                    `LM32_CSR_WIDTH'he
`define LM32_CSR_JRX                    `LM32_CSR_WIDTH'hf
`endif
`ifdef CFG_DEBUG_ENABLED
`define LM32_CSR_BP0                    `LM32_CSR_WIDTH'h10
`define LM32_CSR_BP1                    `LM32_CSR_WIDTH'h11
`define LM32_CSR_BP2                    `LM32_CSR_WIDTH'h12
`define LM32_CSR_BP3                    `LM32_CSR_WIDTH'h13
`define LM32_CSR_WP0                    `LM32_CSR_WIDTH'h18
`define LM32_CSR_WP1                    `LM32_CSR_WIDTH'h19
`define LM32_CSR_WP2                    `LM32_CSR_WIDTH'h1a
`define LM32_CSR_WP3                    `LM32_CSR_WIDTH'h1b
`endif
 
// Values for WPC CSR
`define LM32_WPC_C_RNG                  1:0
`define LM32_WPC_C_DISABLED             2'b00
`define LM32_WPC_C_READ                 2'b01
`define LM32_WPC_C_WRITE                2'b10
`define LM32_WPC_C_READ_WRITE           2'b11
 
// Exception IDs
`define LM32_EID_WIDTH                  3
`define LM32_EID_RNG                    (`LM32_EID_WIDTH-1):0
`define LM32_EID_RESET                  3'h0
`define LM32_EID_BREAKPOINT             3'd1
`define LM32_EID_INST_BUS_ERROR         3'h2
`define LM32_EID_WATCHPOINT             3'd3
`define LM32_EID_DATA_BUS_ERROR         3'h4
`define LM32_EID_DIVIDE_BY_ZERO         3'h5
`define LM32_EID_INTERRUPT              3'h6
`define LM32_EID_SCALL                  3'h7
 
// Pipeline result selection mux controls
 
`define LM32_D_RESULT_SEL_0_RNG          0:0
`define LM32_D_RESULT_SEL_0_REG_0        1'b0
`define LM32_D_RESULT_SEL_0_NEXT_PC      1'b1
 
`define LM32_D_RESULT_SEL_1_RNG          1:0
`define LM32_D_RESULT_SEL_1_ZERO         2'b00
`define LM32_D_RESULT_SEL_1_REG_1        2'b01
`define LM32_D_RESULT_SEL_1_IMMEDIATE    2'b10
 
`define LM32_USER_OPCODE_WIDTH           11
`define LM32_USER_OPCODE_RNG             (`LM32_USER_OPCODE_WIDTH-1):0
 
// Derive a macro to indicate if either of the caches are implemented
`ifdef CFG_ICACHE_ENABLED
`define LM32_CACHE_ENABLED
`else
`ifdef CFG_DCACHE_ENABLED
`define LM32_CACHE_ENABLED
`endif
`endif
 
/////////////////////////////////////////////////////
// Interrupts
/////////////////////////////////////////////////////
 
// Always enable interrupts
`define CFG_INTERRUPTS_ENABLED
 
// Currently this is fixed to 32 and should not be changed
`define CFG_INTERRUPTS                  32
`define LM32_INTERRUPT_WIDTH            `CFG_INTERRUPTS
`define LM32_INTERRUPT_RNG              (`LM32_INTERRUPT_WIDTH-1):0
 
/////////////////////////////////////////////////////
// General
/////////////////////////////////////////////////////
 
// Sub-word range types
`define LM32_BYTE_WIDTH                 8
`define LM32_BYTE_RNG                   7:0
`define LM32_HWORD_WIDTH                16
`define LM32_HWORD_RNG                  15:0
 
// Word sub-byte indicies
`define LM32_BYTE_0_RNG                  7:0
`define LM32_BYTE_1_RNG                  15:8
`define LM32_BYTE_2_RNG                  23:16
`define LM32_BYTE_3_RNG                  31:24
 
// Word sub-halfword indices
`define LM32_HWORD_0_RNG                 15:0
`define LM32_HWORD_1_RNG                 31:16
 
// Use an asynchronous reset
// To use a synchronous reset, define this macro as nothing
`define CFG_RESET_SENSITIVITY or posedge rst_i
 
// V.T. Srce
`define SRCE
 
// Whether to include context registers for debug exceptions
// in addition to standard exception handling registers
// Bizarre - Removing this increases LUT count!
`define CFG_DEBUG_EXCEPTIONS_ENABLED
 
// Wishbone defines 
// Refer to Wishbone System-on-Chip Interconnection Architecture
// These should probably be moved to a Wishbone common file
 
// Wishbone cycle types
`define LM32_CTYPE_WIDTH                3
`define LM32_CTYPE_RNG                  (`LM32_CTYPE_WIDTH-1):0
`define LM32_CTYPE_CLASSIC              3'b000
`define LM32_CTYPE_CONSTANT             3'b001
`define LM32_CTYPE_INCREMENTING         3'b010
`define LM32_CTYPE_END                  3'b111
 
// Wishbone burst types
`define LM32_BTYPE_WIDTH                2
`define LM32_BTYPE_RNG                  (`LM32_BTYPE_WIDTH-1):0
`define LM32_BTYPE_LINEAR               2'b00
`define LM32_BTYPE_4_BEAT               2'b01
`define LM32_BTYPE_8_BEAT               2'b10
`define LM32_BTYPE_16_BEAT              2'b11
 
`endif

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Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [lm32/] [verilog/] [src/] [lm32_include.v] - Blame information for rev 17

Line No.	Rev	Author	Line
1	17	alirezamon	`// =============================================================================`
2			`// COPYRIGHT NOTICE`
3			`// Copyright 2006 (c) Lattice Semiconductor Corporation`
4			`// ALL RIGHTS RESERVED`
5			`// This confidential and proprietary software may be used only as authorised by`
6			`// a licensing agreement from Lattice Semiconductor Corporation.`
7			`// The entire notice above must be reproduced on all authorized copies and`
8			`// copies may only be made to the extent permitted by a licensing agreement from`
9			`// Lattice Semiconductor Corporation.`
10			`//`
11			`// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)`
12			`// 5555 NE Moore Court 408-826-6000 (other locations)`
13			`// Hillsboro, OR 97124 web : http://www.latticesemi.com/`
14			`// U.S.A email: techsupport@latticesemi.com`
15			`// =============================================================================/`
16			`// FILE DETAILS`
17			`// Project : LatticeMico32`
18			`// File : lm32_include.v`
19			`// Title : CPU global macros`
20			`// Version : 6.1.17`
21			`// =============================================================================`
22
23			`ifdef LM32_INCLUDE_V
24			`else
25			`define LM32_INCLUDE_V
26
27			`// Configuration options`
28			`include "system_conf.v"
29
30			`ifdef TRUE
31			`else
32			`define TRUE 1'b1
33			`define FALSE 1'b0
34			`define TRUE_N 1'b0
35			`define FALSE_N 1'b1
36			`endif
37
38			`// Wishbone configuration`
39			`define CFG_IWB_ENABLED
40			`define CFG_DWB_ENABLED
41
42			`// Data-path width`
43			`define LM32_WORD_WIDTH 32
44			`define LM32_WORD_RNG (`LM32_WORD_WIDTH-1):0
45			`define LM32_SHIFT_WIDTH 5
46			`define LM32_SHIFT_RNG (`LM32_SHIFT_WIDTH-1):0
47			`define LM32_BYTE_SELECT_WIDTH 4
48			`define LM32_BYTE_SELECT_RNG (`LM32_BYTE_SELECT_WIDTH-1):0
49
50			`// Register file size`
51			`define LM32_REGISTERS 32
52			`define LM32_REG_IDX_WIDTH 5
53			`define LM32_REG_IDX_RNG (`LM32_REG_IDX_WIDTH-1):0
54
55			`// Standard register numbers`
56			`define LM32_RA_REG `LM32_REG_IDX_WIDTH'd29
57			`define LM32_EA_REG `LM32_REG_IDX_WIDTH'd30
58			`define LM32_BA_REG `LM32_REG_IDX_WIDTH'd31
59
60			`// Range of Program Counter. Two LSBs are always 0.`
61			`ifdef CFG_ICACHE_ENABLED
62			// XXX `define LM32_PC_WIDTH (clogb2(`CFG_ICACHE_LIMIT-`CFG_ICACHE_BASE_ADDRESS)-2) XXX
63			`define LM32_PC_WIDTH 30
64			`else
65			`ifdef CFG_IWB_ENABLED
66			`define LM32_PC_WIDTH (`LM32_WORD_WIDTH-2)
67			`else
68			`define LM32_PC_WIDTH `LM32_IROM_ADDRESS_WIDTH
69			`endif
70			`endif
71			`define LM32_PC_RNG (`LM32_PC_WIDTH+2-1):2
72
73			`// Range of an instruction`
74			`define LM32_INSTRUCTION_WIDTH 32
75			`define LM32_INSTRUCTION_RNG (`LM32_INSTRUCTION_WIDTH-1):0
76
77			`// Adder operation`
78			`define LM32_ADDER_OP_ADD 1'b0
79			`define LM32_ADDER_OP_SUBTRACT 1'b1
80
81			`// Shift direction`
82			`define LM32_SHIFT_OP_RIGHT 1'b0
83			`define LM32_SHIFT_OP_LEFT 1'b1
84
85			`// Currently always enabled`
86			`define CFG_BUS_ERRORS_ENABLED
87
88			`// Derive macro that indicates whether we have single-stepping or not`
89			`ifdef CFG_ROM_DEBUG_ENABLED
90			`define LM32_SINGLE_STEP_ENABLED
91			`else
92			`ifdef CFG_HW_DEBUG_ENABLED
93			`define LM32_SINGLE_STEP_ENABLED
94			`endif
95			`endif
96
97			`// Derive macro that indicates whether JTAG interface is required`
98			`ifdef CFG_JTAG_UART_ENABLED
99			`define LM32_JTAG_ENABLED
100			`else
101			`ifdef CFG_DEBUG_ENABLED
102			`define LM32_JTAG_ENABLED
103			`else
104			`endif
105			`endif
106
107			`// Derive macro that indicates whether we have a barrel-shifter or not`
108			`ifdef CFG_PL_BARREL_SHIFT_ENABLED
109			`define LM32_BARREL_SHIFT_ENABLED
110			`else // CFG_PL_BARREL_SHIFT_ENABLED
111			`ifdef CFG_MC_BARREL_SHIFT_ENABLED
112			`define LM32_BARREL_SHIFT_ENABLED
113			`else
114			`define LM32_NO_BARREL_SHIFT
115			`endif
116			`endif // CFG_PL_BARREL_SHIFT_ENABLED
117
118			`// Derive macro that indicates whether we have a multiplier or not`
119			`ifdef CFG_PL_MULTIPLY_ENABLED
120			`define LM32_MULTIPLY_ENABLED
121			`else
122			`ifdef CFG_MC_MULTIPLY_ENABLED
123			`define LM32_MULTIPLY_ENABLED
124			`endif
125			`endif
126
127			`// Derive a macro that indicates whether or not the multi-cycle arithmetic unit is required`
128			`ifdef CFG_MC_DIVIDE_ENABLED
129			`define LM32_MC_ARITHMETIC_ENABLED
130			`endif
131			`ifdef CFG_MC_MULTIPLY_ENABLED
132			`define LM32_MC_ARITHMETIC_ENABLED
133			`endif
134			`ifdef CFG_MC_BARREL_SHIFT_ENABLED
135			`define LM32_MC_ARITHMETIC_ENABLED
136			`endif
137
138			`// Derive macro that indicates if we are using an EBR register file`
139			`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
140			`define LM32_EBR_REGISTER_FILE
141			`endif
142			`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
143			`define LM32_EBR_REGISTER_FILE
144			`endif
145
146			`// Revision number`
147			`define LM32_REVISION 6'h11
148
149			`// Logical operations - Function encoded directly in instruction`
150			`define LM32_LOGIC_OP_RNG 3:0
151
152			`// Conditions for conditional branches`
153			`define LM32_CONDITION_WIDTH 3
154			`define LM32_CONDITION_RNG (`LM32_CONDITION_WIDTH-1):0
155			`define LM32_CONDITION_E 3'b001
156			`define LM32_CONDITION_G 3'b010
157			`define LM32_CONDITION_GE 3'b011
158			`define LM32_CONDITION_GEU 3'b100
159			`define LM32_CONDITION_GU 3'b101
160			`define LM32_CONDITION_NE 3'b111
161			`define LM32_CONDITION_U1 3'b000
162			`define LM32_CONDITION_U2 3'b110
163
164			`// Size of load or store instruction - Encoding corresponds to opcode`
165			`define LM32_SIZE_WIDTH 2
166			`define LM32_SIZE_RNG 1:0
167			`define LM32_SIZE_BYTE 2'b00
168			`define LM32_SIZE_HWORD 2'b11
169			`define LM32_SIZE_WORD 2'b10
170			`define LM32_ADDRESS_LSBS_WIDTH 2
171
172			`// Width and range of a CSR index`
173			`ifdef CFG_DEBUG_ENABLED
174			`define LM32_CSR_WIDTH 5
175			`define LM32_CSR_RNG (`LM32_CSR_WIDTH-1):0
176			`else
177			`ifdef CFG_JTAG_ENABLED
178			`define LM32_CSR_WIDTH 4
179			`define LM32_CSR_RNG (`LM32_CSR_WIDTH-1):0
180			`else
181			`define LM32_CSR_WIDTH 3
182			`define LM32_CSR_RNG (`LM32_CSR_WIDTH-1):0
183			`endif
184			`endif
185
186			`// CSR indices`
187			`define LM32_CSR_IE `LM32_CSR_WIDTH'h0
188			`define LM32_CSR_IM `LM32_CSR_WIDTH'h1
189			`define LM32_CSR_IP `LM32_CSR_WIDTH'h2
190			`define LM32_CSR_ICC `LM32_CSR_WIDTH'h3
191			`define LM32_CSR_DCC `LM32_CSR_WIDTH'h4
192			`define LM32_CSR_CC `LM32_CSR_WIDTH'h5
193			`define LM32_CSR_CFG `LM32_CSR_WIDTH'h6
194			`define LM32_CSR_EBA `LM32_CSR_WIDTH'h7
195			`ifdef CFG_DEBUG_ENABLED
196			`define LM32_CSR_DC `LM32_CSR_WIDTH'h8
197			`define LM32_CSR_DEBA `LM32_CSR_WIDTH'h9
198			`endif
199			`ifdef CFG_JTAG_ENABLED
200			`define LM32_CSR_JTX `LM32_CSR_WIDTH'he
201			`define LM32_CSR_JRX `LM32_CSR_WIDTH'hf
202			`endif
203			`ifdef CFG_DEBUG_ENABLED
204			`define LM32_CSR_BP0 `LM32_CSR_WIDTH'h10
205			`define LM32_CSR_BP1 `LM32_CSR_WIDTH'h11
206			`define LM32_CSR_BP2 `LM32_CSR_WIDTH'h12
207			`define LM32_CSR_BP3 `LM32_CSR_WIDTH'h13
208			`define LM32_CSR_WP0 `LM32_CSR_WIDTH'h18
209			`define LM32_CSR_WP1 `LM32_CSR_WIDTH'h19
210			`define LM32_CSR_WP2 `LM32_CSR_WIDTH'h1a
211			`define LM32_CSR_WP3 `LM32_CSR_WIDTH'h1b
212			`endif
213
214			`// Values for WPC CSR`
215			`define LM32_WPC_C_RNG 1:0
216			`define LM32_WPC_C_DISABLED 2'b00
217			`define LM32_WPC_C_READ 2'b01
218			`define LM32_WPC_C_WRITE 2'b10
219			`define LM32_WPC_C_READ_WRITE 2'b11
220
221			`// Exception IDs`
222			`define LM32_EID_WIDTH 3
223			`define LM32_EID_RNG (`LM32_EID_WIDTH-1):0
224			`define LM32_EID_RESET 3'h0
225			`define LM32_EID_BREAKPOINT 3'd1
226			`define LM32_EID_INST_BUS_ERROR 3'h2
227			`define LM32_EID_WATCHPOINT 3'd3
228			`define LM32_EID_DATA_BUS_ERROR 3'h4
229			`define LM32_EID_DIVIDE_BY_ZERO 3'h5
230			`define LM32_EID_INTERRUPT 3'h6
231			`define LM32_EID_SCALL 3'h7
232
233			`// Pipeline result selection mux controls`
234
235			`define LM32_D_RESULT_SEL_0_RNG 0:0
236			`define LM32_D_RESULT_SEL_0_REG_0 1'b0
237			`define LM32_D_RESULT_SEL_0_NEXT_PC 1'b1
238
239			`define LM32_D_RESULT_SEL_1_RNG 1:0
240			`define LM32_D_RESULT_SEL_1_ZERO 2'b00
241			`define LM32_D_RESULT_SEL_1_REG_1 2'b01
242			`define LM32_D_RESULT_SEL_1_IMMEDIATE 2'b10
243
244			`define LM32_USER_OPCODE_WIDTH 11
245			`define LM32_USER_OPCODE_RNG (`LM32_USER_OPCODE_WIDTH-1):0
246
247			`// Derive a macro to indicate if either of the caches are implemented`
248			`ifdef CFG_ICACHE_ENABLED
249			`define LM32_CACHE_ENABLED
250			`else
251			`ifdef CFG_DCACHE_ENABLED
252			`define LM32_CACHE_ENABLED
253			`endif
254			`endif
255
256			`/////////////////////////////////////////////////////`
257			`// Interrupts`
258			`/////////////////////////////////////////////////////`
259
260			`// Always enable interrupts`
261			`define CFG_INTERRUPTS_ENABLED
262
263			`// Currently this is fixed to 32 and should not be changed`
264			`define CFG_INTERRUPTS 32
265			`define LM32_INTERRUPT_WIDTH `CFG_INTERRUPTS
266			`define LM32_INTERRUPT_RNG (`LM32_INTERRUPT_WIDTH-1):0
267
268			`/////////////////////////////////////////////////////`
269			`// General`
270			`/////////////////////////////////////////////////////`
271
272			`// Sub-word range types`
273			`define LM32_BYTE_WIDTH 8
274			`define LM32_BYTE_RNG 7:0
275			`define LM32_HWORD_WIDTH 16
276			`define LM32_HWORD_RNG 15:0
277
278			`// Word sub-byte indicies`
279			`define LM32_BYTE_0_RNG 7:0
280			`define LM32_BYTE_1_RNG 15:8
281			`define LM32_BYTE_2_RNG 23:16
282			`define LM32_BYTE_3_RNG 31:24
283
284			`// Word sub-halfword indices`
285			`define LM32_HWORD_0_RNG 15:0
286			`define LM32_HWORD_1_RNG 31:16
287
288			`// Use an asynchronous reset`
289			`// To use a synchronous reset, define this macro as nothing`
290			`define CFG_RESET_SENSITIVITY or posedge rst_i
291
292			`// V.T. Srce`
293			`define SRCE
294
295			`// Whether to include context registers for debug exceptions`
296			`// in addition to standard exception handling registers`
297			`// Bizarre - Removing this increases LUT count!`
298			`define CFG_DEBUG_EXCEPTIONS_ENABLED
299
300			`// Wishbone defines`
301			`// Refer to Wishbone System-on-Chip Interconnection Architecture`
302			`// These should probably be moved to a Wishbone common file`
303
304			`// Wishbone cycle types`
305			`define LM32_CTYPE_WIDTH 3
306			`define LM32_CTYPE_RNG (`LM32_CTYPE_WIDTH-1):0
307			`define LM32_CTYPE_CLASSIC 3'b000
308			`define LM32_CTYPE_CONSTANT 3'b001
309			`define LM32_CTYPE_INCREMENTING 3'b010
310			`define LM32_CTYPE_END 3'b111
311
312			`// Wishbone burst types`
313			`define LM32_BTYPE_WIDTH 2
314			`define LM32_BTYPE_RNG (`LM32_BTYPE_WIDTH-1):0
315			`define LM32_BTYPE_LINEAR 2'b00
316			`define LM32_BTYPE_4_BEAT 2'b01
317			`define LM32_BTYPE_8_BEAT 2'b10
318			`define LM32_BTYPE_16_BEAT 2'b11
319
320			`endif