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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [lm32/] [verilog/] [src/] [lm32_include.v] - Blame information for rev 17

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1 17 alirezamon
// =============================================================================
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//                           COPYRIGHT NOTICE
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// Copyright 2006 (c) Lattice Semiconductor Corporation
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// ALL RIGHTS RESERVED
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// This confidential and proprietary software may be used only as authorised by
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// a licensing agreement from Lattice Semiconductor Corporation.
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// The entire notice above must be reproduced on all authorized copies and
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// copies may only be made to the extent permitted by a licensing agreement from
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// Lattice Semiconductor Corporation.
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//
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// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
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// 5555 NE Moore Court                            408-826-6000 (other locations)
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// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
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// U.S.A                                   email: techsupport@latticesemi.com
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// =============================================================================/
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//                         FILE DETAILS
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// Project          : LatticeMico32
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// File             : lm32_include.v
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// Title            : CPU global macros
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// Version          : 6.1.17
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// =============================================================================
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`ifdef LM32_INCLUDE_V
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`else
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`define LM32_INCLUDE_V
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// Configuration options
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`include "system_conf.v"
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30
`ifdef TRUE
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`else
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`define TRUE    1'b1
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`define FALSE   1'b0
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`define TRUE_N  1'b0
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`define FALSE_N 1'b1
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`endif
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38
// Wishbone configuration
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`define CFG_IWB_ENABLED
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`define CFG_DWB_ENABLED
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42
// Data-path width
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`define LM32_WORD_WIDTH                 32
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`define LM32_WORD_RNG                   (`LM32_WORD_WIDTH-1):0
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`define LM32_SHIFT_WIDTH                5
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`define LM32_SHIFT_RNG                  (`LM32_SHIFT_WIDTH-1):0
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`define LM32_BYTE_SELECT_WIDTH          4
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`define LM32_BYTE_SELECT_RNG            (`LM32_BYTE_SELECT_WIDTH-1):0
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// Register file size
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`define LM32_REGISTERS                  32
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`define LM32_REG_IDX_WIDTH              5
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`define LM32_REG_IDX_RNG                (`LM32_REG_IDX_WIDTH-1):0
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// Standard register numbers
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`define LM32_RA_REG                     `LM32_REG_IDX_WIDTH'd29
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`define LM32_EA_REG                     `LM32_REG_IDX_WIDTH'd30
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`define LM32_BA_REG                     `LM32_REG_IDX_WIDTH'd31
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// Range of Program Counter. Two LSBs are always 0. 
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`ifdef CFG_ICACHE_ENABLED
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// XXX `define LM32_PC_WIDTH                   (clogb2(`CFG_ICACHE_LIMIT-`CFG_ICACHE_BASE_ADDRESS)-2) XXX
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`define LM32_PC_WIDTH                   30
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`else
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`ifdef CFG_IWB_ENABLED
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`define LM32_PC_WIDTH                   (`LM32_WORD_WIDTH-2)
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`else
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`define LM32_PC_WIDTH                   `LM32_IROM_ADDRESS_WIDTH
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`endif
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`endif
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`define LM32_PC_RNG                     (`LM32_PC_WIDTH+2-1):2
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// Range of an instruction
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`define LM32_INSTRUCTION_WIDTH          32
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`define LM32_INSTRUCTION_RNG            (`LM32_INSTRUCTION_WIDTH-1):0
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// Adder operation
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`define LM32_ADDER_OP_ADD               1'b0
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`define LM32_ADDER_OP_SUBTRACT          1'b1
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81
// Shift direction
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`define LM32_SHIFT_OP_RIGHT             1'b0
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`define LM32_SHIFT_OP_LEFT              1'b1
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85
// Currently always enabled
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`define CFG_BUS_ERRORS_ENABLED
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// Derive macro that indicates whether we have single-stepping or not
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`ifdef CFG_ROM_DEBUG_ENABLED
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`define LM32_SINGLE_STEP_ENABLED
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`else
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`ifdef CFG_HW_DEBUG_ENABLED
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`define LM32_SINGLE_STEP_ENABLED
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`endif
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`endif
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// Derive macro that indicates whether JTAG interface is required
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`ifdef CFG_JTAG_UART_ENABLED
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`define LM32_JTAG_ENABLED
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`else
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`ifdef CFG_DEBUG_ENABLED
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`define LM32_JTAG_ENABLED
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`else
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`endif
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`endif
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// Derive macro that indicates whether we have a barrel-shifter or not
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`ifdef CFG_PL_BARREL_SHIFT_ENABLED
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`define LM32_BARREL_SHIFT_ENABLED
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`else // CFG_PL_BARREL_SHIFT_ENABLED
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`ifdef CFG_MC_BARREL_SHIFT_ENABLED
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`define LM32_BARREL_SHIFT_ENABLED
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`else
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`define LM32_NO_BARREL_SHIFT
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`endif
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`endif // CFG_PL_BARREL_SHIFT_ENABLED
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// Derive macro that indicates whether we have a multiplier or not
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`ifdef CFG_PL_MULTIPLY_ENABLED
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`define LM32_MULTIPLY_ENABLED
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`else
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`ifdef CFG_MC_MULTIPLY_ENABLED
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`define LM32_MULTIPLY_ENABLED
124
`endif
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`endif
126
 
127
// Derive a macro that indicates whether or not the multi-cycle arithmetic unit is required
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`ifdef CFG_MC_DIVIDE_ENABLED
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`define LM32_MC_ARITHMETIC_ENABLED
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`endif
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`ifdef CFG_MC_MULTIPLY_ENABLED
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`define LM32_MC_ARITHMETIC_ENABLED
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`endif
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`ifdef CFG_MC_BARREL_SHIFT_ENABLED
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`define LM32_MC_ARITHMETIC_ENABLED
136
`endif
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138
// Derive macro that indicates if we are using an EBR register file
139
`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
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`define LM32_EBR_REGISTER_FILE
141
`endif
142
`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
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`define LM32_EBR_REGISTER_FILE
144
`endif
145
 
146
// Revision number
147
`define LM32_REVISION                   6'h11
148
 
149
// Logical operations - Function encoded directly in instruction
150
`define LM32_LOGIC_OP_RNG               3:0
151
 
152
// Conditions for conditional branches
153
`define LM32_CONDITION_WIDTH            3
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`define LM32_CONDITION_RNG              (`LM32_CONDITION_WIDTH-1):0
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`define LM32_CONDITION_E                3'b001
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`define LM32_CONDITION_G                3'b010
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`define LM32_CONDITION_GE               3'b011
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`define LM32_CONDITION_GEU              3'b100
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`define LM32_CONDITION_GU               3'b101
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`define LM32_CONDITION_NE               3'b111
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`define LM32_CONDITION_U1               3'b000
162
`define LM32_CONDITION_U2               3'b110
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164
// Size of load or store instruction - Encoding corresponds to opcode
165
`define LM32_SIZE_WIDTH                 2
166
`define LM32_SIZE_RNG                   1:0
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`define LM32_SIZE_BYTE                  2'b00
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`define LM32_SIZE_HWORD                 2'b11
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`define LM32_SIZE_WORD                  2'b10
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`define LM32_ADDRESS_LSBS_WIDTH         2
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172
// Width and range of a CSR index
173
`ifdef CFG_DEBUG_ENABLED
174
`define LM32_CSR_WIDTH                  5
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`define LM32_CSR_RNG                    (`LM32_CSR_WIDTH-1):0
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`else
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`ifdef CFG_JTAG_ENABLED
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`define LM32_CSR_WIDTH                  4
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`define LM32_CSR_RNG                    (`LM32_CSR_WIDTH-1):0
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`else
181
`define LM32_CSR_WIDTH                  3
182
`define LM32_CSR_RNG                    (`LM32_CSR_WIDTH-1):0
183
`endif
184
`endif
185
 
186
// CSR indices
187
`define LM32_CSR_IE                     `LM32_CSR_WIDTH'h0
188
`define LM32_CSR_IM                     `LM32_CSR_WIDTH'h1
189
`define LM32_CSR_IP                     `LM32_CSR_WIDTH'h2
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`define LM32_CSR_ICC                    `LM32_CSR_WIDTH'h3
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`define LM32_CSR_DCC                    `LM32_CSR_WIDTH'h4
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`define LM32_CSR_CC                     `LM32_CSR_WIDTH'h5
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`define LM32_CSR_CFG                    `LM32_CSR_WIDTH'h6
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`define LM32_CSR_EBA                    `LM32_CSR_WIDTH'h7
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`ifdef CFG_DEBUG_ENABLED
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`define LM32_CSR_DC                     `LM32_CSR_WIDTH'h8
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`define LM32_CSR_DEBA                   `LM32_CSR_WIDTH'h9
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`endif
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`ifdef CFG_JTAG_ENABLED
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`define LM32_CSR_JTX                    `LM32_CSR_WIDTH'he
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`define LM32_CSR_JRX                    `LM32_CSR_WIDTH'hf
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`endif
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`ifdef CFG_DEBUG_ENABLED
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`define LM32_CSR_BP0                    `LM32_CSR_WIDTH'h10
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`define LM32_CSR_BP1                    `LM32_CSR_WIDTH'h11
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`define LM32_CSR_BP2                    `LM32_CSR_WIDTH'h12
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`define LM32_CSR_BP3                    `LM32_CSR_WIDTH'h13
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`define LM32_CSR_WP0                    `LM32_CSR_WIDTH'h18
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`define LM32_CSR_WP1                    `LM32_CSR_WIDTH'h19
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`define LM32_CSR_WP2                    `LM32_CSR_WIDTH'h1a
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`define LM32_CSR_WP3                    `LM32_CSR_WIDTH'h1b
212
`endif
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// Values for WPC CSR
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`define LM32_WPC_C_RNG                  1:0
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`define LM32_WPC_C_DISABLED             2'b00
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`define LM32_WPC_C_READ                 2'b01
218
`define LM32_WPC_C_WRITE                2'b10
219
`define LM32_WPC_C_READ_WRITE           2'b11
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// Exception IDs
222
`define LM32_EID_WIDTH                  3
223
`define LM32_EID_RNG                    (`LM32_EID_WIDTH-1):0
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`define LM32_EID_RESET                  3'h0
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`define LM32_EID_BREAKPOINT             3'd1
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`define LM32_EID_INST_BUS_ERROR         3'h2
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`define LM32_EID_WATCHPOINT             3'd3
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`define LM32_EID_DATA_BUS_ERROR         3'h4
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`define LM32_EID_DIVIDE_BY_ZERO         3'h5
230
`define LM32_EID_INTERRUPT              3'h6
231
`define LM32_EID_SCALL                  3'h7
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233
// Pipeline result selection mux controls
234
 
235
`define LM32_D_RESULT_SEL_0_RNG          0:0
236
`define LM32_D_RESULT_SEL_0_REG_0        1'b0
237
`define LM32_D_RESULT_SEL_0_NEXT_PC      1'b1
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`define LM32_D_RESULT_SEL_1_RNG          1:0
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`define LM32_D_RESULT_SEL_1_ZERO         2'b00
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`define LM32_D_RESULT_SEL_1_REG_1        2'b01
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`define LM32_D_RESULT_SEL_1_IMMEDIATE    2'b10
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244
`define LM32_USER_OPCODE_WIDTH           11
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`define LM32_USER_OPCODE_RNG             (`LM32_USER_OPCODE_WIDTH-1):0
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// Derive a macro to indicate if either of the caches are implemented
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`ifdef CFG_ICACHE_ENABLED
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`define LM32_CACHE_ENABLED
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`else
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`ifdef CFG_DCACHE_ENABLED
252
`define LM32_CACHE_ENABLED
253
`endif
254
`endif
255
 
256
/////////////////////////////////////////////////////
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// Interrupts
258
/////////////////////////////////////////////////////
259
 
260
// Always enable interrupts
261
`define CFG_INTERRUPTS_ENABLED
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263
// Currently this is fixed to 32 and should not be changed
264
`define CFG_INTERRUPTS                  32
265
`define LM32_INTERRUPT_WIDTH            `CFG_INTERRUPTS
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`define LM32_INTERRUPT_RNG              (`LM32_INTERRUPT_WIDTH-1):0
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268
/////////////////////////////////////////////////////
269
// General
270
/////////////////////////////////////////////////////
271
 
272
// Sub-word range types
273
`define LM32_BYTE_WIDTH                 8
274
`define LM32_BYTE_RNG                   7:0
275
`define LM32_HWORD_WIDTH                16
276
`define LM32_HWORD_RNG                  15:0
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278
// Word sub-byte indicies
279
`define LM32_BYTE_0_RNG                  7:0
280
`define LM32_BYTE_1_RNG                  15:8
281
`define LM32_BYTE_2_RNG                  23:16
282
`define LM32_BYTE_3_RNG                  31:24
283
 
284
// Word sub-halfword indices
285
`define LM32_HWORD_0_RNG                 15:0
286
`define LM32_HWORD_1_RNG                 31:16
287
 
288
// Use an asynchronous reset
289
// To use a synchronous reset, define this macro as nothing
290
`define CFG_RESET_SENSITIVITY or posedge rst_i
291
 
292
// V.T. Srce
293
`define SRCE
294
 
295
// Whether to include context registers for debug exceptions
296
// in addition to standard exception handling registers
297
// Bizarre - Removing this increases LUT count!
298
`define CFG_DEBUG_EXCEPTIONS_ENABLED
299
 
300
// Wishbone defines 
301
// Refer to Wishbone System-on-Chip Interconnection Architecture
302
// These should probably be moved to a Wishbone common file
303
 
304
// Wishbone cycle types
305
`define LM32_CTYPE_WIDTH                3
306
`define LM32_CTYPE_RNG                  (`LM32_CTYPE_WIDTH-1):0
307
`define LM32_CTYPE_CLASSIC              3'b000
308
`define LM32_CTYPE_CONSTANT             3'b001
309
`define LM32_CTYPE_INCREMENTING         3'b010
310
`define LM32_CTYPE_END                  3'b111
311
 
312
// Wishbone burst types
313
`define LM32_BTYPE_WIDTH                2
314
`define LM32_BTYPE_RNG                  (`LM32_BTYPE_WIDTH-1):0
315
`define LM32_BTYPE_LINEAR               2'b00
316
`define LM32_BTYPE_4_BEAT               2'b01
317
`define LM32_BTYPE_8_BEAT               2'b10
318
`define LM32_BTYPE_16_BEAT              2'b11
319
 
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`endif

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