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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [lm32/] [verilog/] [src/] [lm32_interrupt.v] - Blame information for rev 17

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// =============================================================================
//                           COPYRIGHT NOTICE
// Copyright 2006 (c) Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// This confidential and proprietary software may be used only as authorised by
// a licensing agreement from Lattice Semiconductor Corporation.
// The entire notice above must be reproduced on all authorized copies and
// copies may only be made to the extent permitted by a licensing agreement from
// Lattice Semiconductor Corporation.
//
// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
// 5555 NE Moore Court                            408-826-6000 (other locations)
// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
// U.S.A                                   email: techsupport@latticesemi.com
// =============================================================================/
//                         FILE DETAILS
// Project          : LatticeMico32
// File             : lm32_interrupt.v
// Title            : Interrupt logic
// Dependencies     : lm32_include.v
// Version          : 6.1.17
// =============================================================================
 
`include "system_conf.v"
`include "lm32_include.v"
 
/////////////////////////////////////////////////////
// Module interface
/////////////////////////////////////////////////////
 
module lm32_interrupt (
    // ----- Inputs -------
    clk_i,
    rst_i,
    // From external devices
    interrupt_n,
    // From pipeline
    stall_x,
`ifdef CFG_DEBUG_ENABLED
    non_debug_exception,
    debug_exception,
`else
    exception,
`endif
    eret_q_x,
`ifdef CFG_DEBUG_ENABLED
    bret_q_x,
`endif
    csr,
    csr_write_data,
    csr_write_enable,
    // ----- Outputs -------
    interrupt_exception,
    // To pipeline
    csr_read_data
    );
 
/////////////////////////////////////////////////////
// Parameters
/////////////////////////////////////////////////////
 
parameter interrupts = `CFG_INTERRUPTS;         // Number of interrupts
 
/////////////////////////////////////////////////////
// Inputs
/////////////////////////////////////////////////////
 
input clk_i;                                    // Clock
input rst_i;                                    // Reset
 
input [interrupts-1:0] interrupt_n;             // Interrupt pins, active-low
 
input stall_x;                                  // Stall X pipeline stage
 
`ifdef CFG_DEBUG_ENABLED
input non_debug_exception;                      // Non-debug related exception has been raised
input debug_exception;                          // Debug-related exception has been raised
`else
input exception;                                // Exception has been raised
`endif
input eret_q_x;                                 // Return from exception 
`ifdef CFG_DEBUG_ENABLED
input bret_q_x;                                 // Return from breakpoint 
`endif
 
input [`LM32_CSR_RNG] csr;                      // CSR read/write index
input [`LM32_WORD_RNG] csr_write_data;          // Data to write to specified CSR
input csr_write_enable;                         // CSR write enable
 
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
 
output interrupt_exception;                     // Request to raide an interrupt exception
wire   interrupt_exception;
 
output [`LM32_WORD_RNG] csr_read_data;          // Data read from CSR
reg    [`LM32_WORD_RNG] csr_read_data;
 
/////////////////////////////////////////////////////
// Internal nets and registers 
/////////////////////////////////////////////////////
 
wire [interrupts-1:0] asserted;                 // Which interrupts are currently being asserted
wire [interrupts-1:0] interrupt_n_exception;
 
// Interrupt CSRs
 
reg ie;                                         // Interrupt enable
reg eie;                                        // Exception interrupt enable
`ifdef CFG_DEBUG_ENABLED
reg bie;                                        // Breakpoint interrupt enable
`endif
reg [interrupts-1:0] ip;                        // Interrupt pending
reg [interrupts-1:0] im;                        // Interrupt mask
 
/////////////////////////////////////////////////////
// Combinational Logic
/////////////////////////////////////////////////////
 
// Determine which interrupts have occured and are unmasked
assign interrupt_n_exception = ip & im;
 
// Determine if any unmasked interrupts have occured
assign interrupt_exception = (|interrupt_n_exception) & ie;
 
// Determine which interrupts are currently being asserted (active-low) or are already pending
assign asserted = ip | ~interrupt_n;
 
//assign ie_csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}}, 
//`ifdef CFG_DEBUG_ENABLED
//                           bie,
//`else
//                           1'b0,
//`endif                             
//                           eie, 
//                           ie
//                          };
wire   ip_csr_read_data = ip;
wire   im_csr_read_data = im;
// XXX JB XXX
// generate
//    if (interrupts > 1) 
//    begin
// CSR read
always @*
begin
    case (csr)
    `LM32_CSR_IE:  csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}},
`ifdef CFG_DEBUG_ENABLED
                                    bie,
`else
                                    1'b0,
`endif
                                    eie,
                                    ie
                                   };
    `LM32_CSR_IP:  csr_read_data = ip;
    `LM32_CSR_IM:  csr_read_data = im;
    default:       csr_read_data = {`LM32_WORD_WIDTH{1'bx}};
    endcase
end
// XXX JB XXX
//    end
//    else
//    begin
//// CSR read
//always @*
//begin
//    case (csr)
//    `LM32_CSR_IE:  csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}}, 
//`ifdef CFG_DEBUG_ENABLED
//                                    bie, 
//`else
//                                    1'b0,                                    
//`endif
//                                    eie, 
//                                    ie
//                                   };
//    `LM32_CSR_IP:  csr_read_data = ip;
//    default:       csr_read_data = {`LM32_WORD_WIDTH{1'bx}};
//    endcase
//end
//    end
//endgenerate
 
/////////////////////////////////////////////////////
// Sequential Logic
/////////////////////////////////////////////////////
 
// XXX JB XXX
//generate
//    if (interrupts > 1)
//    begin
// IE, IM, IP - Interrupt Enable, Interrupt Mask and Interrupt Pending CSRs
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
    if (rst_i == `TRUE)
    begin
        ie <= `FALSE;
        eie <= `FALSE;
`ifdef CFG_DEBUG_ENABLED
        bie <= `FALSE;
`endif
        im <= {interrupts{1'b0}};
        ip <= {interrupts{1'b0}};
    end
    else
    begin
        // Set IP bit when interrupt line is asserted
        ip <= asserted;
`ifdef CFG_DEBUG_ENABLED
        if (non_debug_exception == `TRUE)
        begin
            // Save and then clear interrupt enable
            eie <= ie;
            ie <= `FALSE;
        end
        else if (debug_exception == `TRUE)
        begin
            // Save and then clear interrupt enable
            bie <= ie;
            ie <= `FALSE;
        end
`else
        if (exception == `TRUE)
        begin
            // Save and then clear interrupt enable
            eie <= ie;
            ie <= `FALSE;
        end
`endif
        else if (stall_x == `FALSE)
        begin
            if (eret_q_x == `TRUE)
                // Restore interrupt enable
                ie <= eie;
`ifdef CFG_DEBUG_ENABLED
            else if (bret_q_x == `TRUE)
                // Restore interrupt enable
                ie <= bie;
`endif
            else if (csr_write_enable == `TRUE)
            begin
                // Handle wcsr write
                if (csr == `LM32_CSR_IE)
                begin
                    ie <= csr_write_data[0];
                    eie <= csr_write_data[1];
`ifdef CFG_DEBUG_ENABLED
                    bie <= csr_write_data[2];
`endif
                end
                if (csr == `LM32_CSR_IM)
                    im <= csr_write_data[interrupts-1:0];
                if (csr == `LM32_CSR_IP)
                    ip <= asserted & ~csr_write_data[interrupts-1:0];
            end
        end
    end
end
//    end
//else
//    begin
//// IE, IM, IP - Interrupt Enable, Interrupt Mask and Interrupt Pending CSRs
//always @(posedge clk_i `CFG_RESET_SENSITIVITY)
//begin
//    if (rst_i == `TRUE)
//    begin
//        ie <= `FALSE;
//        eie <= `FALSE;
//`ifdef CFG_DEBUG_ENABLED
//        bie <= `FALSE;
//`endif
//        ip <= {interrupts{1'b0}};
//    end
//    else
//    begin
//        // Set IP bit when interrupt line is asserted
//        ip <= asserted;
//`ifdef CFG_DEBUG_ENABLED
//        if (non_debug_exception == `TRUE)
//        begin
//            // Save and then clear interrupt enable
//            eie <= ie;
//            ie <= `FALSE;
//        end
//        else if (debug_exception == `TRUE)
//        begin
//            // Save and then clear interrupt enable
//            bie <= ie;
//            ie <= `FALSE;
//        end
//`else
//        if (exception == `TRUE)
//        begin
//            // Save and then clear interrupt enable
//            eie <= ie;
//            ie <= `FALSE;
//        end
//`endif
//        else if (stall_x == `FALSE)
//        begin
//            if (eret_q_x == `TRUE)
//                // Restore interrupt enable
//                ie <= eie;          
//`ifdef CFG_DEBUG_ENABLED
//            else if (bret_q_x == `TRUE)
//                // Restore interrupt enable
//                ie <= bie;
//`endif
//            else if (csr_write_enable == `TRUE)
//            begin
//                // Handle wcsr write
//                if (csr == `LM32_CSR_IE)
//                begin
//                    ie <= csr_write_data[0];
//                    eie <= csr_write_data[1];
//`ifdef CFG_DEBUG_ENABLED
//                    bie <= csr_write_data[2];
//`endif
//                end
//                if (csr == `LM32_CSR_IP)
//                    ip <= asserted & ~csr_write_data[interrupts-1:0];
//            end
//        end
//    end
//end
//    end
//endgenerate
 
endmodule
 

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Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [lm32/] [verilog/] [src/] [lm32_interrupt.v] - Blame information for rev 17

Line No.	Rev	Author	Line
1	17	alirezamon	`// =============================================================================`
2			`// COPYRIGHT NOTICE`
3			`// Copyright 2006 (c) Lattice Semiconductor Corporation`
4			`// ALL RIGHTS RESERVED`
5			`// This confidential and proprietary software may be used only as authorised by`
6			`// a licensing agreement from Lattice Semiconductor Corporation.`
7			`// The entire notice above must be reproduced on all authorized copies and`
8			`// copies may only be made to the extent permitted by a licensing agreement from`
9			`// Lattice Semiconductor Corporation.`
10			`//`
11			`// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)`
12			`// 5555 NE Moore Court 408-826-6000 (other locations)`
13			`// Hillsboro, OR 97124 web : http://www.latticesemi.com/`
14			`// U.S.A email: techsupport@latticesemi.com`
15			`// =============================================================================/`
16			`// FILE DETAILS`
17			`// Project : LatticeMico32`
18			`// File : lm32_interrupt.v`
19			`// Title : Interrupt logic`
20			`// Dependencies : lm32_include.v`
21			`// Version : 6.1.17`
22			`// =============================================================================`
23
24			`include "system_conf.v"
25			`include "lm32_include.v"
26
27			`/////////////////////////////////////////////////////`
28			`// Module interface`
29			`/////////////////////////////////////////////////////`
30
31			`module lm32_interrupt (`
32			`// ----- Inputs -------`
33			`clk_i,`
34			`rst_i,`
35			`// From external devices`
36			`interrupt_n,`
37			`// From pipeline`
38			`stall_x,`
39			`ifdef CFG_DEBUG_ENABLED
40			`non_debug_exception,`
41			`debug_exception,`
42			`else
43			`exception,`
44			`endif
45			`eret_q_x,`
46			`ifdef CFG_DEBUG_ENABLED
47			`bret_q_x,`
48			`endif
49			`csr,`
50			`csr_write_data,`
51			`csr_write_enable,`
52			`// ----- Outputs -------`
53			`interrupt_exception,`
54			`// To pipeline`
55			`csr_read_data`
56			`);`
57
58			`/////////////////////////////////////////////////////`
59			`// Parameters`
60			`/////////////////////////////////////////////////////`
61
62			parameter interrupts = `CFG_INTERRUPTS; // Number of interrupts
63
64			`/////////////////////////////////////////////////////`
65			`// Inputs`
66			`/////////////////////////////////////////////////////`
67
68			`input clk_i; // Clock`
69			`input rst_i; // Reset`
70
71			`input [interrupts-1:0] interrupt_n; // Interrupt pins, active-low`
72
73			`input stall_x; // Stall X pipeline stage`
74
75			`ifdef CFG_DEBUG_ENABLED
76			`input non_debug_exception; // Non-debug related exception has been raised`
77			`input debug_exception; // Debug-related exception has been raised`
78			`else
79			`input exception; // Exception has been raised`
80			`endif
81			`input eret_q_x; // Return from exception`
82			`ifdef CFG_DEBUG_ENABLED
83			`input bret_q_x; // Return from breakpoint`
84			`endif
85
86			input [`LM32_CSR_RNG] csr; // CSR read/write index
87			input [`LM32_WORD_RNG] csr_write_data; // Data to write to specified CSR
88			`input csr_write_enable; // CSR write enable`
89
90			`/////////////////////////////////////////////////////`
91			`// Outputs`
92			`/////////////////////////////////////////////////////`
93
94			`output interrupt_exception; // Request to raide an interrupt exception`
95			`wire interrupt_exception;`
96
97			output [`LM32_WORD_RNG] csr_read_data; // Data read from CSR
98			reg [`LM32_WORD_RNG] csr_read_data;
99
100			`/////////////////////////////////////////////////////`
101			`// Internal nets and registers`
102			`/////////////////////////////////////////////////////`
103
104			`wire [interrupts-1:0] asserted; // Which interrupts are currently being asserted`
105			`wire [interrupts-1:0] interrupt_n_exception;`
106
107			`// Interrupt CSRs`
108
109			`reg ie; // Interrupt enable`
110			`reg eie; // Exception interrupt enable`
111			`ifdef CFG_DEBUG_ENABLED
112			`reg bie; // Breakpoint interrupt enable`
113			`endif
114			`reg [interrupts-1:0] ip; // Interrupt pending`
115			`reg [interrupts-1:0] im; // Interrupt mask`
116
117			`/////////////////////////////////////////////////////`
118			`// Combinational Logic`
119			`/////////////////////////////////////////////////////`
120
121			`// Determine which interrupts have occured and are unmasked`
122			`assign interrupt_n_exception = ip & im;`
123
124			`// Determine if any unmasked interrupts have occured`
125			`assign interrupt_exception = (\|interrupt_n_exception) & ie;`
126
127			`// Determine which interrupts are currently being asserted (active-low) or are already pending`
128			`assign asserted = ip \| ~interrupt_n;`
129
130			//assign ie_csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}},
131			//`ifdef CFG_DEBUG_ENABLED
132			`// bie,`
133			//`else
134			`// 1'b0,`
135			//`endif
136			`// eie,`
137			`// ie`
138			`// };`
139			`wire ip_csr_read_data = ip;`
140			`wire im_csr_read_data = im;`
141			`// XXX JB XXX`
142			`// generate`
143			`// if (interrupts > 1)`
144			`// begin`
145			`// CSR read`
146			`always @*`
147			`begin`
148			`case (csr)`
149			`LM32_CSR_IE: csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}},
150			`ifdef CFG_DEBUG_ENABLED
151			`bie,`
152			`else
153			`1'b0,`
154			`endif
155			`eie,`
156			`ie`
157			`};`
158			`LM32_CSR_IP: csr_read_data = ip;
159			`LM32_CSR_IM: csr_read_data = im;
160			default: csr_read_data = {`LM32_WORD_WIDTH{1'bx}};
161			`endcase`
162			`end`
163			`// XXX JB XXX`
164			`// end`
165			`// else`
166			`// begin`
167			`//// CSR read`
168			`//always @*`
169			`//begin`
170			`// case (csr)`
171			// `LM32_CSR_IE: csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}},
172			//`ifdef CFG_DEBUG_ENABLED
173			`// bie,`
174			//`else
175			`// 1'b0,`
176			//`endif
177			`// eie,`
178			`// ie`
179			`// };`
180			// `LM32_CSR_IP: csr_read_data = ip;
181			// default: csr_read_data = {`LM32_WORD_WIDTH{1'bx}};
182			`// endcase`
183			`//end`
184			`// end`
185			`//endgenerate`
186
187			`/////////////////////////////////////////////////////`
188			`// Sequential Logic`
189			`/////////////////////////////////////////////////////`
190
191			`// XXX JB XXX`
192			`//generate`
193			`// if (interrupts > 1)`
194			`// begin`
195			`// IE, IM, IP - Interrupt Enable, Interrupt Mask and Interrupt Pending CSRs`
196			always @(posedge clk_i `CFG_RESET_SENSITIVITY)
197			`begin`
198			if (rst_i == `TRUE)
199			`begin`
200			ie <= `FALSE;
201			eie <= `FALSE;
202			`ifdef CFG_DEBUG_ENABLED
203			bie <= `FALSE;
204			`endif
205			`im <= {interrupts{1'b0}};`
206			`ip <= {interrupts{1'b0}};`
207			`end`
208			`else`
209			`begin`
210			`// Set IP bit when interrupt line is asserted`
211			`ip <= asserted;`
212			`ifdef CFG_DEBUG_ENABLED
213			if (non_debug_exception == `TRUE)
214			`begin`
215			`// Save and then clear interrupt enable`
216			`eie <= ie;`
217			ie <= `FALSE;
218			`end`
219			else if (debug_exception == `TRUE)
220			`begin`
221			`// Save and then clear interrupt enable`
222			`bie <= ie;`
223			ie <= `FALSE;
224			`end`
225			`else
226			if (exception == `TRUE)
227			`begin`
228			`// Save and then clear interrupt enable`
229			`eie <= ie;`
230			ie <= `FALSE;
231			`end`
232			`endif
233			else if (stall_x == `FALSE)
234			`begin`
235			if (eret_q_x == `TRUE)
236			`// Restore interrupt enable`
237			`ie <= eie;`
238			`ifdef CFG_DEBUG_ENABLED
239			else if (bret_q_x == `TRUE)
240			`// Restore interrupt enable`
241			`ie <= bie;`
242			`endif
243			else if (csr_write_enable == `TRUE)
244			`begin`
245			`// Handle wcsr write`
246			if (csr == `LM32_CSR_IE)
247			`begin`
248			`ie <= csr_write_data[0];`
249			`eie <= csr_write_data[1];`
250			`ifdef CFG_DEBUG_ENABLED
251			`bie <= csr_write_data[2];`
252			`endif
253			`end`
254			if (csr == `LM32_CSR_IM)
255			`im <= csr_write_data[interrupts-1:0];`
256			if (csr == `LM32_CSR_IP)
257			`ip <= asserted & ~csr_write_data[interrupts-1:0];`
258			`end`
259			`end`
260			`end`
261			`end`
262			`// end`
263			`//else`
264			`// begin`
265			`//// IE, IM, IP - Interrupt Enable, Interrupt Mask and Interrupt Pending CSRs`
266			//always @(posedge clk_i `CFG_RESET_SENSITIVITY)
267			`//begin`
268			// if (rst_i == `TRUE)
269			`// begin`
270			// ie <= `FALSE;
271			// eie <= `FALSE;
272			//`ifdef CFG_DEBUG_ENABLED
273			// bie <= `FALSE;
274			//`endif
275			`// ip <= {interrupts{1'b0}};`
276			`// end`
277			`// else`
278			`// begin`
279			`// // Set IP bit when interrupt line is asserted`
280			`// ip <= asserted;`
281			//`ifdef CFG_DEBUG_ENABLED
282			// if (non_debug_exception == `TRUE)
283			`// begin`
284			`// // Save and then clear interrupt enable`
285			`// eie <= ie;`
286			// ie <= `FALSE;
287			`// end`
288			// else if (debug_exception == `TRUE)
289			`// begin`
290			`// // Save and then clear interrupt enable`
291			`// bie <= ie;`
292			// ie <= `FALSE;
293			`// end`
294			//`else
295			// if (exception == `TRUE)
296			`// begin`
297			`// // Save and then clear interrupt enable`
298			`// eie <= ie;`
299			// ie <= `FALSE;
300			`// end`
301			//`endif
302			// else if (stall_x == `FALSE)
303			`// begin`
304			// if (eret_q_x == `TRUE)
305			`// // Restore interrupt enable`
306			`// ie <= eie;`
307			//`ifdef CFG_DEBUG_ENABLED
308			// else if (bret_q_x == `TRUE)
309			`// // Restore interrupt enable`
310			`// ie <= bie;`
311			//`endif
312			// else if (csr_write_enable == `TRUE)
313			`// begin`
314			`// // Handle wcsr write`
315			// if (csr == `LM32_CSR_IE)
316			`// begin`
317			`// ie <= csr_write_data[0];`
318			`// eie <= csr_write_data[1];`
319			//`ifdef CFG_DEBUG_ENABLED
320			`// bie <= csr_write_data[2];`
321			//`endif
322			`// end`
323			// if (csr == `LM32_CSR_IP)
324			`// ip <= asserted & ~csr_write_data[interrupts-1:0];`
325			`// end`
326			`// end`
327			`// end`
328			`//end`
329			`// end`
330			`//endgenerate`
331
332			`endmodule`
333