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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [mor1kx-3.1/] [rtl/] [verilog/] [mor1kx_bus_if_wb32.v] - Blame information for rev 38

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1 38 alirezamon 
/* ****************************************************************************
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  This Source Code Form is subject to the terms of the
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  Open Hardware Description License, v. 1.0. If a copy
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  of the OHDL was not distributed with this file, You
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  can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
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  Description: mor1kx processor Wishbone bus bridge
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  For now, very simple, not registering,  assumes 32-bit data, addressing
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  Copyright (C) 2012 Authors
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  Author(s): Julius Baxter <juliusbaxter@gmail.com>
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***************************************************************************** */
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`include "mor1kx-defines.v"
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module mor1kx_bus_if_wb32
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  #(
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    parameter BUS_IF_TYPE = "CLASSIC",
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    parameter BURST_LENGTH = 8
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    )
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   (
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    input         clk,
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    input         rst,
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    output        cpu_err_o,
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    output        cpu_ack_o,
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    output [31:0] cpu_dat_o,
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    input [31:0]  cpu_adr_i,
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    input [31:0]  cpu_dat_i,
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    input         cpu_req_i,
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    input [3:0]   cpu_bsel_i,
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    input         cpu_we_i,
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    input         cpu_burst_i,
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    output [31:0] wbm_adr_o,
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    output        wbm_stb_o,
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    output        wbm_cyc_o,
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    output [3:0]  wbm_sel_o,
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    output        wbm_we_o,
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    output [2:0]  wbm_cti_o,
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    output [1:0]  wbm_bte_o,
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    output [31:0] wbm_dat_o,
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    input         wbm_err_i,
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    input         wbm_ack_i,
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    input [31:0]  wbm_dat_i,
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    input         wbm_rty_i
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    );
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   localparam  BADDR_WITH = (BURST_LENGTH==4) ? 2 :
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                            (BURST_LENGTH==8) ? 3 :
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                            (BURST_LENGTH==16)? 4 : 30;
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   initial
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     $display("%m: Wishbone bus IF is %s",BUS_IF_TYPE);
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   generate
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      /* verilator lint_off WIDTH */
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      if (BUS_IF_TYPE=="B3_READ_BURSTING") begin : b3_read_bursting
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         /* verilator lint_on WIDTH */
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         // Burst until the incoming address is not what it should be
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         wire                         finish_burst;
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         reg                          finish_burst_r;
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         reg                          bursting;
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         reg [31:2]                   burst_address;
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         reg [BADDR_WITH-1:0]          burst_wrap_start;
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         wire [BADDR_WITH-1:0]         burst_wrap_finish;
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         wire                         address_differs;
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         always @(posedge clk `OR_ASYNC_RST)
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           if (rst)
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             bursting <= 0;
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           else if (wbm_err_i)
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             bursting <= 0;
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           else if (bursting & finish_burst & wbm_ack_i)
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             bursting <= 0;
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           else if (cpu_req_i & !bursting & !cpu_we_i)
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             bursting <= 1;
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         always @(posedge clk `OR_ASYNC_RST)
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           if (rst)
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             begin
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                burst_address <= 0;
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                burst_wrap_start <= 0;
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             end
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           else if (cpu_req_i & !bursting)
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             begin
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                burst_address <= cpu_adr_i[31:2];
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                burst_wrap_start <= cpu_adr_i[BADDR_WITH+2-1:2];
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             end
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           else if (wbm_ack_i)
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             burst_address[BADDR_WITH+2-1:2] <= burst_address[BADDR_WITH+2-1:2]
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                  + 1;
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         assign address_differs = (burst_address!=cpu_adr_i[31:2]);
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         assign burst_wrap_finish = burst_wrap_start - 1;
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         assign finish_burst = (bursting & (
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                      (BURST_LENGTH!=0 &&
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                       burst_address[BADDR_WITH+2-1:2]==(burst_wrap_finish))
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                                            | address_differs
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                                            | !cpu_req_i
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                                            )
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                                )
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           ;
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         always @(posedge clk `OR_ASYNC_RST)
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           if (rst)
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             finish_burst_r <= 0;
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           else if (wbm_ack_i)
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             finish_burst_r <= finish_burst;
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           else
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             finish_burst_r <= 0;
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         assign wbm_adr_o = bursting ? {burst_address,2'b00} : cpu_adr_i;
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         assign wbm_stb_o = bursting & !finish_burst_r;
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         assign wbm_cyc_o = bursting & !finish_burst_r;
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         assign wbm_sel_o = cpu_bsel_i;
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         assign wbm_we_o = cpu_we_i;
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         assign wbm_cti_o = bursting ? (finish_burst ? 3'b111 : 3'b010) :
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                            3'b000;
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         assign wbm_bte_o = BURST_LENGTH==4  ? 2'b01 :
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                            BURST_LENGTH==8  ? 2'b10 :
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                            BURST_LENGTH==16 ? 2'b11 :
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                            2'b00; // Linear burst
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         assign wbm_dat_o = cpu_dat_i;
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         assign cpu_err_o = wbm_err_i;
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         assign cpu_ack_o = (wbm_ack_i) &
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                            !(bursting & address_differs) & cpu_req_i;
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         assign cpu_dat_o = wbm_err_i ? 0 :  wbm_dat_i;
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      /* verilator lint_off WIDTH */
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      end else if (BUS_IF_TYPE=="B3_REGISTERED_FEEDBACK") begin : b3_registered_feedback
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         /* verilator lint_on WIDTH */
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         assign wbm_adr_o = cpu_adr_i;
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         assign wbm_stb_o = cpu_req_i;
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         assign wbm_cyc_o = cpu_req_i;
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         assign wbm_sel_o = cpu_bsel_i;
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         assign wbm_we_o = cpu_we_i;
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         assign wbm_cti_o = cpu_burst_i ? 3'b010 : 3'b111;
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         assign wbm_bte_o = BURST_LENGTH==4  ? 2'b01 :
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                            BURST_LENGTH==8  ? 2'b10 :
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                            BURST_LENGTH==16 ? 2'b11 :
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                            2'b00; // Linear burst
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         assign wbm_dat_o = cpu_dat_i;
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         assign cpu_err_o = wbm_err_i;
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         assign cpu_ack_o = wbm_ack_i;
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         assign cpu_dat_o = wbm_dat_i;
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      end else begin : classic // CLASSIC only
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         // Only classic, single cycle accesses
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         // A register to force de-assertion of access request signals after
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         // each ack
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         reg                                  cycle_end;
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         always @(posedge clk `OR_ASYNC_RST)
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           if (rst)
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             cycle_end <= 1;
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           else
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             cycle_end <= wbm_ack_i | wbm_err_i;
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         assign cpu_err_o = wbm_err_i;
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         assign cpu_ack_o = wbm_ack_i;
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         assign cpu_dat_o = wbm_dat_i;
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         assign wbm_adr_o = cpu_adr_i;
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         assign wbm_stb_o = cpu_req_i & !cycle_end;
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         assign wbm_cyc_o = cpu_req_i;
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         assign wbm_sel_o = cpu_bsel_i;
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         assign wbm_we_o = cpu_we_i;
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         assign wbm_cti_o = 0;
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         assign wbm_bte_o = 0;
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         assign wbm_dat_o = cpu_dat_i;
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      end // else: !if(BUS_IF_TYPE=="READ_B3_BURSTING")
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   endgenerate
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endmodule // mor1kx_bus_if_wb

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