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alirezamon |
/* ****************************************************************************
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This Source Code Form is subject to the terms of the
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Open Hardware Description License, v. 1.0. If a copy
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of the OHDL was not distributed with this file, You
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can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
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Description: "Pronto espresso" pipeline CPU module
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Copyright (C) 2012 Authors
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Author(s): Julius Baxter <juliusbaxter@gmail.com>
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***************************************************************************** */
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`include "mor1kx-defines.v"
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module mor1kx_cpu_prontoespresso
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#(
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parameter OPTION_OPERAND_WIDTH = 32,
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parameter FEATURE_DATACACHE = "NONE",
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parameter OPTION_DCACHE_BLOCK_WIDTH = 5,
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parameter OPTION_DCACHE_SET_WIDTH = 9,
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parameter OPTION_DCACHE_WAYS = 2,
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parameter FEATURE_DMMU = "NONE",
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parameter FEATURE_DMMU_HW_TLB_RELOAD = "NONE",
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parameter FEATURE_INSTRUCTIONCACHE = "NONE",
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parameter OPTION_ICACHE_BLOCK_WIDTH = 5,
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parameter OPTION_ICACHE_SET_WIDTH = 9,
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parameter OPTION_ICACHE_WAYS = 2,
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parameter FEATURE_IMMU = "NONE",
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parameter FEATURE_IMMU_HW_TLB_RELOAD = "NONE",
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parameter FEATURE_TIMER = "ENABLED",
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parameter FEATURE_DEBUGUNIT = "NONE",
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parameter FEATURE_PERFCOUNTERS = "NONE",
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parameter FEATURE_MAC = "NONE",
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parameter FEATURE_SYSCALL = "ENABLED",
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parameter FEATURE_TRAP = "ENABLED",
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parameter FEATURE_RANGE = "ENABLED",
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parameter FEATURE_PIC = "ENABLED",
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parameter OPTION_PIC_TRIGGER = "LEVEL",
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parameter OPTION_PIC_NMI_WIDTH = 0,
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parameter FEATURE_DSX = "NONE",
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parameter FEATURE_FASTCONTEXTS = "NONE",
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parameter FEATURE_OVERFLOW = "NONE",
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parameter FEATURE_CARRY_FLAG = "ENABLED",
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parameter OPTION_RF_ADDR_WIDTH = 5,
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parameter OPTION_RF_WORDS = 32,
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parameter OPTION_RESET_PC = {{(OPTION_OPERAND_WIDTH-13){1'b0}},
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`OR1K_RESET_VECTOR,8'd0},
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parameter OPTION_TCM_FETCHER = "DISABLED",
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parameter FEATURE_MULTIPLIER = "THREESTAGE",
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parameter FEATURE_DIVIDER = "NONE",
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parameter FEATURE_ADDC = "NONE",
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parameter FEATURE_SRA = "ENABLED",
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parameter FEATURE_ROR = "NONE",
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parameter FEATURE_EXT = "NONE",
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parameter FEATURE_CMOV = "NONE",
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parameter FEATURE_FFL1 = "NONE",
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parameter FEATURE_MSYNC = "NONE",
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parameter FEATURE_PSYNC = "NONE",
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parameter FEATURE_CSYNC = "NONE",
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parameter FEATURE_CUST1 = "NONE",
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parameter FEATURE_CUST2 = "NONE",
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parameter FEATURE_CUST3 = "NONE",
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parameter FEATURE_CUST4 = "NONE",
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parameter FEATURE_CUST5 = "NONE",
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parameter FEATURE_CUST6 = "NONE",
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parameter FEATURE_CUST7 = "NONE",
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parameter FEATURE_CUST8 = "NONE",
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parameter OPTION_SHIFTER = "BARREL",
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parameter FEATURE_MULTICORE = "NONE",
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parameter FEATURE_TRACEPORT_EXEC = "NONE"
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)
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(
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input clk,
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input rst,
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// Instruction bus
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input ibus_err_i,
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input ibus_ack_i,
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input [`OR1K_INSN_WIDTH-1:0] ibus_dat_i,
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output [OPTION_OPERAND_WIDTH-1:0] ibus_adr_o,
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output ibus_req_o,
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output ibus_burst_o,
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// Data bus
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input dbus_err_i,
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input dbus_ack_i,
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input [OPTION_OPERAND_WIDTH-1:0] dbus_dat_i,
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output [OPTION_OPERAND_WIDTH-1:0] dbus_adr_o,
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output [OPTION_OPERAND_WIDTH-1:0] dbus_dat_o,
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output dbus_req_o,
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output [3:0] dbus_bsel_o,
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output dbus_we_o,
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output dbus_burst_o,
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// Interrupts
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input [31:0] irq_i,
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// Debug interface
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input [15:0] du_addr_i,
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input du_stb_i,
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input [OPTION_OPERAND_WIDTH-1:0] du_dat_i,
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input du_we_i,
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output [OPTION_OPERAND_WIDTH-1:0] du_dat_o,
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output du_ack_o,
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// Stall control from debug interface
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input du_stall_i,
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output du_stall_o,
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// SPR accesses to external units (cache, mmu, etc.)
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output [15:0] spr_bus_addr_o,
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output spr_bus_we_o,
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output spr_bus_stb_o,
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output [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_o,
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input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_dmmu_i,
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input spr_bus_ack_dmmu_i,
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input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_immu_i,
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input spr_bus_ack_immu_i,
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input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_mac_i,
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input spr_bus_ack_mac_i,
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input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_pmu_i,
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input spr_bus_ack_pmu_i,
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input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_pcu_i,
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input spr_bus_ack_pcu_i,
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input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_fpu_i,
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input spr_bus_ack_fpu_i,
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output [15:0] spr_sr_o,
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// The multicore core identifier
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input [OPTION_OPERAND_WIDTH-1:0] multicore_coreid_i
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);
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wire [OPTION_OPERAND_WIDTH-1:0] pc_fetch_to_decode;
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wire [`OR1K_INSN_WIDTH-1:0] insn_fetch_to_decode;
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wire [OPTION_OPERAND_WIDTH-1:0] pc_decode_to_execute;
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wire [OPTION_OPERAND_WIDTH-1:0] pc_execute_to_ctrl;
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [OPTION_OPERAND_WIDTH-1:0] adder_result_o;// From mor1kx_execute_alu of mor1kx_execute_alu.v
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wire [OPTION_OPERAND_WIDTH-1:0] alu_result_o;// From mor1kx_execute_alu of mor1kx_execute_alu.v
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wire alu_valid_o; // From mor1kx_execute_alu of mor1kx_execute_alu.v
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wire carry_clear_o; // From mor1kx_execute_alu of mor1kx_execute_alu.v
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wire carry_o; // From mor1kx_ctrl_prontoespresso of mor1kx_ctrl_prontoespresso.v
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wire carry_set_o; // From mor1kx_execute_alu of mor1kx_execute_alu.v
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wire ctrl_branch_occur_o; // From mor1kx_ctrl_prontoespresso of mor1kx_ctrl_prontoespresso.v
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wire [OPTION_OPERAND_WIDTH-1:0] ctrl_branch_target_o;// From mor1kx_ctrl_prontoespresso of mor1kx_ctrl_prontoespresso.v
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wire ctrl_insn_done_o; // From mor1kx_ctrl_prontoespresso of mor1kx_ctrl_prontoespresso.v
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wire ctrl_mfspr_we_o; // From mor1kx_ctrl_prontoespresso of mor1kx_ctrl_prontoespresso.v
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wire decode_adder_do_carry_o;// From mor1kx_decode of mor1kx_decode.v
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wire decode_adder_do_sub_o; // From mor1kx_decode of mor1kx_decode.v
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wire decode_except_ibus_err_o;// From mor1kx_fetch_prontoespresso of mor1kx_fetch_tcm_prontoespresso.v, ...
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wire decode_except_illegal_o;// From mor1kx_decode of mor1kx_decode.v
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wire decode_except_syscall_o;// From mor1kx_decode of mor1kx_decode.v
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wire decode_except_trap_o; // From mor1kx_decode of mor1kx_decode.v
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wire [`OR1K_IMM_WIDTH-1:0] decode_imm16_o; // From mor1kx_decode of mor1kx_decode.v
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wire [OPTION_OPERAND_WIDTH-1:0] decode_immediate_o;// From mor1kx_decode of mor1kx_decode.v
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wire decode_immediate_sel_o; // From mor1kx_decode of mor1kx_decode.v
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wire [9:0] decode_immjbr_upper_o; // From mor1kx_decode of mor1kx_decode.v
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wire [1:0] decode_lsu_length_o; // From mor1kx_decode of mor1kx_decode.v
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wire decode_lsu_zext_o; // From mor1kx_decode of mor1kx_decode.v
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wire decode_op_add_o; // From mor1kx_decode of mor1kx_decode.v
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wire decode_op_alu_o; // From mor1kx_decode of mor1kx_decode.v
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wire decode_op_bf_o; // From mor1kx_decode of mor1kx_decode.v
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wire decode_op_bnf_o; // From mor1kx_decode of mor1kx_decode.v
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wire decode_op_branch_o; // From mor1kx_decode of mor1kx_decode.v
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wire decode_op_brcond_o; // From mor1kx_decode of mor1kx_decode.v
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wire decode_op_div_o; // From mor1kx_decode of mor1kx_decode.v
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wire decode_op_div_signed_o; // From mor1kx_decode of mor1kx_decode.v
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wire decode_op_div_unsigned_o;// From mor1kx_decode of mor1kx_decode.v
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wire decode_op_ffl1_o; // From mor1kx_decode of mor1kx_decode.v
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wire decode_op_jal_o; // From mor1kx_decode of mor1kx_decode.v
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wire decode_op_jbr_o; // From mor1kx_decode of mor1kx_decode.v
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wire decode_op_jr_o; // From mor1kx_decode of mor1kx_decode.v
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wire decode_op_lsu_atomic_o; // From mor1kx_decode of mor1kx_decode.v
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wire decode_op_lsu_load_o; // From mor1kx_decode of mor1kx_decode.v
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wire decode_op_lsu_store_o; // From mor1kx_decode of mor1kx_decode.v
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wire decode_op_mfspr_o; // From mor1kx_decode of mor1kx_decode.v
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wire decode_op_movhi_o; // From mor1kx_decode of mor1kx_decode.v
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wire decode_op_mtspr_o; // From mor1kx_decode of mor1kx_decode.v
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wire decode_op_mul_o; // From mor1kx_decode of mor1kx_decode.v
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wire decode_op_mul_signed_o; // From mor1kx_decode of mor1kx_decode.v
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wire decode_op_mul_unsigned_o;// From mor1kx_decode of mor1kx_decode.v
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wire decode_op_rfe_o; // From mor1kx_decode of mor1kx_decode.v
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wire decode_op_setflag_o; // From mor1kx_decode of mor1kx_decode.v
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wire decode_op_shift_o; // From mor1kx_decode of mor1kx_decode.v
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wire [`OR1K_ALU_OPC_WIDTH-1:0] decode_opc_alu_o;// From mor1kx_decode of mor1kx_decode.v
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wire [`OR1K_ALU_OPC_WIDTH-1:0] decode_opc_alu_secondary_o;// From mor1kx_decode of mor1kx_decode.v
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wire [`OR1K_OPCODE_WIDTH-1:0] decode_opc_insn_o;// From mor1kx_decode of mor1kx_decode.v
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wire decode_rf_wb_o; // From mor1kx_decode of mor1kx_decode.v
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wire [OPTION_RF_ADDR_WIDTH-1:0] decode_rfa_adr_o;// From mor1kx_decode of mor1kx_decode.v
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wire [OPTION_RF_ADDR_WIDTH-1:0] decode_rfb_adr_o;// From mor1kx_decode of mor1kx_decode.v
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wire [OPTION_RF_ADDR_WIDTH-1:0] decode_rfd_adr_o;// From mor1kx_decode of mor1kx_decode.v
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wire du_restart_o; // From mor1kx_ctrl_prontoespresso of mor1kx_ctrl_prontoespresso.v
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wire [OPTION_OPERAND_WIDTH-1:0] du_restart_pc_o;// From mor1kx_ctrl_prontoespresso of mor1kx_ctrl_prontoespresso.v
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wire exception_taken_o; // From mor1kx_ctrl_prontoespresso of mor1kx_ctrl_prontoespresso.v
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wire execute_waiting_o; // From mor1kx_ctrl_prontoespresso of mor1kx_ctrl_prontoespresso.v
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wire fetch_quick_branch_o; // From mor1kx_fetch_prontoespresso of mor1kx_fetch_prontoespresso.v
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wire fetch_ready_o; // From mor1kx_fetch_prontoespresso of mor1kx_fetch_tcm_prontoespresso.v, ...
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wire fetch_rf_re_o; // From mor1kx_fetch_prontoespresso of mor1kx_fetch_tcm_prontoespresso.v, ...
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wire [OPTION_RF_ADDR_WIDTH-1:0] fetch_rfa_adr_o;// From mor1kx_fetch_prontoespresso of mor1kx_fetch_tcm_prontoespresso.v, ...
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wire [OPTION_RF_ADDR_WIDTH-1:0] fetch_rfb_adr_o;// From mor1kx_fetch_prontoespresso of mor1kx_fetch_tcm_prontoespresso.v, ...
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wire fetch_sleep_o; // From mor1kx_fetch_prontoespresso of mor1kx_fetch_tcm_prontoespresso.v, ...
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wire fetch_take_exception_branch_o;// From mor1kx_ctrl_prontoespresso of mor1kx_ctrl_prontoespresso.v
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wire [OPTION_OPERAND_WIDTH-1:0] fetched_pc_o;// From mor1kx_fetch_prontoespresso of mor1kx_fetch_tcm_prontoespresso.v, ...
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wire flag_clear_o; // From mor1kx_execute_alu of mor1kx_execute_alu.v
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wire flag_o; // From mor1kx_ctrl_prontoespresso of mor1kx_ctrl_prontoespresso.v
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wire flag_set_o; // From mor1kx_execute_alu of mor1kx_execute_alu.v
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wire [OPTION_OPERAND_WIDTH-1:0] link_addr_o; // From mor1kx_ctrl_prontoespresso of mor1kx_ctrl_prontoespresso.v
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wire lsu_except_align_o; // From mor1kx_lsu_espresso of mor1kx_lsu_espresso.v
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wire lsu_except_dbus_o; // From mor1kx_lsu_espresso of mor1kx_lsu_espresso.v
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wire [OPTION_OPERAND_WIDTH-1:0] lsu_result_o;// From mor1kx_lsu_espresso of mor1kx_lsu_espresso.v
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wire lsu_valid_o; // From mor1kx_lsu_espresso of mor1kx_lsu_espresso.v
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wire [OPTION_OPERAND_WIDTH-1:0] mfspr_dat_o; // From mor1kx_ctrl_prontoespresso of mor1kx_ctrl_prontoespresso.v
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wire [OPTION_OPERAND_WIDTH-1:0] mul_result_o;// From mor1kx_execute_alu of mor1kx_execute_alu.v
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wire overflow_clear_o; // From mor1kx_execute_alu of mor1kx_execute_alu.v
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wire overflow_set_o; // From mor1kx_execute_alu of mor1kx_execute_alu.v
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wire padv_decode_o; // From mor1kx_ctrl_prontoespresso of mor1kx_ctrl_prontoespresso.v
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wire padv_execute_o; // From mor1kx_ctrl_prontoespresso of mor1kx_ctrl_prontoespresso.v
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wire padv_fetch_o; // From mor1kx_ctrl_prontoespresso of mor1kx_ctrl_prontoespresso.v
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wire [OPTION_OPERAND_WIDTH-1:0] pc_fetch_next_o;// From mor1kx_fetch_prontoespresso of mor1kx_fetch_tcm_prontoespresso.v, ...
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wire pipeline_flush_o; // From mor1kx_ctrl_prontoespresso of mor1kx_ctrl_prontoespresso.v
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wire [OPTION_OPERAND_WIDTH-1:0] rf_result_o; // From mor1kx_wb_mux_espresso of mor1kx_wb_mux_espresso.v
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wire rf_we_o; // From mor1kx_ctrl_prontoespresso of mor1kx_ctrl_prontoespresso.v
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wire [OPTION_OPERAND_WIDTH-1:0] rfa_o; // From mor1kx_rf_espresso of mor1kx_rf_espresso.v
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wire [OPTION_OPERAND_WIDTH-1:0] rfb_o; // From mor1kx_rf_espresso of mor1kx_rf_espresso.v
|
241 |
|
|
wire spr_bus_ack_ic_i; // From mor1kx_fetch_prontoespresso of mor1kx_fetch_prontoespresso.v
|
242 |
|
|
wire [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_ic_i;// From mor1kx_fetch_prontoespresso of mor1kx_fetch_prontoespresso.v
|
243 |
|
|
wire [OPTION_OPERAND_WIDTH-1:0] spr_npc_o; // From mor1kx_ctrl_prontoespresso of mor1kx_ctrl_prontoespresso.v
|
244 |
|
|
wire [OPTION_OPERAND_WIDTH-1:0] spr_ppc_o; // From mor1kx_ctrl_prontoespresso of mor1kx_ctrl_prontoespresso.v
|
245 |
|
|
wire stepping_o; // From mor1kx_ctrl_prontoespresso of mor1kx_ctrl_prontoespresso.v
|
246 |
|
|
// End of automatics
|
247 |
|
|
|
248 |
|
|
generate
|
249 |
|
|
if (OPTION_TCM_FETCHER=="ENABLED")
|
250 |
|
|
begin : fetch_tcm
|
251 |
|
|
|
252 |
|
|
/* mor1kx_fetch_tcm_prontoespresso AUTO_TEMPLATE (
|
253 |
|
|
.padv_i (padv_fetch_o),
|
254 |
|
|
.branch_occur_i (ctrl_branch_occur_o),
|
255 |
|
|
.branch_dest_i (ctrl_branch_target_o),
|
256 |
|
|
.pipeline_flush_i (pipeline_flush_o),
|
257 |
|
|
.pc_decode_o (pc_fetch_to_decode),
|
258 |
|
|
.decode_insn_o (insn_fetch_to_decode),
|
259 |
|
|
.du_restart_pc_i (du_restart_pc_o),
|
260 |
|
|
.du_restart_i (du_restart_o),
|
261 |
|
|
.fetch_take_exception_branch_i (fetch_take_exception_branch_o),
|
262 |
|
|
.execute_waiting_i (execute_waiting_o),
|
263 |
|
|
.stepping_i (stepping_o),
|
264 |
|
|
.flag_i (flag_o),
|
265 |
|
|
.flag_clear_i (flag_clear_o),
|
266 |
|
|
.flag_set_i (flag_set_o),
|
267 |
|
|
); */
|
268 |
|
|
mor1kx_fetch_tcm_prontoespresso
|
269 |
|
|
#(
|
270 |
|
|
.OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH),
|
271 |
|
|
.OPTION_RF_ADDR_WIDTH(OPTION_RF_ADDR_WIDTH),
|
272 |
|
|
.OPTION_RESET_PC(OPTION_RESET_PC)
|
273 |
|
|
)
|
274 |
|
|
mor1kx_fetch_prontoespresso
|
275 |
|
|
(/*AUTOINST*/
|
276 |
|
|
// Outputs
|
277 |
|
|
.ibus_adr_o (ibus_adr_o[OPTION_OPERAND_WIDTH-1:0]),
|
278 |
|
|
.ibus_req_o (ibus_req_o),
|
279 |
|
|
.decode_insn_o (insn_fetch_to_decode), // Templated
|
280 |
|
|
.fetched_pc_o (fetched_pc_o[OPTION_OPERAND_WIDTH-1:0]),
|
281 |
|
|
.fetch_ready_o (fetch_ready_o),
|
282 |
|
|
.fetch_rfa_adr_o (fetch_rfa_adr_o[OPTION_RF_ADDR_WIDTH-1:0]),
|
283 |
|
|
.fetch_rfb_adr_o (fetch_rfb_adr_o[OPTION_RF_ADDR_WIDTH-1:0]),
|
284 |
|
|
.fetch_rf_re_o (fetch_rf_re_o),
|
285 |
|
|
.pc_fetch_next_o (pc_fetch_next_o[OPTION_OPERAND_WIDTH-1:0]),
|
286 |
|
|
.decode_except_ibus_err_o (decode_except_ibus_err_o),
|
287 |
|
|
.fetch_sleep_o (fetch_sleep_o),
|
288 |
|
|
// Inputs
|
289 |
|
|
.clk (clk),
|
290 |
|
|
.rst (rst),
|
291 |
|
|
.ibus_err_i (ibus_err_i),
|
292 |
|
|
.ibus_ack_i (ibus_ack_i),
|
293 |
|
|
.ibus_dat_i (ibus_dat_i[`OR1K_INSN_WIDTH-1:0]),
|
294 |
|
|
.padv_i (padv_fetch_o), // Templated
|
295 |
|
|
.branch_occur_i (ctrl_branch_occur_o), // Templated
|
296 |
|
|
.branch_dest_i (ctrl_branch_target_o), // Templated
|
297 |
|
|
.du_restart_i (du_restart_o), // Templated
|
298 |
|
|
.du_restart_pc_i (du_restart_pc_o), // Templated
|
299 |
|
|
.fetch_take_exception_branch_i(fetch_take_exception_branch_o), // Templated
|
300 |
|
|
.execute_waiting_i (execute_waiting_o), // Templated
|
301 |
|
|
.du_stall_i (du_stall_i),
|
302 |
|
|
.stepping_i (stepping_o), // Templated
|
303 |
|
|
.flag_i (flag_o), // Templated
|
304 |
|
|
.flag_clear_i (flag_clear_o), // Templated
|
305 |
|
|
.flag_set_i (flag_set_o)); // Templated
|
306 |
|
|
|
307 |
|
|
end
|
308 |
|
|
else
|
309 |
|
|
begin : fetch
|
310 |
|
|
|
311 |
|
|
/* mor1kx_fetch_prontoespresso AUTO_TEMPLATE (
|
312 |
|
|
.padv_i (padv_fetch_o),
|
313 |
|
|
.branch_occur_i (ctrl_branch_occur_o),
|
314 |
|
|
.branch_dest_i (ctrl_branch_target_o),
|
315 |
|
|
.ctrl_insn_done_i (ctrl_insn_done_o),
|
316 |
|
|
.pipeline_flush_i (pipeline_flush_o),
|
317 |
|
|
.pc_decode_o (pc_fetch_to_decode),
|
318 |
|
|
.decode_insn_o (insn_fetch_to_decode),
|
319 |
|
|
.du_restart_pc_i (du_restart_pc_o),
|
320 |
|
|
.du_restart_i (du_restart_o),
|
321 |
|
|
.fetch_take_exception_branch_i (fetch_take_exception_branch_o),
|
322 |
|
|
.execute_waiting_i (execute_waiting_o),
|
323 |
|
|
.stepping_i (stepping_o),
|
324 |
|
|
.flag_i (flag_o),
|
325 |
|
|
.flag_clear_i (flag_clear_o),
|
326 |
|
|
.flag_set_i (flag_set_o),
|
327 |
|
|
.spr_bus_dat_ic_o (spr_bus_dat_ic_i[OPTION_OPERAND_WIDTH-1:0]),
|
328 |
|
|
.spr_bus_ack_ic_o (spr_bus_ack_ic_i),
|
329 |
|
|
.spr_bus_addr_i (spr_bus_addr_o[15:0]),
|
330 |
|
|
.spr_bus_we_i (spr_bus_we_o),
|
331 |
|
|
.spr_bus_stb_i (spr_bus_stb_o),
|
332 |
|
|
.spr_bus_dat_i (spr_bus_dat_o[OPTION_OPERAND_WIDTH-1:0]),
|
333 |
|
|
.ic_enable (spr_sr_o[`OR1K_SPR_SR_ICE]),
|
334 |
|
|
); */
|
335 |
|
|
mor1kx_fetch_prontoespresso
|
336 |
|
|
#(
|
337 |
|
|
.OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH),
|
338 |
|
|
.OPTION_RF_ADDR_WIDTH(OPTION_RF_ADDR_WIDTH),
|
339 |
|
|
.OPTION_RESET_PC(OPTION_RESET_PC),
|
340 |
|
|
.FEATURE_INSTRUCTIONCACHE(FEATURE_INSTRUCTIONCACHE),
|
341 |
|
|
.OPTION_ICACHE_BLOCK_WIDTH(OPTION_ICACHE_BLOCK_WIDTH)
|
342 |
|
|
)
|
343 |
|
|
mor1kx_fetch_prontoespresso
|
344 |
|
|
(/*AUTOINST*/
|
345 |
|
|
// Outputs
|
346 |
|
|
.ibus_adr_o (ibus_adr_o[OPTION_OPERAND_WIDTH-1:0]),
|
347 |
|
|
.ibus_req_o (ibus_req_o),
|
348 |
|
|
.ibus_burst_o (ibus_burst_o),
|
349 |
|
|
.decode_insn_o (insn_fetch_to_decode), // Templated
|
350 |
|
|
.fetched_pc_o (fetched_pc_o[OPTION_OPERAND_WIDTH-1:0]),
|
351 |
|
|
.fetch_ready_o (fetch_ready_o),
|
352 |
|
|
.fetch_rfa_adr_o (fetch_rfa_adr_o[OPTION_RF_ADDR_WIDTH-1:0]),
|
353 |
|
|
.fetch_rfb_adr_o (fetch_rfb_adr_o[OPTION_RF_ADDR_WIDTH-1:0]),
|
354 |
|
|
.fetch_rf_re_o (fetch_rf_re_o),
|
355 |
|
|
.pc_fetch_next_o (pc_fetch_next_o[OPTION_OPERAND_WIDTH-1:0]),
|
356 |
|
|
.decode_except_ibus_err_o (decode_except_ibus_err_o),
|
357 |
|
|
.fetch_sleep_o (fetch_sleep_o),
|
358 |
|
|
.fetch_quick_branch_o (fetch_quick_branch_o),
|
359 |
|
|
.spr_bus_dat_ic_o (spr_bus_dat_ic_i[OPTION_OPERAND_WIDTH-1:0]), // Templated
|
360 |
|
|
.spr_bus_ack_ic_o (spr_bus_ack_ic_i), // Templated
|
361 |
|
|
// Inputs
|
362 |
|
|
.clk (clk),
|
363 |
|
|
.rst (rst),
|
364 |
|
|
.ibus_err_i (ibus_err_i),
|
365 |
|
|
.ibus_ack_i (ibus_ack_i),
|
366 |
|
|
.ibus_dat_i (ibus_dat_i[`OR1K_INSN_WIDTH-1:0]),
|
367 |
|
|
.ic_enable (spr_sr_o[`OR1K_SPR_SR_ICE]), // Templated
|
368 |
|
|
.padv_i (padv_fetch_o), // Templated
|
369 |
|
|
.branch_occur_i (ctrl_branch_occur_o), // Templated
|
370 |
|
|
.branch_dest_i (ctrl_branch_target_o), // Templated
|
371 |
|
|
.ctrl_insn_done_i (ctrl_insn_done_o), // Templated
|
372 |
|
|
.du_restart_i (du_restart_o), // Templated
|
373 |
|
|
.du_restart_pc_i (du_restart_pc_o), // Templated
|
374 |
|
|
.fetch_take_exception_branch_i(fetch_take_exception_branch_o), // Templated
|
375 |
|
|
.execute_waiting_i (execute_waiting_o), // Templated
|
376 |
|
|
.du_stall_i (du_stall_i),
|
377 |
|
|
.stepping_i (stepping_o), // Templated
|
378 |
|
|
.flag_i (flag_o), // Templated
|
379 |
|
|
.flag_clear_i (flag_clear_o), // Templated
|
380 |
|
|
.flag_set_i (flag_set_o), // Templated
|
381 |
|
|
.spr_bus_addr_i (spr_bus_addr_o[15:0]), // Templated
|
382 |
|
|
.spr_bus_we_i (spr_bus_we_o), // Templated
|
383 |
|
|
.spr_bus_stb_i (spr_bus_stb_o), // Templated
|
384 |
|
|
.spr_bus_dat_i (spr_bus_dat_o[OPTION_OPERAND_WIDTH-1:0])); // Templated
|
385 |
|
|
end // else: !if(OPTION_TCM_FETCHER=="ENABLED")
|
386 |
|
|
endgenerate
|
387 |
|
|
|
388 |
|
|
/* mor1kx_decode AUTO_TEMPLATE (
|
389 |
|
|
.decode_insn_i (insn_fetch_to_decode),
|
390 |
|
|
.decode_op_lsu_atomic_o (),
|
391 |
|
|
); */
|
392 |
|
|
mor1kx_decode
|
393 |
|
|
#(
|
394 |
|
|
.OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH),
|
395 |
|
|
.OPTION_RESET_PC(OPTION_RESET_PC),
|
396 |
|
|
.OPTION_RF_ADDR_WIDTH(OPTION_RF_ADDR_WIDTH),
|
397 |
|
|
.FEATURE_SYSCALL(FEATURE_SYSCALL),
|
398 |
|
|
.FEATURE_TRAP(FEATURE_TRAP),
|
399 |
|
|
.FEATURE_RANGE(FEATURE_RANGE),
|
400 |
|
|
.FEATURE_MAC(FEATURE_MAC),
|
401 |
|
|
.FEATURE_MULTIPLIER(FEATURE_MULTIPLIER),
|
402 |
|
|
.FEATURE_DIVIDER(FEATURE_DIVIDER),
|
403 |
|
|
.FEATURE_ADDC(FEATURE_ADDC),
|
404 |
|
|
.FEATURE_SRA(FEATURE_SRA),
|
405 |
|
|
.FEATURE_ROR(FEATURE_ROR),
|
406 |
|
|
.FEATURE_EXT(FEATURE_EXT),
|
407 |
|
|
.FEATURE_CMOV(FEATURE_CMOV),
|
408 |
|
|
.FEATURE_FFL1(FEATURE_FFL1),
|
409 |
|
|
.FEATURE_MSYNC(FEATURE_MSYNC),
|
410 |
|
|
.FEATURE_PSYNC(FEATURE_PSYNC),
|
411 |
|
|
.FEATURE_CSYNC(FEATURE_CSYNC),
|
412 |
|
|
.FEATURE_CUST1(FEATURE_CUST1),
|
413 |
|
|
.FEATURE_CUST2(FEATURE_CUST2),
|
414 |
|
|
.FEATURE_CUST3(FEATURE_CUST3),
|
415 |
|
|
.FEATURE_CUST4(FEATURE_CUST4),
|
416 |
|
|
.FEATURE_CUST5(FEATURE_CUST5),
|
417 |
|
|
.FEATURE_CUST6(FEATURE_CUST6),
|
418 |
|
|
.FEATURE_CUST7(FEATURE_CUST7),
|
419 |
|
|
.FEATURE_CUST8(FEATURE_CUST8)
|
420 |
|
|
)
|
421 |
|
|
mor1kx_decode
|
422 |
|
|
(/*AUTOINST*/
|
423 |
|
|
// Outputs
|
424 |
|
|
.decode_opc_alu_o (decode_opc_alu_o[`OR1K_ALU_OPC_WIDTH-1:0]),
|
425 |
|
|
.decode_opc_alu_secondary_o (decode_opc_alu_secondary_o[`OR1K_ALU_OPC_WIDTH-1:0]),
|
426 |
|
|
.decode_imm16_o (decode_imm16_o[`OR1K_IMM_WIDTH-1:0]),
|
427 |
|
|
.decode_immediate_o (decode_immediate_o[OPTION_OPERAND_WIDTH-1:0]),
|
428 |
|
|
.decode_immediate_sel_o (decode_immediate_sel_o),
|
429 |
|
|
.decode_immjbr_upper_o (decode_immjbr_upper_o[9:0]),
|
430 |
|
|
.decode_rfd_adr_o (decode_rfd_adr_o[OPTION_RF_ADDR_WIDTH-1:0]),
|
431 |
|
|
.decode_rfa_adr_o (decode_rfa_adr_o[OPTION_RF_ADDR_WIDTH-1:0]),
|
432 |
|
|
.decode_rfb_adr_o (decode_rfb_adr_o[OPTION_RF_ADDR_WIDTH-1:0]),
|
433 |
|
|
.decode_rf_wb_o (decode_rf_wb_o),
|
434 |
|
|
.decode_op_jbr_o (decode_op_jbr_o),
|
435 |
|
|
.decode_op_jr_o (decode_op_jr_o),
|
436 |
|
|
.decode_op_jal_o (decode_op_jal_o),
|
437 |
|
|
.decode_op_bf_o (decode_op_bf_o),
|
438 |
|
|
.decode_op_bnf_o (decode_op_bnf_o),
|
439 |
|
|
.decode_op_brcond_o (decode_op_brcond_o),
|
440 |
|
|
.decode_op_branch_o (decode_op_branch_o),
|
441 |
|
|
.decode_op_alu_o (decode_op_alu_o),
|
442 |
|
|
.decode_op_lsu_load_o (decode_op_lsu_load_o),
|
443 |
|
|
.decode_op_lsu_store_o (decode_op_lsu_store_o),
|
444 |
|
|
.decode_op_lsu_atomic_o (decode_op_lsu_atomic_o),
|
445 |
|
|
.decode_lsu_length_o (decode_lsu_length_o[1:0]),
|
446 |
|
|
.decode_lsu_zext_o (decode_lsu_zext_o),
|
447 |
|
|
.decode_op_mfspr_o (decode_op_mfspr_o),
|
448 |
|
|
.decode_op_mtspr_o (decode_op_mtspr_o),
|
449 |
|
|
.decode_op_rfe_o (decode_op_rfe_o),
|
450 |
|
|
.decode_op_setflag_o (decode_op_setflag_o),
|
451 |
|
|
.decode_op_add_o (decode_op_add_o),
|
452 |
|
|
.decode_op_mul_o (decode_op_mul_o),
|
453 |
|
|
.decode_op_mul_signed_o (decode_op_mul_signed_o),
|
454 |
|
|
.decode_op_mul_unsigned_o (decode_op_mul_unsigned_o),
|
455 |
|
|
.decode_op_div_o (decode_op_div_o),
|
456 |
|
|
.decode_op_div_signed_o (decode_op_div_signed_o),
|
457 |
|
|
.decode_op_div_unsigned_o (decode_op_div_unsigned_o),
|
458 |
|
|
.decode_op_shift_o (decode_op_shift_o),
|
459 |
|
|
.decode_op_ffl1_o (decode_op_ffl1_o),
|
460 |
|
|
.decode_op_movhi_o (decode_op_movhi_o),
|
461 |
|
|
.decode_adder_do_sub_o (decode_adder_do_sub_o),
|
462 |
|
|
.decode_adder_do_carry_o (decode_adder_do_carry_o),
|
463 |
|
|
.decode_except_illegal_o (decode_except_illegal_o),
|
464 |
|
|
.decode_except_syscall_o (decode_except_syscall_o),
|
465 |
|
|
.decode_except_trap_o (decode_except_trap_o),
|
466 |
|
|
.decode_opc_insn_o (decode_opc_insn_o[`OR1K_OPCODE_WIDTH-1:0]),
|
467 |
|
|
// Inputs
|
468 |
|
|
.clk (clk),
|
469 |
|
|
.rst (rst),
|
470 |
|
|
.decode_insn_i (insn_fetch_to_decode)); // Templated
|
471 |
|
|
|
472 |
|
|
/* mor1kx_execute_alu AUTO_TEMPLATE (
|
473 |
|
|
.padv_execute_i (padv_execute_o),
|
474 |
|
|
.padv_ctrl_i (1'b1),
|
475 |
|
|
.opc_alu_i (decode_opc_alu_o),
|
476 |
|
|
.opc_alu_secondary_i (decode_opc_alu_secondary_o),
|
477 |
|
|
.imm16_i (decode_imm16_o),
|
478 |
|
|
.immediate_i (decode_immediate_o),
|
479 |
|
|
.immediate_sel_i (decode_immediate_sel_o),
|
480 |
|
|
.decode_valid_i (padv_decode_o),
|
481 |
|
|
.op_alu_i (decode_op_alu_o),
|
482 |
|
|
.op_add_i (decode_op_add_o),
|
483 |
|
|
.op_mul_i (decode_op_mul_o),
|
484 |
|
|
.op_mul_signed_i (decode_op_mul_signed_o),
|
485 |
|
|
.op_mul_unsigned_i (decode_op_mul_unsigned_o),
|
486 |
|
|
.op_div_i (decode_op_div_o),
|
487 |
|
|
.op_div_signed_i (decode_op_div_signed_o),
|
488 |
|
|
.op_div_unsigned_i (decode_op_div_unsigned_o),
|
489 |
|
|
.op_shift_i (decode_op_shift_o),
|
490 |
|
|
.op_ffl1_i (decode_op_ffl1_o),
|
491 |
|
|
.op_setflag_i (decode_op_setflag_o),
|
492 |
|
|
.op_mtspr_i (decode_op_mtspr_o),
|
493 |
|
|
.op_mfspr_i (decode_op_mfspr_o),
|
494 |
|
|
.op_movhi_i (decode_op_movhi_o),
|
495 |
|
|
.op_jbr_i (decode_op_jbr_o),
|
496 |
|
|
.op_jr_i (decode_op_jr_o),
|
497 |
|
|
.immjbr_upper_i (decode_immjbr_upper_o),
|
498 |
|
|
.pc_execute_i (spr_ppc_o),
|
499 |
|
|
.adder_do_sub_i (decode_adder_do_sub_o),
|
500 |
|
|
.adder_do_carry_i (decode_adder_do_carry_o),
|
501 |
|
|
.rfa_i (rfa_o),
|
502 |
|
|
.rfb_i (rfb_o),
|
503 |
|
|
.flag_i (flag_o),
|
504 |
|
|
.carry_i (carry_o),
|
505 |
|
|
); */
|
506 |
|
|
mor1kx_execute_alu
|
507 |
|
|
#(
|
508 |
|
|
.OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH),
|
509 |
|
|
.FEATURE_MULTIPLIER(FEATURE_MULTIPLIER),
|
510 |
|
|
.FEATURE_DIVIDER(FEATURE_DIVIDER),
|
511 |
|
|
.FEATURE_ADDC(FEATURE_ADDC),
|
512 |
|
|
.FEATURE_SRA(FEATURE_SRA),
|
513 |
|
|
.FEATURE_ROR(FEATURE_ROR),
|
514 |
|
|
.FEATURE_EXT(FEATURE_EXT),
|
515 |
|
|
.FEATURE_CMOV(FEATURE_CMOV),
|
516 |
|
|
.FEATURE_FFL1(FEATURE_FFL1),
|
517 |
|
|
.FEATURE_CUST1(FEATURE_CUST1),
|
518 |
|
|
.FEATURE_CUST2(FEATURE_CUST2),
|
519 |
|
|
.FEATURE_CUST3(FEATURE_CUST3),
|
520 |
|
|
.FEATURE_CUST4(FEATURE_CUST4),
|
521 |
|
|
.FEATURE_CUST5(FEATURE_CUST5),
|
522 |
|
|
.FEATURE_CUST6(FEATURE_CUST6),
|
523 |
|
|
.FEATURE_CUST7(FEATURE_CUST7),
|
524 |
|
|
.FEATURE_CUST8(FEATURE_CUST8),
|
525 |
|
|
.OPTION_SHIFTER(OPTION_SHIFTER)
|
526 |
|
|
)
|
527 |
|
|
mor1kx_execute_alu
|
528 |
|
|
(/*AUTOINST*/
|
529 |
|
|
// Outputs
|
530 |
|
|
.flag_set_o (flag_set_o),
|
531 |
|
|
.flag_clear_o (flag_clear_o),
|
532 |
|
|
.carry_set_o (carry_set_o),
|
533 |
|
|
.carry_clear_o (carry_clear_o),
|
534 |
|
|
.overflow_set_o (overflow_set_o),
|
535 |
|
|
.overflow_clear_o (overflow_clear_o),
|
536 |
|
|
.alu_result_o (alu_result_o[OPTION_OPERAND_WIDTH-1:0]),
|
537 |
|
|
.alu_valid_o (alu_valid_o),
|
538 |
|
|
.mul_result_o (mul_result_o[OPTION_OPERAND_WIDTH-1:0]),
|
539 |
|
|
.adder_result_o (adder_result_o[OPTION_OPERAND_WIDTH-1:0]),
|
540 |
|
|
// Inputs
|
541 |
|
|
.clk (clk),
|
542 |
|
|
.rst (rst),
|
543 |
|
|
.padv_execute_i (padv_execute_o), // Templated
|
544 |
|
|
.padv_ctrl_i (1'b1), // Templated
|
545 |
|
|
.opc_alu_i (decode_opc_alu_o), // Templated
|
546 |
|
|
.opc_alu_secondary_i (decode_opc_alu_secondary_o), // Templated
|
547 |
|
|
.imm16_i (decode_imm16_o), // Templated
|
548 |
|
|
.immediate_i (decode_immediate_o), // Templated
|
549 |
|
|
.immediate_sel_i (decode_immediate_sel_o), // Templated
|
550 |
|
|
.decode_valid_i (padv_decode_o), // Templated
|
551 |
|
|
.op_alu_i (decode_op_alu_o), // Templated
|
552 |
|
|
.op_add_i (decode_op_add_o), // Templated
|
553 |
|
|
.op_mul_i (decode_op_mul_o), // Templated
|
554 |
|
|
.op_mul_signed_i (decode_op_mul_signed_o), // Templated
|
555 |
|
|
.op_mul_unsigned_i (decode_op_mul_unsigned_o), // Templated
|
556 |
|
|
.op_div_i (decode_op_div_o), // Templated
|
557 |
|
|
.op_div_signed_i (decode_op_div_signed_o), // Templated
|
558 |
|
|
.op_div_unsigned_i (decode_op_div_unsigned_o), // Templated
|
559 |
|
|
.op_shift_i (decode_op_shift_o), // Templated
|
560 |
|
|
.op_ffl1_i (decode_op_ffl1_o), // Templated
|
561 |
|
|
.op_setflag_i (decode_op_setflag_o), // Templated
|
562 |
|
|
.op_mtspr_i (decode_op_mtspr_o), // Templated
|
563 |
|
|
.op_mfspr_i (decode_op_mfspr_o), // Templated
|
564 |
|
|
.op_movhi_i (decode_op_movhi_o), // Templated
|
565 |
|
|
.op_jbr_i (decode_op_jbr_o), // Templated
|
566 |
|
|
.op_jr_i (decode_op_jr_o), // Templated
|
567 |
|
|
.immjbr_upper_i (decode_immjbr_upper_o), // Templated
|
568 |
|
|
.pc_execute_i (spr_ppc_o), // Templated
|
569 |
|
|
.adder_do_sub_i (decode_adder_do_sub_o), // Templated
|
570 |
|
|
.adder_do_carry_i (decode_adder_do_carry_o), // Templated
|
571 |
|
|
.rfa_i (rfa_o), // Templated
|
572 |
|
|
.rfb_i (rfb_o), // Templated
|
573 |
|
|
.flag_i (flag_o), // Templated
|
574 |
|
|
.carry_i (carry_o)); // Templated
|
575 |
|
|
|
576 |
|
|
|
577 |
|
|
/* mor1kx_lsu_espresso AUTO_TEMPLATE (
|
578 |
|
|
.padv_fetch_i (padv_fetch_o),
|
579 |
|
|
.lsu_adr_i (adder_result_o),
|
580 |
|
|
.rfb_i (rfb_o),
|
581 |
|
|
.op_lsu_load_i (decode_op_lsu_load_o),
|
582 |
|
|
.op_lsu_store_i (decode_op_lsu_store_o),
|
583 |
|
|
.lsu_length_i (decode_lsu_length_o),
|
584 |
|
|
.lsu_zext_i (decode_lsu_zext_o),
|
585 |
|
|
.exception_taken_i (exception_taken_o),
|
586 |
|
|
.du_restart_i (du_restart_o),
|
587 |
|
|
.stepping_i (stepping_o),
|
588 |
|
|
.next_fetch_done_i (fetch_ready_o),
|
589 |
|
|
); */
|
590 |
|
|
mor1kx_lsu_espresso
|
591 |
|
|
#(
|
592 |
|
|
.OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH)
|
593 |
|
|
)
|
594 |
|
|
mor1kx_lsu_espresso
|
595 |
|
|
(/*AUTOINST*/
|
596 |
|
|
// Outputs
|
597 |
|
|
.lsu_result_o (lsu_result_o[OPTION_OPERAND_WIDTH-1:0]),
|
598 |
|
|
.lsu_valid_o (lsu_valid_o),
|
599 |
|
|
.lsu_except_dbus_o (lsu_except_dbus_o),
|
600 |
|
|
.lsu_except_align_o (lsu_except_align_o),
|
601 |
|
|
.dbus_adr_o (dbus_adr_o[OPTION_OPERAND_WIDTH-1:0]),
|
602 |
|
|
.dbus_req_o (dbus_req_o),
|
603 |
|
|
.dbus_dat_o (dbus_dat_o[OPTION_OPERAND_WIDTH-1:0]),
|
604 |
|
|
.dbus_bsel_o (dbus_bsel_o[3:0]),
|
605 |
|
|
.dbus_we_o (dbus_we_o),
|
606 |
|
|
.dbus_burst_o (dbus_burst_o),
|
607 |
|
|
// Inputs
|
608 |
|
|
.clk (clk),
|
609 |
|
|
.rst (rst),
|
610 |
|
|
.padv_fetch_i (padv_fetch_o), // Templated
|
611 |
|
|
.lsu_adr_i (adder_result_o), // Templated
|
612 |
|
|
.rfb_i (rfb_o), // Templated
|
613 |
|
|
.op_lsu_load_i (decode_op_lsu_load_o), // Templated
|
614 |
|
|
.op_lsu_store_i (decode_op_lsu_store_o), // Templated
|
615 |
|
|
.lsu_length_i (decode_lsu_length_o), // Templated
|
616 |
|
|
.lsu_zext_i (decode_lsu_zext_o), // Templated
|
617 |
|
|
.exception_taken_i (exception_taken_o), // Templated
|
618 |
|
|
.du_restart_i (du_restart_o), // Templated
|
619 |
|
|
.stepping_i (stepping_o), // Templated
|
620 |
|
|
.next_fetch_done_i (fetch_ready_o), // Templated
|
621 |
|
|
.dbus_err_i (dbus_err_i),
|
622 |
|
|
.dbus_ack_i (dbus_ack_i),
|
623 |
|
|
.dbus_dat_i (dbus_dat_i[OPTION_OPERAND_WIDTH-1:0]));
|
624 |
|
|
|
625 |
|
|
|
626 |
|
|
/* mor1kx_wb_mux_espresso AUTO_TEMPLATE (
|
627 |
|
|
.alu_result_i (alu_result_o),
|
628 |
|
|
.lsu_result_i (lsu_result_o),
|
629 |
|
|
.spr_i (mfspr_dat_o),
|
630 |
|
|
.op_jal_i (decode_op_jal_o),
|
631 |
|
|
.op_lsu_load_i (decode_op_lsu_load_o),
|
632 |
|
|
.ppc_i (spr_ppc_o),
|
633 |
|
|
.op_mfspr_i (decode_op_mfspr_o),
|
634 |
|
|
.pc_fetch_next_i (link_addr_o),
|
635 |
|
|
); */
|
636 |
|
|
mor1kx_wb_mux_espresso
|
637 |
|
|
#(
|
638 |
|
|
.OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH)
|
639 |
|
|
)
|
640 |
|
|
mor1kx_wb_mux_espresso
|
641 |
|
|
(/*AUTOINST*/
|
642 |
|
|
// Outputs
|
643 |
|
|
.rf_result_o (rf_result_o[OPTION_OPERAND_WIDTH-1:0]),
|
644 |
|
|
// Inputs
|
645 |
|
|
.clk (clk),
|
646 |
|
|
.rst (rst),
|
647 |
|
|
.alu_result_i (alu_result_o), // Templated
|
648 |
|
|
.lsu_result_i (lsu_result_o), // Templated
|
649 |
|
|
.ppc_i (spr_ppc_o), // Templated
|
650 |
|
|
.pc_fetch_next_i (link_addr_o), // Templated
|
651 |
|
|
.spr_i (mfspr_dat_o), // Templated
|
652 |
|
|
.op_jal_i (decode_op_jal_o), // Templated
|
653 |
|
|
.op_lsu_load_i (decode_op_lsu_load_o), // Templated
|
654 |
|
|
.op_mfspr_i (decode_op_mfspr_o)); // Templated
|
655 |
|
|
|
656 |
|
|
|
657 |
|
|
/* mor1kx_rf_espresso AUTO_TEMPLATE (
|
658 |
|
|
.rf_we_i (rf_we_o),
|
659 |
|
|
.rf_re_i (fetch_rf_re_o),
|
660 |
|
|
.rfd_adr_i (decode_rfd_adr_o),
|
661 |
|
|
.rfa_adr_i (fetch_rfa_adr_o),
|
662 |
|
|
.rfb_adr_i (fetch_rfb_adr_o),
|
663 |
|
|
.result_i (rf_result_o),
|
664 |
|
|
); */
|
665 |
|
|
mor1kx_rf_espresso
|
666 |
|
|
#(
|
667 |
|
|
.OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH),
|
668 |
|
|
.OPTION_RF_ADDR_WIDTH(OPTION_RF_ADDR_WIDTH),
|
669 |
|
|
.OPTION_RF_WORDS(OPTION_RF_WORDS)
|
670 |
|
|
)
|
671 |
|
|
mor1kx_rf_espresso
|
672 |
|
|
(/*AUTOINST*/
|
673 |
|
|
// Outputs
|
674 |
|
|
.rfa_o (rfa_o[OPTION_OPERAND_WIDTH-1:0]),
|
675 |
|
|
.rfb_o (rfb_o[OPTION_OPERAND_WIDTH-1:0]),
|
676 |
|
|
// Inputs
|
677 |
|
|
.clk (clk),
|
678 |
|
|
.rst (rst),
|
679 |
|
|
.rfd_adr_i (decode_rfd_adr_o), // Templated
|
680 |
|
|
.rfa_adr_i (fetch_rfa_adr_o), // Templated
|
681 |
|
|
.rfb_adr_i (fetch_rfb_adr_o), // Templated
|
682 |
|
|
.rf_we_i (rf_we_o), // Templated
|
683 |
|
|
.rf_re_i (fetch_rf_re_o), // Templated
|
684 |
|
|
.result_i (rf_result_o)); // Templated
|
685 |
|
|
|
686 |
|
|
|
687 |
|
|
/* Debug signals required for the debug monitor */
|
688 |
|
|
function [OPTION_OPERAND_WIDTH-1:0] get_gpr;
|
689 |
|
|
// verilator public
|
690 |
|
|
input [4:0] gpr_num;
|
691 |
|
|
begin
|
692 |
|
|
// If we're writing, the value won't be in the GPR yet, so snoop
|
693 |
|
|
// it off the result in line.
|
694 |
|
|
if (rf_we_o)
|
695 |
|
|
get_gpr = rf_result_o;
|
696 |
|
|
else
|
697 |
|
|
get_gpr = mor1kx_rf_espresso.rfa.mem[gpr_num];
|
698 |
|
|
end
|
699 |
|
|
endfunction //
|
700 |
|
|
|
701 |
|
|
|
702 |
|
|
`ifndef SYNTHESIS
|
703 |
|
|
// synthesis translate_off
|
704 |
|
|
task set_gpr;
|
705 |
|
|
// verilator public
|
706 |
|
|
input [4:0] gpr_num;
|
707 |
|
|
input [OPTION_OPERAND_WIDTH-1:0] gpr_value;
|
708 |
|
|
begin
|
709 |
|
|
mor1kx_rf_espresso.rfa.mem[gpr_num] = gpr_value;
|
710 |
|
|
mor1kx_rf_espresso.rfb.mem[gpr_num] = gpr_value;
|
711 |
|
|
end
|
712 |
|
|
endtask
|
713 |
|
|
// synthesis translate_on
|
714 |
|
|
`endif
|
715 |
|
|
|
716 |
|
|
/* mor1kx_ctrl_prontoespresso AUTO_TEMPLATE (
|
717 |
|
|
.ctrl_alu_result_i (alu_result_o),
|
718 |
|
|
.ctrl_rfb_i (rfb_o),
|
719 |
|
|
.ctrl_flag_set_i (flag_set_o),
|
720 |
|
|
.ctrl_flag_clear_i (flag_clear_o),
|
721 |
|
|
.pc_ctrl_i (),
|
722 |
|
|
.pc_fetch_next_i (pc_fetch_next_o),
|
723 |
|
|
.ctrl_opc_insn_i (decode_opc_insn_o),
|
724 |
|
|
.ctrl_branch_target_i (ctrl_branch_target_o),
|
725 |
|
|
.op_lsu_load_i (decode_op_lsu_load_o),
|
726 |
|
|
.op_lsu_store_i (decode_op_lsu_store_o),
|
727 |
|
|
.alu_valid_i (alu_valid_o),
|
728 |
|
|
.lsu_valid_i (lsu_valid_o),
|
729 |
|
|
.op_jr_i (decode_op_jr_o),
|
730 |
|
|
.op_jbr_i (decode_op_jbr_o),
|
731 |
|
|
.except_ibus_err_i (decode_except_ibus_err_o),
|
732 |
|
|
.except_illegal_i (decode_except_illegal_o),
|
733 |
|
|
.except_syscall_i (decode_except_syscall_o),
|
734 |
|
|
.except_dbus_i (lsu_except_dbus_o),
|
735 |
|
|
.except_trap_i (decode_except_trap_o),
|
736 |
|
|
.except_align_i (lsu_except_align_o),
|
737 |
|
|
.fetch_ready_i (fetch_ready_o),
|
738 |
|
|
.execute_valid_i (execute_valid_o),
|
739 |
|
|
.execute_waiting_i (execute_waiting_o),
|
740 |
|
|
.fetch_branch_taken_i (fetch_branch_taken_o),
|
741 |
|
|
.fetch_ppc_i (fetched_pc_o),
|
742 |
|
|
.fetch_sleep_i (fetch_sleep_o),
|
743 |
|
|
.fetch_quick_branch_i (fetch_quick_branch_o),
|
744 |
|
|
.rf_wb_i (decode_rf_wb_o),
|
745 |
|
|
.spr_bus_dat_dc_i (),
|
746 |
|
|
.spr_bus_ack_dc_i (),
|
747 |
|
|
.carry_set_i (carry_set_o),
|
748 |
|
|
.carry_clear_i (carry_clear_o),
|
749 |
|
|
.overflow_set_i (overflow_set_o),
|
750 |
|
|
.overflow_clear_i (overflow_clear_o),
|
751 |
|
|
); */
|
752 |
|
|
mor1kx_ctrl_prontoespresso
|
753 |
|
|
#(
|
754 |
|
|
.OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH),
|
755 |
|
|
.OPTION_RESET_PC(OPTION_RESET_PC),
|
756 |
|
|
.FEATURE_PIC(FEATURE_PIC),
|
757 |
|
|
.FEATURE_TIMER(FEATURE_TIMER),
|
758 |
|
|
.OPTION_PIC_TRIGGER(OPTION_PIC_TRIGGER),
|
759 |
|
|
.OPTION_PIC_NMI_WIDTH(OPTION_PIC_NMI_WIDTH),
|
760 |
|
|
.FEATURE_DSX(FEATURE_DSX),
|
761 |
|
|
.FEATURE_FASTCONTEXTS(FEATURE_FASTCONTEXTS),
|
762 |
|
|
.FEATURE_OVERFLOW(FEATURE_OVERFLOW),
|
763 |
|
|
.FEATURE_DATACACHE(FEATURE_DATACACHE),
|
764 |
|
|
.OPTION_DCACHE_BLOCK_WIDTH(OPTION_DCACHE_BLOCK_WIDTH),
|
765 |
|
|
.OPTION_DCACHE_SET_WIDTH(OPTION_DCACHE_SET_WIDTH),
|
766 |
|
|
.OPTION_DCACHE_WAYS(OPTION_DCACHE_WAYS),
|
767 |
|
|
.FEATURE_DMMU(FEATURE_DMMU),
|
768 |
|
|
.FEATURE_INSTRUCTIONCACHE(FEATURE_INSTRUCTIONCACHE),
|
769 |
|
|
.OPTION_ICACHE_BLOCK_WIDTH(OPTION_ICACHE_BLOCK_WIDTH),
|
770 |
|
|
.OPTION_ICACHE_SET_WIDTH(OPTION_ICACHE_SET_WIDTH),
|
771 |
|
|
.OPTION_ICACHE_WAYS(OPTION_ICACHE_WAYS),
|
772 |
|
|
.FEATURE_IMMU(FEATURE_IMMU),
|
773 |
|
|
.FEATURE_DEBUGUNIT(FEATURE_DEBUGUNIT),
|
774 |
|
|
.FEATURE_PERFCOUNTERS(FEATURE_PERFCOUNTERS),
|
775 |
|
|
.FEATURE_MAC(FEATURE_MAC),
|
776 |
|
|
.FEATURE_MULTICORE(FEATURE_MULTICORE),
|
777 |
|
|
.FEATURE_SYSCALL(FEATURE_SYSCALL),
|
778 |
|
|
.FEATURE_TRAP(FEATURE_TRAP),
|
779 |
|
|
.FEATURE_RANGE(FEATURE_RANGE)
|
780 |
|
|
)
|
781 |
|
|
mor1kx_ctrl_prontoespresso
|
782 |
|
|
(/*AUTOINST*/
|
783 |
|
|
// Outputs
|
784 |
|
|
.spr_npc_o (spr_npc_o[OPTION_OPERAND_WIDTH-1:0]),
|
785 |
|
|
.spr_ppc_o (spr_ppc_o[OPTION_OPERAND_WIDTH-1:0]),
|
786 |
|
|
.link_addr_o (link_addr_o[OPTION_OPERAND_WIDTH-1:0]),
|
787 |
|
|
.mfspr_dat_o (mfspr_dat_o[OPTION_OPERAND_WIDTH-1:0]),
|
788 |
|
|
.ctrl_mfspr_we_o (ctrl_mfspr_we_o),
|
789 |
|
|
.flag_o (flag_o),
|
790 |
|
|
.carry_o (carry_o),
|
791 |
|
|
.pipeline_flush_o (pipeline_flush_o),
|
792 |
|
|
.padv_fetch_o (padv_fetch_o),
|
793 |
|
|
.padv_decode_o (padv_decode_o),
|
794 |
|
|
.padv_execute_o (padv_execute_o),
|
795 |
|
|
.fetch_take_exception_branch_o (fetch_take_exception_branch_o),
|
796 |
|
|
.exception_taken_o (exception_taken_o),
|
797 |
|
|
.execute_waiting_o (execute_waiting_o),
|
798 |
|
|
.stepping_o (stepping_o),
|
799 |
|
|
.du_dat_o (du_dat_o[OPTION_OPERAND_WIDTH-1:0]),
|
800 |
|
|
.du_ack_o (du_ack_o),
|
801 |
|
|
.du_stall_o (du_stall_o),
|
802 |
|
|
.du_restart_pc_o (du_restart_pc_o[OPTION_OPERAND_WIDTH-1:0]),
|
803 |
|
|
.du_restart_o (du_restart_o),
|
804 |
|
|
.spr_bus_addr_o (spr_bus_addr_o[15:0]),
|
805 |
|
|
.spr_bus_we_o (spr_bus_we_o),
|
806 |
|
|
.spr_bus_stb_o (spr_bus_stb_o),
|
807 |
|
|
.spr_bus_dat_o (spr_bus_dat_o[OPTION_OPERAND_WIDTH-1:0]),
|
808 |
|
|
.spr_sr_o (spr_sr_o[15:0]),
|
809 |
|
|
.ctrl_branch_target_o (ctrl_branch_target_o[OPTION_OPERAND_WIDTH-1:0]),
|
810 |
|
|
.ctrl_insn_done_o (ctrl_insn_done_o),
|
811 |
|
|
.ctrl_branch_occur_o (ctrl_branch_occur_o),
|
812 |
|
|
.rf_we_o (rf_we_o),
|
813 |
|
|
// Inputs
|
814 |
|
|
.clk (clk),
|
815 |
|
|
.rst (rst),
|
816 |
|
|
.ctrl_alu_result_i (alu_result_o), // Templated
|
817 |
|
|
.ctrl_rfb_i (rfb_o), // Templated
|
818 |
|
|
.ctrl_flag_set_i (flag_set_o), // Templated
|
819 |
|
|
.ctrl_flag_clear_i (flag_clear_o), // Templated
|
820 |
|
|
.ctrl_opc_insn_i (decode_opc_insn_o), // Templated
|
821 |
|
|
.fetch_ppc_i (fetched_pc_o), // Templated
|
822 |
|
|
.pc_fetch_next_i (pc_fetch_next_o), // Templated
|
823 |
|
|
.fetch_sleep_i (fetch_sleep_o), // Templated
|
824 |
|
|
.except_ibus_err_i (decode_except_ibus_err_o), // Templated
|
825 |
|
|
.except_illegal_i (decode_except_illegal_o), // Templated
|
826 |
|
|
.except_syscall_i (decode_except_syscall_o), // Templated
|
827 |
|
|
.except_dbus_i (lsu_except_dbus_o), // Templated
|
828 |
|
|
.except_trap_i (decode_except_trap_o), // Templated
|
829 |
|
|
.except_align_i (lsu_except_align_o), // Templated
|
830 |
|
|
.fetch_ready_i (fetch_ready_o), // Templated
|
831 |
|
|
.fetch_quick_branch_i (fetch_quick_branch_o), // Templated
|
832 |
|
|
.alu_valid_i (alu_valid_o), // Templated
|
833 |
|
|
.lsu_valid_i (lsu_valid_o), // Templated
|
834 |
|
|
.op_lsu_load_i (decode_op_lsu_load_o), // Templated
|
835 |
|
|
.op_lsu_store_i (decode_op_lsu_store_o), // Templated
|
836 |
|
|
.op_jr_i (decode_op_jr_o), // Templated
|
837 |
|
|
.op_jbr_i (decode_op_jbr_o), // Templated
|
838 |
|
|
.irq_i (irq_i[31:0]),
|
839 |
|
|
.carry_set_i (carry_set_o), // Templated
|
840 |
|
|
.carry_clear_i (carry_clear_o), // Templated
|
841 |
|
|
.overflow_set_i (overflow_set_o), // Templated
|
842 |
|
|
.overflow_clear_i (overflow_clear_o), // Templated
|
843 |
|
|
.du_addr_i (du_addr_i[15:0]),
|
844 |
|
|
.du_stb_i (du_stb_i),
|
845 |
|
|
.du_dat_i (du_dat_i[OPTION_OPERAND_WIDTH-1:0]),
|
846 |
|
|
.du_we_i (du_we_i),
|
847 |
|
|
.du_stall_i (du_stall_i),
|
848 |
|
|
.spr_bus_dat_dc_i (), // Templated
|
849 |
|
|
.spr_bus_ack_dc_i (), // Templated
|
850 |
|
|
.spr_bus_dat_ic_i (spr_bus_dat_ic_i[OPTION_OPERAND_WIDTH-1:0]),
|
851 |
|
|
.spr_bus_ack_ic_i (spr_bus_ack_ic_i),
|
852 |
|
|
.spr_bus_dat_dmmu_i (spr_bus_dat_dmmu_i[OPTION_OPERAND_WIDTH-1:0]),
|
853 |
|
|
.spr_bus_ack_dmmu_i (spr_bus_ack_dmmu_i),
|
854 |
|
|
.spr_bus_dat_immu_i (spr_bus_dat_immu_i[OPTION_OPERAND_WIDTH-1:0]),
|
855 |
|
|
.spr_bus_ack_immu_i (spr_bus_ack_immu_i),
|
856 |
|
|
.spr_bus_dat_mac_i (spr_bus_dat_mac_i[OPTION_OPERAND_WIDTH-1:0]),
|
857 |
|
|
.spr_bus_ack_mac_i (spr_bus_ack_mac_i),
|
858 |
|
|
.spr_bus_dat_pmu_i (spr_bus_dat_pmu_i[OPTION_OPERAND_WIDTH-1:0]),
|
859 |
|
|
.spr_bus_ack_pmu_i (spr_bus_ack_pmu_i),
|
860 |
|
|
.spr_bus_dat_pcu_i (spr_bus_dat_pcu_i[OPTION_OPERAND_WIDTH-1:0]),
|
861 |
|
|
.spr_bus_ack_pcu_i (spr_bus_ack_pcu_i),
|
862 |
|
|
.spr_bus_dat_fpu_i (spr_bus_dat_fpu_i[OPTION_OPERAND_WIDTH-1:0]),
|
863 |
|
|
.spr_bus_ack_fpu_i (spr_bus_ack_fpu_i),
|
864 |
|
|
.multicore_coreid_i (multicore_coreid_i[OPTION_OPERAND_WIDTH-1:0]),
|
865 |
|
|
.rf_wb_i (decode_rf_wb_o)); // Templated
|
866 |
|
|
|
867 |
|
|
endmodule // mor1kx_cpu_prontoespresso
|