1 |
38 |
alirezamon |
/* ****************************************************************************
|
2 |
|
|
This Source Code Form is subject to the terms of the
|
3 |
|
|
Open Hardware Description License, v. 1.0. If a copy
|
4 |
|
|
of the OHDL was not distributed with this file, You
|
5 |
|
|
can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
|
6 |
|
|
|
7 |
|
|
Description: mor1kx control unit
|
8 |
|
|
|
9 |
|
|
inputs from execute stage
|
10 |
|
|
|
11 |
|
|
generate pipeline controls
|
12 |
|
|
|
13 |
|
|
manage SPRs
|
14 |
|
|
|
15 |
|
|
issue addresses for exceptions to fetch stage
|
16 |
|
|
control branches going to fetch stage
|
17 |
|
|
|
18 |
|
|
contains tick timer
|
19 |
|
|
|
20 |
|
|
contains PIC logic
|
21 |
|
|
|
22 |
|
|
Copyright (C) 2012 Julius Baxter <juliusbaxter@gmail.com>
|
23 |
|
|
Copyright (C) 2012-2013 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
|
24 |
|
|
|
25 |
|
|
***************************************************************************** */
|
26 |
|
|
|
27 |
|
|
`include "mor1kx-defines.v"
|
28 |
|
|
|
29 |
|
|
module mor1kx_ctrl_cappuccino
|
30 |
|
|
#(
|
31 |
|
|
parameter OPTION_OPERAND_WIDTH = 32,
|
32 |
|
|
parameter OPTION_RESET_PC = {{(OPTION_OPERAND_WIDTH-13){1'b0}},
|
33 |
|
|
`OR1K_RESET_VECTOR,8'd0},
|
34 |
|
|
|
35 |
|
|
parameter FEATURE_SYSCALL = "ENABLED",
|
36 |
|
|
parameter FEATURE_TRAP = "ENABLED",
|
37 |
|
|
parameter FEATURE_RANGE = "ENABLED",
|
38 |
|
|
|
39 |
|
|
parameter FEATURE_DATACACHE = "NONE",
|
40 |
|
|
parameter OPTION_DCACHE_BLOCK_WIDTH = 5,
|
41 |
|
|
parameter OPTION_DCACHE_SET_WIDTH = 9,
|
42 |
|
|
parameter OPTION_DCACHE_WAYS = 2,
|
43 |
|
|
parameter FEATURE_DMMU = "NONE",
|
44 |
|
|
parameter OPTION_DMMU_SET_WIDTH = 6,
|
45 |
|
|
parameter OPTION_DMMU_WAYS = 1,
|
46 |
|
|
parameter FEATURE_INSTRUCTIONCACHE = "NONE",
|
47 |
|
|
parameter OPTION_ICACHE_BLOCK_WIDTH = 5,
|
48 |
|
|
parameter OPTION_ICACHE_SET_WIDTH = 9,
|
49 |
|
|
parameter OPTION_ICACHE_WAYS = 2,
|
50 |
|
|
parameter FEATURE_IMMU = "NONE",
|
51 |
|
|
parameter OPTION_IMMU_SET_WIDTH = 6,
|
52 |
|
|
parameter OPTION_IMMU_WAYS = 1,
|
53 |
|
|
parameter FEATURE_TIMER = "ENABLED",
|
54 |
|
|
parameter FEATURE_DEBUGUNIT = "NONE",
|
55 |
|
|
parameter FEATURE_PERFCOUNTERS = "NONE",
|
56 |
|
|
parameter FEATURE_PMU = "NONE",
|
57 |
|
|
parameter FEATURE_MAC = "NONE",
|
58 |
|
|
parameter FEATURE_FPU = "NONE",
|
59 |
|
|
parameter FEATURE_MULTICORE = "NONE",
|
60 |
|
|
|
61 |
|
|
parameter FEATURE_PIC = "ENABLED",
|
62 |
|
|
parameter OPTION_PIC_TRIGGER = "LEVEL",
|
63 |
|
|
parameter OPTION_PIC_NMI_WIDTH = 0,
|
64 |
|
|
|
65 |
|
|
parameter FEATURE_DSX ="NONE",
|
66 |
|
|
parameter FEATURE_FASTCONTEXTS = "NONE",
|
67 |
|
|
parameter OPTION_RF_NUM_SHADOW_GPR = 0,
|
68 |
|
|
parameter FEATURE_OVERFLOW = "NONE",
|
69 |
|
|
parameter FEATURE_CARRY_FLAG = "ENABLED",
|
70 |
|
|
|
71 |
|
|
parameter SPR_SR_WIDTH = 16,
|
72 |
|
|
parameter SPR_SR_RESET_VALUE = 16'h8001
|
73 |
|
|
)
|
74 |
|
|
(
|
75 |
|
|
input clk,
|
76 |
|
|
input rst,
|
77 |
|
|
|
78 |
|
|
// ALU result - either jump target, SPR address
|
79 |
|
|
input [OPTION_OPERAND_WIDTH-1:0] ctrl_alu_result_i,
|
80 |
|
|
|
81 |
|
|
// LSU address, needed for effective address
|
82 |
|
|
input [OPTION_OPERAND_WIDTH-1:0] ctrl_lsu_adr_i,
|
83 |
|
|
|
84 |
|
|
// Operand B from RF might be jump address, might be value for SPR
|
85 |
|
|
input [OPTION_OPERAND_WIDTH-1:0] ctrl_rfb_i,
|
86 |
|
|
|
87 |
|
|
input ctrl_flag_set_i,
|
88 |
|
|
input ctrl_flag_clear_i,
|
89 |
|
|
input atomic_flag_set_i,
|
90 |
|
|
input atomic_flag_clear_i,
|
91 |
|
|
|
92 |
|
|
input [OPTION_OPERAND_WIDTH-1:0] pc_ctrl_i,
|
93 |
|
|
|
94 |
|
|
input ctrl_op_mfspr_i,
|
95 |
|
|
input ctrl_op_mtspr_i,
|
96 |
|
|
input ctrl_op_rfe_i,
|
97 |
|
|
|
98 |
|
|
// Indicate if branch will be taken based on instruction currently in
|
99 |
|
|
// decode stage.
|
100 |
|
|
input decode_branch_i,
|
101 |
|
|
input [OPTION_OPERAND_WIDTH-1:0] decode_branch_target_i,
|
102 |
|
|
|
103 |
|
|
input branch_mispredict_i,
|
104 |
|
|
input [OPTION_OPERAND_WIDTH-1:0] execute_mispredict_target_i,
|
105 |
|
|
|
106 |
|
|
// PC of execute stage (NPC)
|
107 |
|
|
input [OPTION_OPERAND_WIDTH-1:0] pc_execute_i,
|
108 |
|
|
|
109 |
|
|
input execute_op_branch_i,
|
110 |
|
|
|
111 |
|
|
// Exception inputs, registered on output of execute stage
|
112 |
|
|
input except_ibus_err_i,
|
113 |
|
|
input except_itlb_miss_i,
|
114 |
|
|
input except_ipagefault_i,
|
115 |
|
|
input except_ibus_align_i,
|
116 |
|
|
input except_illegal_i,
|
117 |
|
|
input except_syscall_i,
|
118 |
|
|
input except_dbus_i,
|
119 |
|
|
input except_dtlb_miss_i,
|
120 |
|
|
input except_dpagefault_i,
|
121 |
|
|
input except_trap_i,
|
122 |
|
|
input except_align_i,
|
123 |
|
|
|
124 |
|
|
// Inputs from two units that can stall proceedings
|
125 |
|
|
input fetch_valid_i,
|
126 |
|
|
input decode_valid_i,
|
127 |
|
|
input execute_valid_i,
|
128 |
|
|
input ctrl_valid_i,
|
129 |
|
|
|
130 |
|
|
input fetch_exception_taken_i,
|
131 |
|
|
|
132 |
|
|
input decode_bubble_i,
|
133 |
|
|
input execute_bubble_i,
|
134 |
|
|
|
135 |
|
|
// External IRQ lines in
|
136 |
|
|
input [31:0] irq_i,
|
137 |
|
|
|
138 |
|
|
// Exception PC output, used in the lsu to properly signal dbus errors that
|
139 |
|
|
// has went through the store buffer
|
140 |
|
|
output [OPTION_OPERAND_WIDTH-1:0] ctrl_epcr_o,
|
141 |
|
|
// Exception PC input coming from the store buffer
|
142 |
|
|
input [OPTION_OPERAND_WIDTH-1:0] store_buffer_epcr_i,
|
143 |
|
|
|
144 |
|
|
input store_buffer_err_i,
|
145 |
|
|
|
146 |
|
|
// SPR data out
|
147 |
|
|
output [OPTION_OPERAND_WIDTH-1:0] mfspr_dat_o,
|
148 |
|
|
|
149 |
|
|
// WE to RF for l.mfspr
|
150 |
|
|
output ctrl_mfspr_ack_o,
|
151 |
|
|
output ctrl_mtspr_ack_o,
|
152 |
|
|
|
153 |
|
|
// Flag out to branch control, combinatorial
|
154 |
|
|
output ctrl_flag_o,
|
155 |
|
|
|
156 |
|
|
// Arithmetic flags to and from ALU
|
157 |
|
|
output ctrl_carry_o,
|
158 |
|
|
input ctrl_carry_set_i,
|
159 |
|
|
input ctrl_carry_clear_i,
|
160 |
|
|
input ctrl_overflow_set_i,
|
161 |
|
|
input ctrl_overflow_clear_i,
|
162 |
|
|
|
163 |
|
|
// Branch indicator from control unit (l.rfe/exception)
|
164 |
|
|
output ctrl_branch_exception_o,
|
165 |
|
|
// PC out to fetch stage for l.rfe, exceptions
|
166 |
|
|
output [OPTION_OPERAND_WIDTH-1:0] ctrl_branch_except_pc_o,
|
167 |
|
|
|
168 |
|
|
// Clear instructions from decode and fetch stage
|
169 |
|
|
output pipeline_flush_o,
|
170 |
|
|
|
171 |
|
|
// Indicate that a rfe is going on
|
172 |
|
|
output doing_rfe_o,
|
173 |
|
|
|
174 |
|
|
output padv_fetch_o,
|
175 |
|
|
output padv_decode_o,
|
176 |
|
|
output padv_execute_o,
|
177 |
|
|
output padv_ctrl_o,
|
178 |
|
|
|
179 |
|
|
// Debug bus
|
180 |
|
|
input [15:0] du_addr_i,
|
181 |
|
|
input du_stb_i,
|
182 |
|
|
input [OPTION_OPERAND_WIDTH-1:0] du_dat_i,
|
183 |
|
|
input du_we_i,
|
184 |
|
|
output [OPTION_OPERAND_WIDTH-1:0] du_dat_o,
|
185 |
|
|
output du_ack_o,
|
186 |
|
|
// Stall control from debug interface
|
187 |
|
|
input du_stall_i,
|
188 |
|
|
output du_stall_o,
|
189 |
|
|
output [OPTION_OPERAND_WIDTH-1:0] du_restart_pc_o,
|
190 |
|
|
output du_restart_o,
|
191 |
|
|
|
192 |
|
|
// SPR accesses to external units (cache, mmu, etc.)
|
193 |
|
|
output [15:0] spr_bus_addr_o,
|
194 |
|
|
output spr_bus_we_o,
|
195 |
|
|
output spr_bus_stb_o,
|
196 |
|
|
output [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_o,
|
197 |
|
|
input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_dc_i,
|
198 |
|
|
input spr_bus_ack_dc_i,
|
199 |
|
|
input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_ic_i,
|
200 |
|
|
input spr_bus_ack_ic_i,
|
201 |
|
|
input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_dmmu_i,
|
202 |
|
|
input spr_bus_ack_dmmu_i,
|
203 |
|
|
input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_immu_i,
|
204 |
|
|
input spr_bus_ack_immu_i,
|
205 |
|
|
input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_mac_i,
|
206 |
|
|
input spr_bus_ack_mac_i,
|
207 |
|
|
input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_pmu_i,
|
208 |
|
|
input spr_bus_ack_pmu_i,
|
209 |
|
|
input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_pcu_i,
|
210 |
|
|
input spr_bus_ack_pcu_i,
|
211 |
|
|
input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_fpu_i,
|
212 |
|
|
input spr_bus_ack_fpu_i,
|
213 |
|
|
input [OPTION_OPERAND_WIDTH-1:0] spr_gpr_dat_i,
|
214 |
|
|
input spr_gpr_ack_i,
|
215 |
|
|
output [15:0] spr_sr_o,
|
216 |
|
|
|
217 |
|
|
output reg ctrl_bubble_o,
|
218 |
|
|
|
219 |
|
|
input [OPTION_OPERAND_WIDTH-1:0] multicore_coreid_i,
|
220 |
|
|
input [OPTION_OPERAND_WIDTH-1:0] multicore_numcores_i
|
221 |
|
|
);
|
222 |
|
|
|
223 |
|
|
// Internal signals
|
224 |
|
|
reg [SPR_SR_WIDTH-1:0] spr_sr;
|
225 |
|
|
reg [SPR_SR_WIDTH-1:0] spr_esr;
|
226 |
|
|
reg [OPTION_OPERAND_WIDTH-1:0] spr_epcr;
|
227 |
|
|
reg [OPTION_OPERAND_WIDTH-1:0] spr_eear;
|
228 |
|
|
reg [OPTION_OPERAND_WIDTH-1:0] spr_evbar;
|
229 |
|
|
|
230 |
|
|
// Programmable Interrupt Control SPRs
|
231 |
|
|
wire [31:0] spr_picmr;
|
232 |
|
|
wire [31:0] spr_picsr;
|
233 |
|
|
|
234 |
|
|
// Tick Timer SPRs
|
235 |
|
|
wire [31:0] spr_ttmr;
|
236 |
|
|
wire [31:0] spr_ttcr;
|
237 |
|
|
|
238 |
|
|
reg [OPTION_OPERAND_WIDTH-1:0] spr_ppc;
|
239 |
|
|
reg [OPTION_OPERAND_WIDTH-1:0] spr_npc;
|
240 |
|
|
reg execute_delay_slot;
|
241 |
|
|
reg ctrl_delay_slot;
|
242 |
|
|
|
243 |
|
|
wire execute_waiting;
|
244 |
|
|
reg execute_waiting_r;
|
245 |
|
|
|
246 |
|
|
reg decode_execute_halt;
|
247 |
|
|
|
248 |
|
|
reg exception_taken;
|
249 |
|
|
|
250 |
|
|
reg [OPTION_OPERAND_WIDTH-1:0] last_branch_insn_pc;
|
251 |
|
|
reg [OPTION_OPERAND_WIDTH-1:0] last_branch_target_pc;
|
252 |
|
|
reg padv_ctrl;
|
253 |
|
|
|
254 |
|
|
reg exception_r;
|
255 |
|
|
|
256 |
|
|
reg [OPTION_OPERAND_WIDTH-1:0] exception_pc_addr;
|
257 |
|
|
|
258 |
|
|
reg waiting_for_fetch;
|
259 |
|
|
|
260 |
|
|
reg doing_rfe_r;
|
261 |
|
|
wire doing_rfe;
|
262 |
|
|
wire deassert_doing_rfe;
|
263 |
|
|
|
264 |
|
|
wire exception, exception_pending;
|
265 |
|
|
|
266 |
|
|
reg ctrl_stage_exceptions;
|
267 |
|
|
|
268 |
|
|
wire exception_re;
|
269 |
|
|
|
270 |
|
|
wire except_ticktimer;
|
271 |
|
|
wire except_pic;
|
272 |
|
|
|
273 |
|
|
wire except_range;
|
274 |
|
|
|
275 |
|
|
wire [15:0] spr_addr;
|
276 |
|
|
|
277 |
|
|
wire [OPTION_OPERAND_WIDTH-1:0] b;
|
278 |
|
|
|
279 |
|
|
wire deassert_decode_execute_halt;
|
280 |
|
|
|
281 |
|
|
/* Debug SPRs */
|
282 |
|
|
reg [31:0] spr_dmr1;
|
283 |
|
|
reg [31:0] spr_dmr2;
|
284 |
|
|
reg [31:0] spr_dsr;
|
285 |
|
|
reg [31:0] spr_drr;
|
286 |
|
|
|
287 |
|
|
/* DU internal control signals */
|
288 |
|
|
wire du_access;
|
289 |
|
|
reg cpu_stall;
|
290 |
|
|
wire du_restart_from_stall;
|
291 |
|
|
reg [5:0] pstep;
|
292 |
|
|
wire stepping;
|
293 |
|
|
wire stepped_into_delay_slot;
|
294 |
|
|
reg stepped_into_exception;
|
295 |
|
|
reg stepped_into_rfe;
|
296 |
|
|
wire du_npc_write;
|
297 |
|
|
reg du_npc_written;
|
298 |
|
|
wire stall_on_trap;
|
299 |
|
|
|
300 |
|
|
/* Wires for SPR management */
|
301 |
|
|
wire spr_access_valid;
|
302 |
|
|
wire spr_we;
|
303 |
|
|
wire spr_read;
|
304 |
|
|
wire spr_ack;
|
305 |
|
|
wire [OPTION_OPERAND_WIDTH-1:0] spr_write_dat;
|
306 |
|
|
reg [11:0] spr_access;
|
307 |
|
|
wire [11:0] spr_access_ack;
|
308 |
|
|
wire [31:0] spr_internal_read_dat [0:11];
|
309 |
|
|
wire spr_read_access;
|
310 |
|
|
wire spr_write_access;
|
311 |
|
|
wire spr_bus_access;
|
312 |
|
|
reg [OPTION_OPERAND_WIDTH-1:0] spr_sys_group_read;
|
313 |
|
|
|
314 |
|
|
/* Wires from mor1kx_cfgrs module */
|
315 |
|
|
wire [31:0] spr_vr;
|
316 |
|
|
wire [31:0] spr_vr2;
|
317 |
|
|
wire [31:0] spr_avr;
|
318 |
|
|
wire [31:0] spr_upr;
|
319 |
|
|
wire [31:0] spr_cpucfgr;
|
320 |
|
|
wire [31:0] spr_dmmucfgr;
|
321 |
|
|
wire [31:0] spr_immucfgr;
|
322 |
|
|
wire [31:0] spr_dccfgr;
|
323 |
|
|
wire [31:0] spr_iccfgr;
|
324 |
|
|
wire [31:0] spr_dcfgr;
|
325 |
|
|
wire [31:0] spr_pccfgr;
|
326 |
|
|
wire [31:0] spr_fpcsr;
|
327 |
|
|
wire [31:0] spr_isr [0:7];
|
328 |
|
|
|
329 |
|
|
assign b = ctrl_rfb_i;
|
330 |
|
|
|
331 |
|
|
assign ctrl_branch_exception_o = (exception_r | ctrl_op_rfe_i | doing_rfe) &
|
332 |
|
|
!exception_taken;
|
333 |
|
|
assign exception_pending = (except_ibus_err_i | except_ibus_align_i |
|
334 |
|
|
except_illegal_i | except_syscall_i |
|
335 |
|
|
except_dbus_i | except_align_i |
|
336 |
|
|
except_ticktimer | except_range |
|
337 |
|
|
except_pic | except_trap_i |
|
338 |
|
|
except_itlb_miss_i | except_ipagefault_i |
|
339 |
|
|
except_dtlb_miss_i | except_dpagefault_i);
|
340 |
|
|
|
341 |
|
|
assign exception = exception_pending &
|
342 |
|
|
(padv_ctrl & !ctrl_bubble_o | ctrl_stage_exceptions);
|
343 |
|
|
|
344 |
|
|
assign exception_re = exception & !exception_r & !exception_taken;
|
345 |
|
|
|
346 |
|
|
assign except_range = (FEATURE_RANGE!="NONE") ? spr_sr[`OR1K_SPR_SR_OVE] &&
|
347 |
|
|
(spr_sr[`OR1K_SPR_SR_OV] | ctrl_overflow_set_i) &
|
348 |
|
|
!doing_rfe : 0;
|
349 |
|
|
|
350 |
|
|
assign deassert_decode_execute_halt = fetch_exception_taken_i &
|
351 |
|
|
decode_execute_halt;
|
352 |
|
|
|
353 |
|
|
assign ctrl_branch_except_pc_o = (ctrl_op_rfe_i | doing_rfe) ? spr_epcr :
|
354 |
|
|
exception_pc_addr;
|
355 |
|
|
|
356 |
|
|
assign ctrl_epcr_o = ctrl_delay_slot ? pc_ctrl_i - 4 : pc_ctrl_i;
|
357 |
|
|
|
358 |
|
|
always @(posedge clk)
|
359 |
|
|
ctrl_stage_exceptions <= except_align_i | except_dbus_i | except_range |
|
360 |
|
|
except_dtlb_miss_i | except_dpagefault_i;
|
361 |
|
|
|
362 |
|
|
always @(posedge clk)
|
363 |
|
|
if (exception & !exception_r)
|
364 |
|
|
casez(
|
365 |
|
|
{
|
366 |
|
|
except_itlb_miss_i,
|
367 |
|
|
except_ipagefault_i,
|
368 |
|
|
except_ibus_err_i,
|
369 |
|
|
except_illegal_i,
|
370 |
|
|
except_align_i,
|
371 |
|
|
except_ibus_align_i,
|
372 |
|
|
except_syscall_i,
|
373 |
|
|
except_dtlb_miss_i,
|
374 |
|
|
except_dpagefault_i,
|
375 |
|
|
except_trap_i,
|
376 |
|
|
except_dbus_i,
|
377 |
|
|
except_range,
|
378 |
|
|
except_pic,
|
379 |
|
|
except_ticktimer
|
380 |
|
|
}
|
381 |
|
|
)
|
382 |
|
|
14'b1?????????????:
|
383 |
|
|
exception_pc_addr <= spr_evbar |
|
384 |
|
|
{19'd0,`OR1K_ITLB_VECTOR,8'd0};
|
385 |
|
|
14'b01????????????:
|
386 |
|
|
exception_pc_addr <= spr_evbar |
|
387 |
|
|
{19'd0,`OR1K_IPF_VECTOR,8'd0};
|
388 |
|
|
14'b001???????????:
|
389 |
|
|
exception_pc_addr <= spr_evbar |
|
390 |
|
|
{19'd0,`OR1K_BERR_VECTOR,8'd0};
|
391 |
|
|
14'b0001??????????:
|
392 |
|
|
exception_pc_addr <= spr_evbar |
|
393 |
|
|
{19'd0,`OR1K_ILLEGAL_VECTOR,8'd0};
|
394 |
|
|
14'b00001?????????,
|
395 |
|
|
14'b000001????????:
|
396 |
|
|
exception_pc_addr <= spr_evbar |
|
397 |
|
|
{19'd0,`OR1K_ALIGN_VECTOR,8'd0};
|
398 |
|
|
14'b0000001???????:
|
399 |
|
|
exception_pc_addr <= spr_evbar |
|
400 |
|
|
{19'd0,`OR1K_SYSCALL_VECTOR,8'd0};
|
401 |
|
|
14'b00000001??????:
|
402 |
|
|
exception_pc_addr <= spr_evbar |
|
403 |
|
|
{19'd0,`OR1K_DTLB_VECTOR,8'd0};
|
404 |
|
|
14'b000000001?????:
|
405 |
|
|
exception_pc_addr <= spr_evbar |
|
406 |
|
|
{19'd0,`OR1K_DPF_VECTOR,8'd0};
|
407 |
|
|
14'b0000000001????:
|
408 |
|
|
exception_pc_addr <= spr_evbar |
|
409 |
|
|
{19'd0,`OR1K_TRAP_VECTOR,8'd0};
|
410 |
|
|
14'b00000000001???:
|
411 |
|
|
exception_pc_addr <= spr_evbar |
|
412 |
|
|
{19'd0,`OR1K_BERR_VECTOR,8'd0};
|
413 |
|
|
14'b000000000001??:
|
414 |
|
|
exception_pc_addr <= spr_evbar |
|
415 |
|
|
{19'd0,`OR1K_RANGE_VECTOR,8'd0};
|
416 |
|
|
14'b0000000000001?:
|
417 |
|
|
exception_pc_addr <= spr_evbar |
|
418 |
|
|
{19'd0,`OR1K_INT_VECTOR,8'd0};
|
419 |
|
|
//14'b00000000000001:
|
420 |
|
|
default:
|
421 |
|
|
exception_pc_addr <= spr_evbar |
|
422 |
|
|
{19'd0,`OR1K_TT_VECTOR,8'd0};
|
423 |
|
|
endcase // casex (...
|
424 |
|
|
|
425 |
|
|
assign execute_waiting = !execute_valid_i;
|
426 |
|
|
|
427 |
|
|
assign padv_fetch_o = !execute_waiting & !cpu_stall & !decode_bubble_i
|
428 |
|
|
& (!stepping | (stepping & pstep[0] & !fetch_valid_i));
|
429 |
|
|
|
430 |
|
|
assign padv_decode_o = fetch_valid_i & !execute_waiting &
|
431 |
|
|
!decode_execute_halt & !cpu_stall
|
432 |
|
|
& (!stepping | (stepping & pstep[1]));
|
433 |
|
|
|
434 |
|
|
assign padv_execute_o = ((decode_valid_i & !execute_waiting &
|
435 |
|
|
/* Stop fetch before exception branch continuing */
|
436 |
|
|
!(exception_r & fetch_exception_taken_i)) |
|
437 |
|
|
(!execute_waiting & execute_waiting_r &
|
438 |
|
|
fetch_valid_i) |
|
439 |
|
|
// Case where execute became ready before fetch
|
440 |
|
|
// after delay in execute stage
|
441 |
|
|
(waiting_for_fetch & fetch_valid_i)) &
|
442 |
|
|
// Not exceptions occurring
|
443 |
|
|
!decode_execute_halt & !exception_re & !ctrl_op_rfe_i
|
444 |
|
|
& !cpu_stall & (!stepping | (stepping & pstep[2]));
|
445 |
|
|
|
446 |
|
|
assign padv_ctrl_o = padv_ctrl;
|
447 |
|
|
|
448 |
|
|
assign spr_addr = du_access ? du_addr_i : ctrl_alu_result_i[15:0];
|
449 |
|
|
assign ctrl_mfspr_ack_o = spr_ack;
|
450 |
|
|
assign ctrl_mtspr_ack_o = spr_ack;
|
451 |
|
|
|
452 |
|
|
// Pipeline flush
|
453 |
|
|
assign pipeline_flush_o = (padv_ctrl & ctrl_op_rfe_i) |
|
454 |
|
|
(exception_re) |
|
455 |
|
|
cpu_stall;
|
456 |
|
|
|
457 |
|
|
// Flag output
|
458 |
|
|
wire ctrl_flag_clear = ctrl_flag_clear_i | atomic_flag_clear_i;
|
459 |
|
|
wire ctrl_flag_set = ctrl_flag_set_i | atomic_flag_set_i;
|
460 |
|
|
|
461 |
|
|
assign ctrl_flag_o = (!ctrl_flag_clear & spr_sr[`OR1K_SPR_SR_F]) |
|
462 |
|
|
ctrl_flag_set;
|
463 |
|
|
|
464 |
|
|
// Carry output
|
465 |
|
|
assign ctrl_carry_o = FEATURE_CARRY_FLAG!="NONE" &
|
466 |
|
|
(!ctrl_carry_clear_i & spr_sr[`OR1K_SPR_SR_CY] |
|
467 |
|
|
ctrl_carry_set_i);
|
468 |
|
|
|
469 |
|
|
// Ctrl stage pipeline advance signal is one cycle behind execute stage's
|
470 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
471 |
|
|
if (rst)
|
472 |
|
|
padv_ctrl <= 0;
|
473 |
|
|
else
|
474 |
|
|
padv_ctrl <= padv_execute_o;
|
475 |
|
|
|
476 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
477 |
|
|
if (rst)
|
478 |
|
|
execute_waiting_r <= 0;
|
479 |
|
|
else if (!execute_waiting)
|
480 |
|
|
execute_waiting_r <= 0;
|
481 |
|
|
else if (decode_valid_i & execute_waiting)
|
482 |
|
|
execute_waiting_r <= 1;
|
483 |
|
|
|
484 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
485 |
|
|
if (rst)
|
486 |
|
|
decode_execute_halt <= 0;
|
487 |
|
|
else if (du_restart_from_stall)
|
488 |
|
|
decode_execute_halt <= 0;
|
489 |
|
|
else if (decode_execute_halt & deassert_decode_execute_halt)
|
490 |
|
|
decode_execute_halt <= 0;
|
491 |
|
|
else if ((ctrl_op_rfe_i | exception) & !decode_execute_halt &
|
492 |
|
|
!exception_taken)
|
493 |
|
|
decode_execute_halt <= 1;
|
494 |
|
|
|
495 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
496 |
|
|
if (rst)
|
497 |
|
|
exception_r <= 0;
|
498 |
|
|
else if (exception_taken | du_restart_from_stall)
|
499 |
|
|
exception_r <= 0;
|
500 |
|
|
else if (exception & !exception_r)
|
501 |
|
|
exception_r <= 1;
|
502 |
|
|
|
503 |
|
|
// Signal to indicate that the incoming exception or l.rfe has been taken
|
504 |
|
|
// and we're waiting for it to propagate through the pipeline.
|
505 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
506 |
|
|
if (rst)
|
507 |
|
|
exception_taken <= 0;
|
508 |
|
|
else if (exception_taken)
|
509 |
|
|
exception_taken <= 0;
|
510 |
|
|
else if (exception_r & fetch_exception_taken_i)
|
511 |
|
|
exception_taken <= 1;
|
512 |
|
|
|
513 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
514 |
|
|
if (rst)
|
515 |
|
|
last_branch_insn_pc <= 0;
|
516 |
|
|
else if (padv_execute_o & execute_op_branch_i)
|
517 |
|
|
last_branch_insn_pc <= pc_execute_i;
|
518 |
|
|
|
519 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
520 |
|
|
if (rst)
|
521 |
|
|
last_branch_target_pc <= 0;
|
522 |
|
|
else if (padv_execute_o & branch_mispredict_i)
|
523 |
|
|
last_branch_target_pc <= execute_mispredict_target_i;
|
524 |
|
|
else if (padv_decode_o & decode_branch_i)
|
525 |
|
|
last_branch_target_pc <= decode_branch_target_i;
|
526 |
|
|
|
527 |
|
|
// Used to gate execute stage's advance signal in the case where a LSU op has
|
528 |
|
|
// finished before the next instruction has been fetched. Typically this
|
529 |
|
|
// occurs when not using icache and doing lots of memory accesses.
|
530 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
531 |
|
|
if (rst)
|
532 |
|
|
waiting_for_fetch <= 0;
|
533 |
|
|
else if (fetch_valid_i)
|
534 |
|
|
waiting_for_fetch <= 0;
|
535 |
|
|
else if (!execute_waiting & execute_waiting_r & !fetch_valid_i)
|
536 |
|
|
waiting_for_fetch <= 1;
|
537 |
|
|
|
538 |
|
|
|
539 |
|
|
assign doing_rfe = ((padv_ctrl & ctrl_op_rfe_i) | doing_rfe_r) &
|
540 |
|
|
!deassert_doing_rfe;
|
541 |
|
|
|
542 |
|
|
assign doing_rfe_o = doing_rfe;
|
543 |
|
|
|
544 |
|
|
assign deassert_doing_rfe = fetch_exception_taken_i & doing_rfe_r;
|
545 |
|
|
|
546 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
547 |
|
|
if (rst)
|
548 |
|
|
doing_rfe_r <= 0;
|
549 |
|
|
else if (deassert_doing_rfe)
|
550 |
|
|
doing_rfe_r <= 0;
|
551 |
|
|
else if (padv_ctrl)
|
552 |
|
|
doing_rfe_r <= ctrl_op_rfe_i;
|
553 |
|
|
|
554 |
|
|
assign spr_sr_o = spr_sr;
|
555 |
|
|
|
556 |
|
|
// Supervision register
|
557 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
558 |
|
|
if (rst)
|
559 |
|
|
spr_sr <= SPR_SR_RESET_VALUE;
|
560 |
|
|
else if (exception_re)
|
561 |
|
|
begin
|
562 |
|
|
// Go into supervisor mode, disable interrupts, MMUs
|
563 |
|
|
spr_sr[`OR1K_SPR_SR_SM ] <= 1'b1;
|
564 |
|
|
if (FEATURE_TIMER!="NONE")
|
565 |
|
|
spr_sr[`OR1K_SPR_SR_TEE ] <= 1'b0;
|
566 |
|
|
if (FEATURE_PIC!="NONE")
|
567 |
|
|
spr_sr[`OR1K_SPR_SR_IEE ] <= 1'b0;
|
568 |
|
|
if (FEATURE_DMMU!="NONE")
|
569 |
|
|
spr_sr[`OR1K_SPR_SR_DME ] <= 1'b0;
|
570 |
|
|
if (FEATURE_IMMU!="NONE")
|
571 |
|
|
spr_sr[`OR1K_SPR_SR_IME ] <= 1'b0;
|
572 |
|
|
if (FEATURE_DSX!="NONE")
|
573 |
|
|
spr_sr[`OR1K_SPR_SR_DSX ] <= ctrl_delay_slot;
|
574 |
|
|
if (FEATURE_OVERFLOW!="NONE")
|
575 |
|
|
spr_sr[`OR1K_SPR_SR_OVE ] <= 1'b0;
|
576 |
|
|
end
|
577 |
|
|
else if ((spr_we & spr_access[`OR1K_SPR_SYS_BASE] &
|
578 |
|
|
(spr_sr[`OR1K_SPR_SR_SM] & padv_ctrl | du_access)) &&
|
579 |
|
|
`SPR_OFFSET(spr_addr)==`SPR_OFFSET(`OR1K_SPR_SR_ADDR))
|
580 |
|
|
begin
|
581 |
|
|
spr_sr[`OR1K_SPR_SR_SM ] <= spr_write_dat[`OR1K_SPR_SR_SM ];
|
582 |
|
|
|
583 |
|
|
spr_sr[`OR1K_SPR_SR_F ] <= spr_write_dat[`OR1K_SPR_SR_F ];
|
584 |
|
|
|
585 |
|
|
if (FEATURE_TIMER!="NONE")
|
586 |
|
|
spr_sr[`OR1K_SPR_SR_TEE ] <= spr_write_dat[`OR1K_SPR_SR_TEE ];
|
587 |
|
|
|
588 |
|
|
if (FEATURE_PIC!="NONE")
|
589 |
|
|
spr_sr[`OR1K_SPR_SR_IEE ] <= spr_write_dat[`OR1K_SPR_SR_IEE ];
|
590 |
|
|
|
591 |
|
|
if (FEATURE_DATACACHE!="NONE")
|
592 |
|
|
spr_sr[`OR1K_SPR_SR_DCE ] <= spr_write_dat[`OR1K_SPR_SR_DCE ];
|
593 |
|
|
|
594 |
|
|
if (FEATURE_INSTRUCTIONCACHE!="NONE")
|
595 |
|
|
spr_sr[`OR1K_SPR_SR_ICE ] <= spr_write_dat[`OR1K_SPR_SR_ICE ];
|
596 |
|
|
|
597 |
|
|
if (FEATURE_DMMU!="NONE")
|
598 |
|
|
spr_sr[`OR1K_SPR_SR_DME ] <= spr_write_dat[`OR1K_SPR_SR_DME ];
|
599 |
|
|
|
600 |
|
|
if (FEATURE_IMMU!="NONE")
|
601 |
|
|
spr_sr[`OR1K_SPR_SR_IME ] <= spr_write_dat[`OR1K_SPR_SR_IME ];
|
602 |
|
|
|
603 |
|
|
if (FEATURE_FASTCONTEXTS!="NONE")
|
604 |
|
|
spr_sr[`OR1K_SPR_SR_CE ] <= spr_write_dat[`OR1K_SPR_SR_CE ];
|
605 |
|
|
|
606 |
|
|
if (FEATURE_CARRY_FLAG!="NONE")
|
607 |
|
|
spr_sr[`OR1K_SPR_SR_CY] <= spr_write_dat[`OR1K_SPR_SR_CY];
|
608 |
|
|
|
609 |
|
|
if (FEATURE_OVERFLOW!="NONE") begin
|
610 |
|
|
spr_sr[`OR1K_SPR_SR_OV ] <= spr_write_dat[`OR1K_SPR_SR_OV ];
|
611 |
|
|
spr_sr[`OR1K_SPR_SR_OVE ] <= spr_write_dat[`OR1K_SPR_SR_OVE ];
|
612 |
|
|
end
|
613 |
|
|
|
614 |
|
|
if (FEATURE_DSX!="NONE")
|
615 |
|
|
spr_sr[`OR1K_SPR_SR_DSX ] <= spr_write_dat[`OR1K_SPR_SR_DSX ];
|
616 |
|
|
|
617 |
|
|
spr_sr[`OR1K_SPR_SR_EPH ] <= spr_write_dat[`OR1K_SPR_SR_EPH ];
|
618 |
|
|
end
|
619 |
|
|
else if (padv_ctrl)
|
620 |
|
|
begin
|
621 |
|
|
spr_sr[`OR1K_SPR_SR_F ] <= ctrl_flag_set ? 1 :
|
622 |
|
|
ctrl_flag_clear ? 0 :
|
623 |
|
|
spr_sr[`OR1K_SPR_SR_F ];
|
624 |
|
|
|
625 |
|
|
if (FEATURE_CARRY_FLAG!="NONE")
|
626 |
|
|
spr_sr[`OR1K_SPR_SR_CY] <= ctrl_carry_set_i ? 1 :
|
627 |
|
|
ctrl_carry_clear_i ? 0 :
|
628 |
|
|
spr_sr[`OR1K_SPR_SR_CY];
|
629 |
|
|
if (FEATURE_OVERFLOW!="NONE")
|
630 |
|
|
spr_sr[`OR1K_SPR_SR_OV ] <= ctrl_overflow_set_i ? 1 :
|
631 |
|
|
ctrl_overflow_clear_i ? 0 :
|
632 |
|
|
spr_sr[`OR1K_SPR_SR_OV ];
|
633 |
|
|
// Skip FO. TODO: make this even more selective.
|
634 |
|
|
if (ctrl_op_rfe_i)
|
635 |
|
|
spr_sr[14:0] <= spr_esr[14:0];
|
636 |
|
|
end
|
637 |
|
|
|
638 |
|
|
|
639 |
|
|
// Exception SR
|
640 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
641 |
|
|
if (rst)
|
642 |
|
|
spr_esr <= SPR_SR_RESET_VALUE;
|
643 |
|
|
else if (exception_re)
|
644 |
|
|
begin
|
645 |
|
|
spr_esr <= spr_sr;
|
646 |
|
|
if (FEATURE_OVERFLOW!="NONE")
|
647 |
|
|
begin
|
648 |
|
|
if (ctrl_overflow_set_i)
|
649 |
|
|
spr_esr[`OR1K_SPR_SR_OV] <= 1'b1;
|
650 |
|
|
else if (ctrl_overflow_clear_i)
|
651 |
|
|
spr_esr[`OR1K_SPR_SR_OV] <= 1'b0;
|
652 |
|
|
end
|
653 |
|
|
if (FEATURE_CARRY_FLAG!="NONE") begin
|
654 |
|
|
if (ctrl_carry_set_i)
|
655 |
|
|
spr_esr[`OR1K_SPR_SR_CY] <= 1'b1;
|
656 |
|
|
else if (ctrl_carry_clear_i)
|
657 |
|
|
spr_esr[`OR1K_SPR_SR_CY] <= 1'b0;
|
658 |
|
|
end
|
659 |
|
|
end
|
660 |
|
|
else if (spr_we && spr_access[`OR1K_SPR_SYS_BASE] &&
|
661 |
|
|
`SPR_OFFSET(spr_addr)==`SPR_OFFSET(`OR1K_SPR_ESR0_ADDR))
|
662 |
|
|
spr_esr <= spr_write_dat[SPR_SR_WIDTH-1:0];
|
663 |
|
|
|
664 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
665 |
|
|
if (rst)
|
666 |
|
|
ctrl_bubble_o <= 0;
|
667 |
|
|
else if (padv_execute_o)
|
668 |
|
|
ctrl_bubble_o <= execute_bubble_i;
|
669 |
|
|
|
670 |
|
|
// Exception PC
|
671 |
|
|
always @(posedge clk)
|
672 |
|
|
if (exception_re) begin
|
673 |
|
|
if (except_ibus_err_i)
|
674 |
|
|
spr_epcr <= last_branch_insn_pc;
|
675 |
|
|
// Syscall is a special case, we return back to the instruction _after_
|
676 |
|
|
// the syscall instruction, unless the syscall was in a delay slot
|
677 |
|
|
else if (except_syscall_i)
|
678 |
|
|
spr_epcr <= ctrl_delay_slot ? ctrl_epcr_o : pc_ctrl_i + 4;
|
679 |
|
|
else if (store_buffer_err_i)
|
680 |
|
|
spr_epcr <= store_buffer_epcr_i;
|
681 |
|
|
// Don't update EPCR on software breakpoint
|
682 |
|
|
else if (!(stall_on_trap & except_trap_i))
|
683 |
|
|
spr_epcr <= ctrl_epcr_o;
|
684 |
|
|
end else if (spr_we && spr_access[`OR1K_SPR_SYS_BASE] &&
|
685 |
|
|
`SPR_OFFSET(spr_addr)==`SPR_OFFSET(`OR1K_SPR_EPCR0_ADDR)) begin
|
686 |
|
|
spr_epcr <= spr_write_dat;
|
687 |
|
|
end
|
688 |
|
|
|
689 |
|
|
// Exception Effective Address
|
690 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
691 |
|
|
if (rst)
|
692 |
|
|
spr_eear <= {OPTION_OPERAND_WIDTH{1'b0}};
|
693 |
|
|
else if (/*padv_ctrl & exception*/ exception_re)
|
694 |
|
|
begin
|
695 |
|
|
if (except_ibus_err_i | except_itlb_miss_i | except_ipagefault_i)
|
696 |
|
|
spr_eear <= pc_ctrl_i;
|
697 |
|
|
else
|
698 |
|
|
spr_eear <= ctrl_lsu_adr_i;
|
699 |
|
|
end
|
700 |
|
|
|
701 |
|
|
// Track the PC
|
702 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
703 |
|
|
if (rst)
|
704 |
|
|
spr_ppc <= OPTION_RESET_PC;
|
705 |
|
|
else if (padv_ctrl)
|
706 |
|
|
spr_ppc <= pc_ctrl_i;
|
707 |
|
|
|
708 |
|
|
// Generate the NPC for SPR accesses
|
709 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
710 |
|
|
if (rst)
|
711 |
|
|
spr_npc <= OPTION_RESET_PC;
|
712 |
|
|
else if (du_npc_write)
|
713 |
|
|
spr_npc <= du_dat_i;
|
714 |
|
|
else if (du_npc_written)
|
715 |
|
|
spr_npc <= spr_npc;
|
716 |
|
|
else if (stepping) begin
|
717 |
|
|
if (stepped_into_rfe)
|
718 |
|
|
spr_npc <= spr_epcr;
|
719 |
|
|
else if (stepped_into_delay_slot)
|
720 |
|
|
spr_npc <= last_branch_target_pc;
|
721 |
|
|
else if (stepped_into_exception)
|
722 |
|
|
spr_npc <= exception_pc_addr;
|
723 |
|
|
else
|
724 |
|
|
spr_npc <= pc_ctrl_i + 4;
|
725 |
|
|
end else if (stall_on_trap & padv_ctrl & except_trap_i)
|
726 |
|
|
spr_npc <= pc_ctrl_i;
|
727 |
|
|
else if (cpu_stall & padv_ctrl)
|
728 |
|
|
spr_npc <= ctrl_delay_slot ? pc_ctrl_i - 4 : pc_ctrl_i;
|
729 |
|
|
else if (!cpu_stall)
|
730 |
|
|
spr_npc <= pc_execute_i;
|
731 |
|
|
|
732 |
|
|
// Exception Vector Address
|
733 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
734 |
|
|
if (rst)
|
735 |
|
|
spr_evbar <= {OPTION_OPERAND_WIDTH{1'b0}};
|
736 |
|
|
else if (spr_we && spr_access[`OR1K_SPR_SYS_BASE] &&
|
737 |
|
|
`SPR_OFFSET(spr_addr)==`SPR_OFFSET(`OR1K_SPR_EVBAR_ADDR))
|
738 |
|
|
spr_evbar <= {spr_write_dat[OPTION_OPERAND_WIDTH-1:13], 13'd0};
|
739 |
|
|
|
740 |
|
|
// Remember when we're in a delay slot in execute stage.
|
741 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
742 |
|
|
if (rst)
|
743 |
|
|
execute_delay_slot <= 0;
|
744 |
|
|
else if (padv_execute_o)
|
745 |
|
|
execute_delay_slot <= execute_op_branch_i;
|
746 |
|
|
|
747 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
748 |
|
|
if (rst)
|
749 |
|
|
ctrl_delay_slot <= 0;
|
750 |
|
|
else if (padv_execute_o)
|
751 |
|
|
ctrl_delay_slot <= execute_delay_slot;
|
752 |
|
|
|
753 |
|
|
mor1kx_cfgrs
|
754 |
|
|
#(.FEATURE_PIC (FEATURE_PIC),
|
755 |
|
|
.FEATURE_TIMER (FEATURE_TIMER),
|
756 |
|
|
.OPTION_PIC_TRIGGER (OPTION_PIC_TRIGGER),
|
757 |
|
|
.FEATURE_DSX (FEATURE_DSX),
|
758 |
|
|
.FEATURE_FASTCONTEXTS (FEATURE_FASTCONTEXTS),
|
759 |
|
|
.OPTION_RF_NUM_SHADOW_GPR (OPTION_RF_NUM_SHADOW_GPR),
|
760 |
|
|
.FEATURE_OVERFLOW (FEATURE_OVERFLOW),
|
761 |
|
|
.FEATURE_DATACACHE (FEATURE_DATACACHE),
|
762 |
|
|
.OPTION_DCACHE_BLOCK_WIDTH (OPTION_DCACHE_BLOCK_WIDTH),
|
763 |
|
|
.OPTION_DCACHE_SET_WIDTH (OPTION_DCACHE_SET_WIDTH),
|
764 |
|
|
.OPTION_DCACHE_WAYS (OPTION_DCACHE_WAYS),
|
765 |
|
|
.FEATURE_DMMU (FEATURE_DMMU),
|
766 |
|
|
.OPTION_DMMU_SET_WIDTH (OPTION_DMMU_SET_WIDTH),
|
767 |
|
|
.OPTION_DMMU_WAYS (OPTION_DMMU_WAYS),
|
768 |
|
|
.FEATURE_INSTRUCTIONCACHE (FEATURE_INSTRUCTIONCACHE),
|
769 |
|
|
.OPTION_ICACHE_BLOCK_WIDTH (OPTION_ICACHE_BLOCK_WIDTH),
|
770 |
|
|
.OPTION_ICACHE_SET_WIDTH (OPTION_ICACHE_SET_WIDTH),
|
771 |
|
|
.OPTION_ICACHE_WAYS (OPTION_ICACHE_WAYS),
|
772 |
|
|
.FEATURE_IMMU (FEATURE_IMMU),
|
773 |
|
|
.OPTION_IMMU_SET_WIDTH (OPTION_IMMU_SET_WIDTH),
|
774 |
|
|
.OPTION_IMMU_WAYS (OPTION_IMMU_WAYS),
|
775 |
|
|
.FEATURE_DEBUGUNIT (FEATURE_DEBUGUNIT),
|
776 |
|
|
.FEATURE_PERFCOUNTERS (FEATURE_PERFCOUNTERS),
|
777 |
|
|
.FEATURE_MAC (FEATURE_MAC),
|
778 |
|
|
.FEATURE_SYSCALL (FEATURE_SYSCALL),
|
779 |
|
|
.FEATURE_TRAP (FEATURE_TRAP),
|
780 |
|
|
.FEATURE_RANGE (FEATURE_RANGE),
|
781 |
|
|
.FEATURE_DELAYSLOT ("ENABLED"),
|
782 |
|
|
.FEATURE_EVBAR ("ENABLED")
|
783 |
|
|
)
|
784 |
|
|
mor1kx_cfgrs
|
785 |
|
|
(/*AUTOINST*/
|
786 |
|
|
// Outputs
|
787 |
|
|
.spr_vr (spr_vr[31:0]),
|
788 |
|
|
.spr_vr2 (spr_vr2[31:0]),
|
789 |
|
|
.spr_upr (spr_upr[31:0]),
|
790 |
|
|
.spr_cpucfgr (spr_cpucfgr[31:0]),
|
791 |
|
|
.spr_dmmucfgr (spr_dmmucfgr[31:0]),
|
792 |
|
|
.spr_immucfgr (spr_immucfgr[31:0]),
|
793 |
|
|
.spr_dccfgr (spr_dccfgr[31:0]),
|
794 |
|
|
.spr_iccfgr (spr_iccfgr[31:0]),
|
795 |
|
|
.spr_dcfgr (spr_dcfgr[31:0]),
|
796 |
|
|
.spr_pccfgr (spr_pccfgr[31:0]),
|
797 |
|
|
.spr_fpcsr (spr_fpcsr[31:0]),
|
798 |
|
|
.spr_avr (spr_avr[31:0]));
|
799 |
|
|
|
800 |
|
|
/* Implementation-specific registers */
|
801 |
|
|
assign spr_isr[0] = 0;
|
802 |
|
|
assign spr_isr[1] = 0;
|
803 |
|
|
assign spr_isr[2] = 0;
|
804 |
|
|
assign spr_isr[3] = 0;
|
805 |
|
|
assign spr_isr[4] = 0;
|
806 |
|
|
assign spr_isr[5] = 0;
|
807 |
|
|
assign spr_isr[6] = 0;
|
808 |
|
|
assign spr_isr[7] = 0;
|
809 |
|
|
|
810 |
|
|
// System group (0) SPR data out
|
811 |
|
|
always @* begin
|
812 |
|
|
spr_sys_group_read = 0;
|
813 |
|
|
if (spr_access[`OR1K_SPR_SYS_BASE])
|
814 |
|
|
case(`SPR_OFFSET(spr_addr))
|
815 |
|
|
`SPR_OFFSET(`OR1K_SPR_VR_ADDR):
|
816 |
|
|
spr_sys_group_read = spr_vr;
|
817 |
|
|
`SPR_OFFSET(`OR1K_SPR_VR2_ADDR):
|
818 |
|
|
spr_sys_group_read = {spr_vr2[31:8], `MOR1KX_PIPEID_CAPPUCCINO};
|
819 |
|
|
`SPR_OFFSET(`OR1K_SPR_AVR_ADDR):
|
820 |
|
|
spr_sys_group_read = spr_avr;
|
821 |
|
|
`SPR_OFFSET(`OR1K_SPR_UPR_ADDR):
|
822 |
|
|
spr_sys_group_read = spr_upr;
|
823 |
|
|
`SPR_OFFSET(`OR1K_SPR_CPUCFGR_ADDR):
|
824 |
|
|
spr_sys_group_read = spr_cpucfgr;
|
825 |
|
|
`SPR_OFFSET(`OR1K_SPR_DMMUCFGR_ADDR):
|
826 |
|
|
spr_sys_group_read = spr_dmmucfgr;
|
827 |
|
|
`SPR_OFFSET(`OR1K_SPR_IMMUCFGR_ADDR):
|
828 |
|
|
spr_sys_group_read = spr_immucfgr;
|
829 |
|
|
`SPR_OFFSET(`OR1K_SPR_DCCFGR_ADDR):
|
830 |
|
|
spr_sys_group_read = spr_dccfgr;
|
831 |
|
|
`SPR_OFFSET(`OR1K_SPR_ICCFGR_ADDR):
|
832 |
|
|
spr_sys_group_read = spr_iccfgr;
|
833 |
|
|
`SPR_OFFSET(`OR1K_SPR_DCFGR_ADDR):
|
834 |
|
|
spr_sys_group_read = spr_dcfgr;
|
835 |
|
|
`SPR_OFFSET(`OR1K_SPR_PCCFGR_ADDR):
|
836 |
|
|
spr_sys_group_read = spr_pccfgr;
|
837 |
|
|
`SPR_OFFSET(`OR1K_SPR_NPC_ADDR):
|
838 |
|
|
spr_sys_group_read = spr_npc;
|
839 |
|
|
`SPR_OFFSET(`OR1K_SPR_SR_ADDR):
|
840 |
|
|
spr_sys_group_read = {{(OPTION_OPERAND_WIDTH-SPR_SR_WIDTH){1'b0}},
|
841 |
|
|
spr_sr};
|
842 |
|
|
|
843 |
|
|
`SPR_OFFSET(`OR1K_SPR_PPC_ADDR):
|
844 |
|
|
spr_sys_group_read = spr_ppc;
|
845 |
|
|
`SPR_OFFSET(`OR1K_SPR_FPCSR_ADDR):
|
846 |
|
|
spr_sys_group_read = spr_fpcsr;
|
847 |
|
|
`SPR_OFFSET(`OR1K_SPR_EPCR0_ADDR):
|
848 |
|
|
spr_sys_group_read = spr_epcr;
|
849 |
|
|
`SPR_OFFSET(`OR1K_SPR_EEAR0_ADDR):
|
850 |
|
|
spr_sys_group_read = spr_eear;
|
851 |
|
|
`SPR_OFFSET(`OR1K_SPR_ESR0_ADDR):
|
852 |
|
|
spr_sys_group_read = {{(OPTION_OPERAND_WIDTH-SPR_SR_WIDTH){1'b0}},
|
853 |
|
|
spr_esr};
|
854 |
|
|
`SPR_OFFSET(`OR1K_SPR_EVBAR_ADDR):
|
855 |
|
|
spr_sys_group_read = spr_evbar;
|
856 |
|
|
`SPR_OFFSET(`OR1K_SPR_ISR0_ADDR):
|
857 |
|
|
spr_sys_group_read = spr_isr[0];
|
858 |
|
|
`SPR_OFFSET(`OR1K_SPR_ISR0_ADDR) +1:
|
859 |
|
|
spr_sys_group_read = spr_isr[1];
|
860 |
|
|
`SPR_OFFSET(`OR1K_SPR_ISR0_ADDR) +2:
|
861 |
|
|
spr_sys_group_read = spr_isr[2];
|
862 |
|
|
`SPR_OFFSET(`OR1K_SPR_ISR0_ADDR) +3:
|
863 |
|
|
spr_sys_group_read = spr_isr[3];
|
864 |
|
|
`SPR_OFFSET(`OR1K_SPR_ISR0_ADDR) +4:
|
865 |
|
|
spr_sys_group_read = spr_isr[4];
|
866 |
|
|
`SPR_OFFSET(`OR1K_SPR_ISR0_ADDR) +5:
|
867 |
|
|
spr_sys_group_read = spr_isr[5];
|
868 |
|
|
`SPR_OFFSET(`OR1K_SPR_ISR0_ADDR) +6:
|
869 |
|
|
spr_sys_group_read = spr_isr[6];
|
870 |
|
|
`SPR_OFFSET(`OR1K_SPR_ISR0_ADDR) +7:
|
871 |
|
|
spr_sys_group_read = spr_isr[7];
|
872 |
|
|
|
873 |
|
|
`SPR_OFFSET(`OR1K_SPR_COREID_ADDR):
|
874 |
|
|
// If the multicore feature is activated this address returns the
|
875 |
|
|
// core identifier, 0 otherwise
|
876 |
|
|
spr_sys_group_read = (FEATURE_MULTICORE!="NONE") ?
|
877 |
|
|
multicore_coreid_i : 0;
|
878 |
|
|
`SPR_OFFSET(`OR1K_SPR_NUMCORES_ADDR):
|
879 |
|
|
// If the multicore feature is activated this address returns the
|
880 |
|
|
// core identifier, 0 otherwise
|
881 |
|
|
spr_sys_group_read = (FEATURE_MULTICORE!="NONE") ?
|
882 |
|
|
multicore_numcores_i : 0;
|
883 |
|
|
|
884 |
|
|
default:
|
885 |
|
|
// GPR read
|
886 |
|
|
if (spr_addr[10:9] == 2'h2)
|
887 |
|
|
spr_sys_group_read = spr_gpr_dat_i; // Register file
|
888 |
|
|
endcase
|
889 |
|
|
end
|
890 |
|
|
|
891 |
|
|
/* System group read data MUX in */
|
892 |
|
|
assign spr_internal_read_dat[`OR1K_SPR_SYS_BASE] = spr_sys_group_read;
|
893 |
|
|
/* System group ack generation */
|
894 |
|
|
|
895 |
|
|
assign spr_access_ack[`OR1K_SPR_SYS_BASE] = spr_access[`OR1K_SPR_SYS_BASE] &
|
896 |
|
|
((spr_addr[10:9] == 2'h2) ?
|
897 |
|
|
spr_gpr_ack_i : 1);
|
898 |
|
|
|
899 |
|
|
//
|
900 |
|
|
// Generate data to the register file for mfspr operations
|
901 |
|
|
// Read datas are simply ORed since set to 0 when not
|
902 |
|
|
// concerned by spr access.
|
903 |
|
|
//
|
904 |
|
|
assign mfspr_dat_o = spr_internal_read_dat[`OR1K_SPR_SYS_BASE] |
|
905 |
|
|
spr_internal_read_dat[`OR1K_SPR_DMMU_BASE] |
|
906 |
|
|
spr_internal_read_dat[`OR1K_SPR_IMMU_BASE] |
|
907 |
|
|
spr_internal_read_dat[`OR1K_SPR_DC_BASE] |
|
908 |
|
|
spr_internal_read_dat[`OR1K_SPR_IC_BASE] |
|
909 |
|
|
spr_internal_read_dat[`OR1K_SPR_MAC_BASE] |
|
910 |
|
|
spr_internal_read_dat[`OR1K_SPR_DU_BASE] |
|
911 |
|
|
spr_internal_read_dat[`OR1K_SPR_PC_BASE] |
|
912 |
|
|
spr_internal_read_dat[`OR1K_SPR_PM_BASE] |
|
913 |
|
|
spr_internal_read_dat[`OR1K_SPR_PIC_BASE] |
|
914 |
|
|
spr_internal_read_dat[`OR1K_SPR_TT_BASE] |
|
915 |
|
|
spr_internal_read_dat[`OR1K_SPR_FPU_BASE];
|
916 |
|
|
|
917 |
|
|
// PIC SPR control
|
918 |
|
|
generate
|
919 |
|
|
|
920 |
|
|
if (FEATURE_PIC !="NONE") begin : pic
|
921 |
|
|
|
922 |
|
|
/* mor1kx_pic AUTO_TEMPLATE (
|
923 |
|
|
.spr_picsr_o (spr_picsr),
|
924 |
|
|
.spr_picmr_o (spr_picmr),
|
925 |
|
|
.spr_bus_ack (spr_access_ack[`OR1K_SPR_PIC_BASE]),
|
926 |
|
|
.spr_dat_o (spr_internal_read_dat[`OR1K_SPR_PIC_BASE]),
|
927 |
|
|
// Inputs
|
928 |
|
|
.spr_we_i (spr_we),
|
929 |
|
|
.spr_access_i (spr_access[`OR1K_SPR_PIC_BASE])
|
930 |
|
|
.spr_addr_i (spr_addr),
|
931 |
|
|
.spr_dat_i (spr_write_dat),
|
932 |
|
|
);*/
|
933 |
|
|
mor1kx_pic
|
934 |
|
|
#(
|
935 |
|
|
.OPTION_PIC_TRIGGER(OPTION_PIC_TRIGGER),
|
936 |
|
|
.OPTION_PIC_NMI_WIDTH(OPTION_PIC_NMI_WIDTH)
|
937 |
|
|
)
|
938 |
|
|
mor1kx_pic
|
939 |
|
|
(/*AUTOINST*/
|
940 |
|
|
// Outputs
|
941 |
|
|
.spr_picmr_o (spr_picmr), // Templated
|
942 |
|
|
.spr_picsr_o (spr_picsr), // Templated
|
943 |
|
|
.spr_bus_ack (spr_access_ack[`OR1K_SPR_PIC_BASE]), // Templated
|
944 |
|
|
.spr_dat_o (spr_internal_read_dat[`OR1K_SPR_PIC_BASE]), // Templated
|
945 |
|
|
// Inputs
|
946 |
|
|
.clk (clk),
|
947 |
|
|
.rst (rst),
|
948 |
|
|
.irq_i (irq_i[31:0]),
|
949 |
|
|
.spr_access_i (spr_access[`OR1K_SPR_PIC_BASE]), // Templated
|
950 |
|
|
.spr_we_i (spr_we), // Templated
|
951 |
|
|
.spr_addr_i (spr_addr), // Templated
|
952 |
|
|
.spr_dat_i (spr_write_dat)); // Templated
|
953 |
|
|
|
954 |
|
|
|
955 |
|
|
assign except_pic = (|spr_picsr) & spr_sr[`OR1K_SPR_SR_IEE] &
|
956 |
|
|
!ctrl_op_mtspr_i & !doing_rfe;
|
957 |
|
|
end
|
958 |
|
|
else begin
|
959 |
|
|
assign except_pic = 0;
|
960 |
|
|
assign spr_picsr = 0;
|
961 |
|
|
assign spr_picmr = 0;
|
962 |
|
|
assign spr_access_ack[`OR1K_SPR_PIC_BASE] = 0;
|
963 |
|
|
assign spr_internal_read_dat[`OR1K_SPR_PIC_BASE] = 0;
|
964 |
|
|
end // else: !if(FEATURE_PIC !="NONE")
|
965 |
|
|
endgenerate
|
966 |
|
|
|
967 |
|
|
|
968 |
|
|
generate
|
969 |
|
|
if (FEATURE_TIMER!="NONE") begin : tt
|
970 |
|
|
|
971 |
|
|
/* mor1kx_ticktimer AUTO_TEMPLATE (
|
972 |
|
|
.spr_ttmr_o (spr_ttmr),
|
973 |
|
|
.spr_ttcr_o (spr_ttcr),
|
974 |
|
|
.spr_bus_ack (spr_access_ack[`OR1K_SPR_TT_BASE]),
|
975 |
|
|
.spr_dat_o (spr_internal_read_dat[`OR1K_SPR_TT_BASE]),
|
976 |
|
|
// Inputs
|
977 |
|
|
.spr_access_i (spr_access[`OR1K_SPR_TT_BASE]),
|
978 |
|
|
.spr_we_i (spr_we),
|
979 |
|
|
.spr_addr_i (spr_addr),
|
980 |
|
|
.spr_dat_i (spr_write_dat),
|
981 |
|
|
);*/
|
982 |
|
|
mor1kx_ticktimer mor1kx_ticktimer
|
983 |
|
|
(/*AUTOINST*/
|
984 |
|
|
// Outputs
|
985 |
|
|
.spr_ttmr_o (spr_ttmr), // Templated
|
986 |
|
|
.spr_ttcr_o (spr_ttcr), // Templated
|
987 |
|
|
.spr_bus_ack (spr_access_ack[`OR1K_SPR_TT_BASE]), // Templated
|
988 |
|
|
.spr_dat_o (spr_internal_read_dat[`OR1K_SPR_TT_BASE]), // Templated
|
989 |
|
|
// Inputs
|
990 |
|
|
.clk (clk),
|
991 |
|
|
.rst (rst),
|
992 |
|
|
.spr_access_i (spr_access[`OR1K_SPR_TT_BASE]), // Templated
|
993 |
|
|
.spr_we_i (spr_we), // Templated
|
994 |
|
|
.spr_addr_i (spr_addr), // Templated
|
995 |
|
|
.spr_dat_i (spr_write_dat)); // Templated
|
996 |
|
|
|
997 |
|
|
assign except_ticktimer = spr_ttmr[28] & spr_sr[`OR1K_SPR_SR_TEE] &
|
998 |
|
|
!ctrl_op_mtspr_i & !doing_rfe;
|
999 |
|
|
|
1000 |
|
|
end // if (FEATURE_TIMER!="NONE")
|
1001 |
|
|
else begin
|
1002 |
|
|
assign except_ticktimer = 0;
|
1003 |
|
|
assign spr_ttmr = 0;
|
1004 |
|
|
assign spr_ttcr = 0;
|
1005 |
|
|
assign spr_access_ack[`OR1K_SPR_TT_BASE] = 0;
|
1006 |
|
|
assign spr_internal_read_dat[`OR1K_SPR_TT_BASE] = 0;
|
1007 |
|
|
end // else: !if(FEATURE_TIMER!="NONE")
|
1008 |
|
|
endgenerate
|
1009 |
|
|
|
1010 |
|
|
/* SPR access control - allow accesses from either the instructions or from
|
1011 |
|
|
the debug interface */
|
1012 |
|
|
assign spr_read_access = (ctrl_op_mfspr_i | (du_access & !du_we_i));
|
1013 |
|
|
assign spr_write_access = (ctrl_op_mtspr_i | (du_access & du_we_i));
|
1014 |
|
|
|
1015 |
|
|
assign spr_write_dat = du_access ? du_dat_i : b;
|
1016 |
|
|
assign spr_we = spr_write_access & spr_access_valid;
|
1017 |
|
|
assign spr_read = spr_read_access & spr_access_valid;
|
1018 |
|
|
|
1019 |
|
|
/* A bus out to other units that live outside of the control unit */
|
1020 |
|
|
assign spr_bus_addr_o = spr_addr;
|
1021 |
|
|
assign spr_bus_we_o = spr_write_access & spr_access_valid & spr_bus_access;
|
1022 |
|
|
assign spr_bus_stb_o = (spr_read_access | spr_write_access) &
|
1023 |
|
|
spr_access_valid & spr_bus_access;
|
1024 |
|
|
assign spr_bus_dat_o = spr_write_dat;
|
1025 |
|
|
|
1026 |
|
|
/* Select spr */
|
1027 |
|
|
always @(*) begin
|
1028 |
|
|
spr_access <= 0;
|
1029 |
|
|
case(`SPR_BASE(spr_addr))
|
1030 |
|
|
// System group
|
1031 |
|
|
`OR1K_SPR_SYS_BASE:
|
1032 |
|
|
spr_access[`OR1K_SPR_SYS_BASE] <= 1'b1;
|
1033 |
|
|
// DMMU
|
1034 |
|
|
`OR1K_SPR_DMMU_BASE:
|
1035 |
|
|
spr_access[`OR1K_SPR_DMMU_BASE] <= (FEATURE_DMMU!="NONE");
|
1036 |
|
|
// IMMU
|
1037 |
|
|
`OR1K_SPR_IMMU_BASE:
|
1038 |
|
|
spr_access[`OR1K_SPR_IMMU_BASE] <= (FEATURE_IMMU!="NONE");
|
1039 |
|
|
// Data cache
|
1040 |
|
|
`OR1K_SPR_DC_BASE:
|
1041 |
|
|
spr_access[`OR1K_SPR_DC_BASE] <= (FEATURE_DATACACHE!="NONE");
|
1042 |
|
|
// Instruction cache
|
1043 |
|
|
`OR1K_SPR_IC_BASE:
|
1044 |
|
|
spr_access[`OR1K_SPR_IC_BASE] <= (FEATURE_INSTRUCTIONCACHE!= "NONE");
|
1045 |
|
|
// MAC unit
|
1046 |
|
|
`OR1K_SPR_MAC_BASE:
|
1047 |
|
|
spr_access[`OR1K_SPR_MAC_BASE] <= (FEATURE_MAC!="NONE");
|
1048 |
|
|
// Debug unit
|
1049 |
|
|
`OR1K_SPR_DU_BASE:
|
1050 |
|
|
spr_access[`OR1K_SPR_DU_BASE] <= (FEATURE_DEBUGUNIT!="NONE");
|
1051 |
|
|
// Performance counters
|
1052 |
|
|
`OR1K_SPR_PC_BASE:
|
1053 |
|
|
spr_access[`OR1K_SPR_PC_BASE] <= (FEATURE_PERFCOUNTERS!="NONE");
|
1054 |
|
|
// Power Management
|
1055 |
|
|
`OR1K_SPR_PM_BASE:
|
1056 |
|
|
spr_access[`OR1K_SPR_PM_BASE] <= (FEATURE_PMU!="NONE");
|
1057 |
|
|
// PIC
|
1058 |
|
|
`OR1K_SPR_PIC_BASE:
|
1059 |
|
|
spr_access[`OR1K_SPR_PIC_BASE] <= (FEATURE_PIC!="NONE");
|
1060 |
|
|
// Tick timer
|
1061 |
|
|
`OR1K_SPR_TT_BASE:
|
1062 |
|
|
spr_access[`OR1K_SPR_TT_BASE] <= (FEATURE_TIMER!="NONE");
|
1063 |
|
|
// FPU
|
1064 |
|
|
`OR1K_SPR_FPU_BASE:
|
1065 |
|
|
spr_access[`OR1K_SPR_FPU_BASE] <= (FEATURE_FPU!="NONE");
|
1066 |
|
|
/* generate invalid if the group is not present in the design */
|
1067 |
|
|
default:
|
1068 |
|
|
spr_access <= 0;
|
1069 |
|
|
endcase
|
1070 |
|
|
end
|
1071 |
|
|
|
1072 |
|
|
// Is the SPR in the design?
|
1073 |
|
|
assign spr_access_valid = |spr_access;
|
1074 |
|
|
|
1075 |
|
|
assign spr_ack = (|spr_access_ack) | !spr_access_valid;
|
1076 |
|
|
|
1077 |
|
|
/* Is a SPR bus access needed, or is the requested SPR in this file? */
|
1078 |
|
|
assign spr_bus_access = /* Any of the units we don't have in this file */
|
1079 |
|
|
/* System group */
|
1080 |
|
|
!(spr_access[`OR1K_SPR_SYS_BASE] ||
|
1081 |
|
|
/* Debug Group */
|
1082 |
|
|
spr_access[`OR1K_SPR_DU_BASE] ||
|
1083 |
|
|
/* PIC Group */
|
1084 |
|
|
spr_access[`OR1K_SPR_PIC_BASE] ||
|
1085 |
|
|
/* Tick Group */
|
1086 |
|
|
spr_access[`OR1K_SPR_TT_BASE]) ||
|
1087 |
|
|
// GPR
|
1088 |
|
|
(spr_access[`OR1K_SPR_SYS_BASE] &&
|
1089 |
|
|
spr_addr[10:9]==2'h2);
|
1090 |
|
|
|
1091 |
|
|
generate
|
1092 |
|
|
if (FEATURE_DEBUGUNIT!="NONE") begin : du
|
1093 |
|
|
|
1094 |
|
|
reg [OPTION_OPERAND_WIDTH-1:0] du_read_dat;
|
1095 |
|
|
|
1096 |
|
|
reg du_ack;
|
1097 |
|
|
reg du_stall_r;
|
1098 |
|
|
reg [1:0] branch_step;
|
1099 |
|
|
|
1100 |
|
|
assign du_access = du_stb_i;
|
1101 |
|
|
|
1102 |
|
|
// Generate ack back to the debug interface bus
|
1103 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
1104 |
|
|
if (rst)
|
1105 |
|
|
du_ack <= 0;
|
1106 |
|
|
else if (du_ack)
|
1107 |
|
|
du_ack <= 0;
|
1108 |
|
|
else if (du_stb_i) begin
|
1109 |
|
|
du_ack <= spr_ack;
|
1110 |
|
|
end
|
1111 |
|
|
|
1112 |
|
|
assign du_ack_o = du_ack;
|
1113 |
|
|
|
1114 |
|
|
/* Data back to the debug bus */
|
1115 |
|
|
always @(posedge clk)
|
1116 |
|
|
du_read_dat <= mfspr_dat_o;
|
1117 |
|
|
|
1118 |
|
|
assign du_dat_o = du_read_dat;
|
1119 |
|
|
|
1120 |
|
|
always @(posedge clk)
|
1121 |
|
|
if (rst)
|
1122 |
|
|
cpu_stall <= 0;
|
1123 |
|
|
else if (!du_stall_i)
|
1124 |
|
|
cpu_stall <= 0;
|
1125 |
|
|
else if (padv_execute_o & !execute_bubble_i & du_stall_i |
|
1126 |
|
|
du_stall_o)
|
1127 |
|
|
cpu_stall <= 1;
|
1128 |
|
|
|
1129 |
|
|
/* goes out to the debug interface and comes back 1 cycle later
|
1130 |
|
|
via du_stall_i */
|
1131 |
|
|
assign du_stall_o = stepping & pstep[4] |
|
1132 |
|
|
(stall_on_trap & padv_ctrl & except_trap_i);
|
1133 |
|
|
|
1134 |
|
|
/* Pulse to indicate we're restarting after a stall */
|
1135 |
|
|
assign du_restart_from_stall = du_stall_r & !du_stall_i;
|
1136 |
|
|
|
1137 |
|
|
/* NPC debug control logic */
|
1138 |
|
|
assign du_npc_write = (du_we_i && du_addr_i==`OR1K_SPR_NPC_ADDR &&
|
1139 |
|
|
du_ack_o);
|
1140 |
|
|
|
1141 |
|
|
/* Pick the traps-cause-stall bit out of the DSR */
|
1142 |
|
|
assign stall_on_trap = spr_dsr[`OR1K_SPR_DSR_TE];
|
1143 |
|
|
|
1144 |
|
|
/* record if NPC was written while we were stalled.
|
1145 |
|
|
If so, we will use this value for restarting */
|
1146 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
1147 |
|
|
if (rst)
|
1148 |
|
|
du_npc_written <= 0;
|
1149 |
|
|
else if (du_restart_from_stall)
|
1150 |
|
|
du_npc_written <= 0;
|
1151 |
|
|
else if (du_npc_write)
|
1152 |
|
|
du_npc_written <= 1;
|
1153 |
|
|
|
1154 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
1155 |
|
|
if (rst)
|
1156 |
|
|
stepped_into_exception <= 0;
|
1157 |
|
|
else if (du_restart_from_stall)
|
1158 |
|
|
stepped_into_exception <= 0;
|
1159 |
|
|
else if (exception & stepping & (padv_ctrl | ctrl_stage_exceptions))
|
1160 |
|
|
stepped_into_exception <= 1;
|
1161 |
|
|
|
1162 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
1163 |
|
|
if (rst)
|
1164 |
|
|
stepped_into_rfe <= 0;
|
1165 |
|
|
else if (du_restart_from_stall)
|
1166 |
|
|
stepped_into_rfe <= 0;
|
1167 |
|
|
else if (stepping & padv_ctrl)
|
1168 |
|
|
stepped_into_rfe <= ctrl_op_rfe_i;
|
1169 |
|
|
|
1170 |
|
|
assign du_restart_pc_o = spr_npc;
|
1171 |
|
|
|
1172 |
|
|
assign du_restart_o = du_restart_from_stall;
|
1173 |
|
|
|
1174 |
|
|
/* Indicate when we're stepping */
|
1175 |
|
|
assign stepping = spr_dmr1[`OR1K_SPR_DMR1_ST] &
|
1176 |
|
|
spr_dsr[`OR1K_SPR_DSR_TE];
|
1177 |
|
|
|
1178 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
1179 |
|
|
if (rst)
|
1180 |
|
|
pstep <= 0;
|
1181 |
|
|
else if (du_restart_from_stall & stepping)
|
1182 |
|
|
pstep <= 6'h1;
|
1183 |
|
|
else if ((pstep[0] & fetch_valid_i) |
|
1184 |
|
|
/* decode is always single cycle */
|
1185 |
|
|
(pstep[1] & padv_decode_o) |
|
1186 |
|
|
/* execute stage */
|
1187 |
|
|
(pstep[2] & (execute_valid_i | ctrl_stage_exceptions)) |
|
1188 |
|
|
/* ctrl stage */
|
1189 |
|
|
(pstep[3] & (ctrl_valid_i | ctrl_stage_exceptions)) |
|
1190 |
|
|
pstep[4])
|
1191 |
|
|
pstep <= {pstep[4:0],1'b0};
|
1192 |
|
|
|
1193 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
1194 |
|
|
if (rst)
|
1195 |
|
|
branch_step <= 0;
|
1196 |
|
|
else if (du_npc_written)
|
1197 |
|
|
branch_step <= 0;
|
1198 |
|
|
else if (stepping & pstep[2])
|
1199 |
|
|
branch_step <= {branch_step[0], decode_branch_i};
|
1200 |
|
|
else if (!stepping & padv_ctrl)
|
1201 |
|
|
branch_step <= {branch_step[0], ctrl_delay_slot};
|
1202 |
|
|
|
1203 |
|
|
assign stepped_into_delay_slot = branch_step[1] & stepping;
|
1204 |
|
|
|
1205 |
|
|
/* Signals for waveform debuging */
|
1206 |
|
|
wire [31:0] spr_read_data_group_0;
|
1207 |
|
|
assign spr_read_data_group_0 = spr_internal_read_dat[0];
|
1208 |
|
|
wire [31:0] spr_read_data_group_1;
|
1209 |
|
|
assign spr_read_data_group_1 = spr_internal_read_dat[1];
|
1210 |
|
|
wire [31:0] spr_read_data_group_2;
|
1211 |
|
|
assign spr_read_data_group_2 = spr_internal_read_dat[2];
|
1212 |
|
|
wire [31:0] spr_read_data_group_3;
|
1213 |
|
|
assign spr_read_data_group_3 = spr_internal_read_dat[3];
|
1214 |
|
|
wire [31:0] spr_read_data_group_4;
|
1215 |
|
|
assign spr_read_data_group_4 = spr_internal_read_dat[4];
|
1216 |
|
|
wire [31:0] spr_read_data_group_5;
|
1217 |
|
|
assign spr_read_data_group_5 = spr_internal_read_dat[5];
|
1218 |
|
|
wire [31:0] spr_read_data_group_6;
|
1219 |
|
|
assign spr_read_data_group_6 = spr_internal_read_dat[6];
|
1220 |
|
|
wire [31:0] spr_read_data_group_7;
|
1221 |
|
|
assign spr_read_data_group_7 = spr_internal_read_dat[7];
|
1222 |
|
|
wire [31:0] spr_read_data_group_8;
|
1223 |
|
|
assign spr_read_data_group_8 = spr_internal_read_dat[8];
|
1224 |
|
|
wire [31:0] spr_read_data_group_9;
|
1225 |
|
|
assign spr_read_data_group_9 = spr_internal_read_dat[9];
|
1226 |
|
|
|
1227 |
|
|
|
1228 |
|
|
/* always single cycle access */
|
1229 |
|
|
assign spr_access_ack[`OR1K_SPR_DU_BASE] = spr_access[`OR1K_SPR_DU_BASE];
|
1230 |
|
|
assign spr_internal_read_dat[`OR1K_SPR_DU_BASE] =
|
1231 |
|
|
(spr_addr==`OR1K_SPR_DMR1_ADDR) ?
|
1232 |
|
|
spr_dmr1 :
|
1233 |
|
|
(spr_addr==`OR1K_SPR_DMR2_ADDR) ?
|
1234 |
|
|
spr_dmr2 :
|
1235 |
|
|
(spr_addr==`OR1K_SPR_DSR_ADDR) ?
|
1236 |
|
|
spr_dsr :
|
1237 |
|
|
(spr_addr==`OR1K_SPR_DRR_ADDR) ?
|
1238 |
|
|
spr_drr : 0;
|
1239 |
|
|
|
1240 |
|
|
/* Put the incoming stall signal through a register to detect FE */
|
1241 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
1242 |
|
|
if (rst)
|
1243 |
|
|
du_stall_r <= 0;
|
1244 |
|
|
else
|
1245 |
|
|
du_stall_r <= du_stall_i;
|
1246 |
|
|
|
1247 |
|
|
/* DMR1 */
|
1248 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
1249 |
|
|
if (rst)
|
1250 |
|
|
spr_dmr1 <= 0;
|
1251 |
|
|
else if (spr_we && spr_addr==`OR1K_SPR_DMR1_ADDR)
|
1252 |
|
|
spr_dmr1[23:0] <= spr_write_dat[23:0];
|
1253 |
|
|
|
1254 |
|
|
/* DMR2 */
|
1255 |
|
|
always @(posedge clk)
|
1256 |
|
|
spr_dmr2 <= 0;
|
1257 |
|
|
|
1258 |
|
|
/* DSR */
|
1259 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
1260 |
|
|
if (rst)
|
1261 |
|
|
spr_dsr <= 0;
|
1262 |
|
|
else if (spr_we && spr_addr==`OR1K_SPR_DSR_ADDR)
|
1263 |
|
|
spr_dsr[13:0] <= spr_write_dat[13:0];
|
1264 |
|
|
|
1265 |
|
|
/* DRR */
|
1266 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
1267 |
|
|
if (rst)
|
1268 |
|
|
spr_drr <= 0;
|
1269 |
|
|
else if (spr_we && spr_addr==`OR1K_SPR_DRR_ADDR)
|
1270 |
|
|
spr_drr[13:0] <= spr_write_dat[13:0];
|
1271 |
|
|
else if (stall_on_trap & padv_ctrl & except_trap_i)
|
1272 |
|
|
spr_drr[`OR1K_SPR_DRR_TE] <= 1;
|
1273 |
|
|
|
1274 |
|
|
end // block: du
|
1275 |
|
|
else
|
1276 |
|
|
begin : no_du
|
1277 |
|
|
assign du_access = 0;
|
1278 |
|
|
assign du_stall_o = 0;
|
1279 |
|
|
assign du_ack_o = 0;
|
1280 |
|
|
assign du_restart_o = 0;
|
1281 |
|
|
assign du_restart_pc_o = 0;
|
1282 |
|
|
assign stepping = 0;
|
1283 |
|
|
assign du_npc_write = 0;
|
1284 |
|
|
assign stepped_into_delay_slot = 0;
|
1285 |
|
|
assign du_dat_o = 0;
|
1286 |
|
|
assign du_restart_from_stall = 0;
|
1287 |
|
|
assign spr_access_ack[`OR1K_SPR_DU_BASE] = 0;
|
1288 |
|
|
assign spr_internal_read_dat[`OR1K_SPR_DU_BASE] = 0;
|
1289 |
|
|
always @(posedge clk)
|
1290 |
|
|
begin
|
1291 |
|
|
spr_dmr1 <= 0;
|
1292 |
|
|
spr_dmr2 <= 0;
|
1293 |
|
|
spr_dsr <= 0;
|
1294 |
|
|
spr_drr <= 0;
|
1295 |
|
|
du_npc_written <= 0;
|
1296 |
|
|
cpu_stall <= 0;
|
1297 |
|
|
end
|
1298 |
|
|
end
|
1299 |
|
|
endgenerate
|
1300 |
|
|
|
1301 |
|
|
// Controls to generate ACKs from units that are external to this module
|
1302 |
|
|
generate
|
1303 |
|
|
if (FEATURE_DMMU!="NONE") begin : dmmu_ctrl
|
1304 |
|
|
assign spr_access_ack[`OR1K_SPR_DMMU_BASE] = spr_bus_ack_dmmu_i &
|
1305 |
|
|
spr_access[`OR1K_SPR_DMMU_BASE];
|
1306 |
|
|
assign spr_internal_read_dat[`OR1K_SPR_DMMU_BASE] =
|
1307 |
|
|
spr_bus_dat_dmmu_i &
|
1308 |
|
|
{OPTION_OPERAND_WIDTH{spr_access[`OR1K_SPR_DMMU_BASE]}};
|
1309 |
|
|
end else begin
|
1310 |
|
|
assign spr_access_ack[`OR1K_SPR_DMMU_BASE] = 0;
|
1311 |
|
|
assign spr_internal_read_dat[`OR1K_SPR_DMMU_BASE] = 0;
|
1312 |
|
|
end
|
1313 |
|
|
endgenerate
|
1314 |
|
|
|
1315 |
|
|
generate
|
1316 |
|
|
if (FEATURE_IMMU!="NONE") begin : immu_ctrl
|
1317 |
|
|
assign spr_access_ack[`OR1K_SPR_IMMU_BASE] = spr_bus_ack_immu_i &
|
1318 |
|
|
spr_access[`OR1K_SPR_IMMU_BASE];
|
1319 |
|
|
assign spr_internal_read_dat[`OR1K_SPR_IMMU_BASE] =
|
1320 |
|
|
spr_bus_dat_immu_i &
|
1321 |
|
|
{OPTION_OPERAND_WIDTH{spr_access[`OR1K_SPR_IMMU_BASE]}};
|
1322 |
|
|
end else begin
|
1323 |
|
|
assign spr_access_ack[`OR1K_SPR_IMMU_BASE] = 0;
|
1324 |
|
|
assign spr_internal_read_dat[`OR1K_SPR_IMMU_BASE] = 0;
|
1325 |
|
|
end
|
1326 |
|
|
endgenerate
|
1327 |
|
|
|
1328 |
|
|
generate
|
1329 |
|
|
if (FEATURE_DATACACHE!="NONE") begin : datacache_ctrl
|
1330 |
|
|
assign spr_access_ack[`OR1K_SPR_DC_BASE] = spr_bus_ack_dc_i &
|
1331 |
|
|
spr_access[`OR1K_SPR_DC_BASE];
|
1332 |
|
|
assign spr_internal_read_dat[`OR1K_SPR_DC_BASE] =
|
1333 |
|
|
spr_bus_dat_dc_i & {OPTION_OPERAND_WIDTH{spr_access[`OR1K_SPR_DC_BASE]}};
|
1334 |
|
|
end else begin
|
1335 |
|
|
assign spr_access_ack[`OR1K_SPR_DC_BASE] = 0;
|
1336 |
|
|
assign spr_internal_read_dat[`OR1K_SPR_DC_BASE] = 0;
|
1337 |
|
|
end
|
1338 |
|
|
endgenerate
|
1339 |
|
|
|
1340 |
|
|
generate
|
1341 |
|
|
if (FEATURE_INSTRUCTIONCACHE!="NONE") begin : instructioncache_ctrl
|
1342 |
|
|
assign spr_access_ack[`OR1K_SPR_IC_BASE] = spr_bus_ack_ic_i &
|
1343 |
|
|
spr_access[`OR1K_SPR_IC_BASE];
|
1344 |
|
|
assign spr_internal_read_dat[`OR1K_SPR_IC_BASE] =
|
1345 |
|
|
spr_bus_dat_ic_i & {OPTION_OPERAND_WIDTH{spr_access[`OR1K_SPR_IC_BASE]}};
|
1346 |
|
|
end else begin
|
1347 |
|
|
assign spr_access_ack[`OR1K_SPR_IC_BASE] = 0;
|
1348 |
|
|
assign spr_internal_read_dat[`OR1K_SPR_IC_BASE] = 0;
|
1349 |
|
|
end
|
1350 |
|
|
endgenerate
|
1351 |
|
|
|
1352 |
|
|
generate
|
1353 |
|
|
if (FEATURE_MAC!="NONE") begin : mac_ctrl
|
1354 |
|
|
assign spr_access_ack[`OR1K_SPR_MAC_BASE] = spr_bus_ack_mac_i &
|
1355 |
|
|
spr_access[`OR1K_SPR_MAC_BASE];
|
1356 |
|
|
assign spr_internal_read_dat[`OR1K_SPR_MAC_BASE] =
|
1357 |
|
|
spr_bus_dat_mac_i &
|
1358 |
|
|
{OPTION_OPERAND_WIDTH{spr_access[`OR1K_SPR_MAC_BASE]}};
|
1359 |
|
|
end else begin
|
1360 |
|
|
assign spr_access_ack[`OR1K_SPR_MAC_BASE] = 0;
|
1361 |
|
|
assign spr_internal_read_dat[`OR1K_SPR_MAC_BASE] = 0;
|
1362 |
|
|
end
|
1363 |
|
|
endgenerate
|
1364 |
|
|
|
1365 |
|
|
generate
|
1366 |
|
|
if (FEATURE_PERFCOUNTERS!="NONE") begin : perfcounters_ctrl
|
1367 |
|
|
assign spr_access_ack[`OR1K_SPR_PC_BASE] = spr_bus_ack_pcu_i &
|
1368 |
|
|
spr_access[`OR1K_SPR_PC_BASE];
|
1369 |
|
|
assign spr_internal_read_dat[`OR1K_SPR_PC_BASE] =
|
1370 |
|
|
spr_bus_dat_pcu_i & {OPTION_OPERAND_WIDTH{spr_access[`OR1K_SPR_PC_BASE]}};
|
1371 |
|
|
end else begin
|
1372 |
|
|
assign spr_access_ack[`OR1K_SPR_PC_BASE] = 0;
|
1373 |
|
|
assign spr_internal_read_dat[`OR1K_SPR_PC_BASE] = 0;
|
1374 |
|
|
end
|
1375 |
|
|
endgenerate
|
1376 |
|
|
|
1377 |
|
|
generate
|
1378 |
|
|
if (FEATURE_PMU!="NONE") begin : pmu_ctrl
|
1379 |
|
|
assign spr_access_ack[`OR1K_SPR_PM_BASE] = spr_bus_ack_pmu_i &
|
1380 |
|
|
spr_access[`OR1K_SPR_PM_BASE];
|
1381 |
|
|
assign spr_internal_read_dat[`OR1K_SPR_PM_BASE] =
|
1382 |
|
|
spr_bus_dat_pmu_i & {OPTION_OPERAND_WIDTH{spr_access[`OR1K_SPR_PM_BASE]}};
|
1383 |
|
|
end else begin
|
1384 |
|
|
assign spr_access_ack[`OR1K_SPR_PM_BASE] = 0;
|
1385 |
|
|
assign spr_internal_read_dat[`OR1K_SPR_PM_BASE] = 0;
|
1386 |
|
|
end
|
1387 |
|
|
endgenerate
|
1388 |
|
|
|
1389 |
|
|
generate
|
1390 |
|
|
if (FEATURE_FPU!="NONE") begin : fpu_ctrl
|
1391 |
|
|
assign spr_access_ack[`OR1K_SPR_FPU_BASE] = spr_bus_ack_fpu_i;
|
1392 |
|
|
assign spr_internal_read_dat[`OR1K_SPR_FPU_BASE] =
|
1393 |
|
|
spr_bus_dat_fpu_i &
|
1394 |
|
|
{OPTION_OPERAND_WIDTH{spr_access[`OR1K_SPR_FPU_BASE]}};
|
1395 |
|
|
end else begin
|
1396 |
|
|
assign spr_access_ack[`OR1K_SPR_FPU_BASE] = 0;
|
1397 |
|
|
assign spr_internal_read_dat[`OR1K_SPR_FPU_BASE] = 0;
|
1398 |
|
|
end
|
1399 |
|
|
endgenerate
|
1400 |
|
|
|
1401 |
|
|
endmodule // mor1kx_ctrl_cappuccino
|