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alirezamon |
/* ****************************************************************************
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This Source Code Form is subject to the terms of the
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Open Hardware Description License, v. 1.0. If a copy
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of the OHDL was not distributed with this file, You
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can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
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Description: mor1kx espresso fetch unit
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Fetch insn, advance PC (or take new branch address) on padv_i.
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What we might want to do is have a 1-insn buffer here, so when the current
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insn is fetched, but the main pipeline doesn't want it yet
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indicate ibus errors
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Copyright (C) 2012 Authors
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Author(s): Julius Baxter <juliusbaxter@gmail.com>
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***************************************************************************** */
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`include "mor1kx-defines.v"
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module mor1kx_fetch_espresso
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(/*AUTOARG*/
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// Outputs
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ibus_adr_o, ibus_req_o, ibus_burst_o, decode_insn_o,
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next_fetch_done_o, fetch_rfa_adr_o, fetch_rfb_adr_o, pc_fetch_o,
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pc_fetch_next_o, decode_except_ibus_err_o, fetch_advancing_o,
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// Inputs
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clk, rst, ibus_err_i, ibus_ack_i, ibus_dat_i, padv_i,
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branch_occur_i, branch_dest_i, du_restart_i, du_restart_pc_i,
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fetch_take_exception_branch_i, execute_waiting_i, du_stall_i,
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stepping_i
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);
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parameter OPTION_OPERAND_WIDTH = 32;
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parameter OPTION_RF_ADDR_WIDTH = 5;
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parameter OPTION_RESET_PC = {{(OPTION_OPERAND_WIDTH-13){1'b0}},
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`OR1K_RESET_VECTOR,8'd0};
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input clk, rst;
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// interface to ibus
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output [OPTION_OPERAND_WIDTH-1:0] ibus_adr_o;
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output ibus_req_o;
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output ibus_burst_o;
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input ibus_err_i;
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input ibus_ack_i;
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input [`OR1K_INSN_WIDTH-1:0] ibus_dat_i;
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// pipeline control input
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input padv_i;
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// interface to decode unit
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output reg [`OR1K_INSN_WIDTH-1:0] decode_insn_o;
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// Indication to pipeline control that the fetch is valid
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output next_fetch_done_o;
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output [OPTION_RF_ADDR_WIDTH-1:0] fetch_rfa_adr_o;
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output [OPTION_RF_ADDR_WIDTH-1:0] fetch_rfb_adr_o;
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// Signal back to the control
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output [OPTION_OPERAND_WIDTH-1:0] pc_fetch_o;
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output [OPTION_OPERAND_WIDTH-1:0] pc_fetch_next_o;
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// branch/jump indication
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input branch_occur_i;
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input [OPTION_OPERAND_WIDTH-1:0] branch_dest_i;
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// restart signals from debug unit
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input du_restart_i;
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input [OPTION_OPERAND_WIDTH-1:0] du_restart_pc_i;
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input fetch_take_exception_branch_i;
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input execute_waiting_i;
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// CPU is stalled
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input du_stall_i;
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// We're single stepping - this should cause us to fetch only a single insn
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input stepping_i;
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// instruction ibus error indication out
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output reg decode_except_ibus_err_o;
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output fetch_advancing_o;
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// registers
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reg [OPTION_OPERAND_WIDTH-1:0] pc_fetch;
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reg fetch_req;
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reg next_insn_buffered;
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reg [OPTION_OPERAND_WIDTH-1:0] insn_buffer;
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reg branch_occur_r;
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reg bus_access_done_re_r;
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reg advancing_into_branch;
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reg bus_access_done_r;
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reg wait_for_exception_after_ibus_err;
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wire [OPTION_OPERAND_WIDTH-1:0] pc_fetch_next;
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wire bus_access_done;
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wire bus_access_done_fe;
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wire branch_occur_re;
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wire awkward_transition_to_branch_target;
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wire taking_branch;
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wire jal_buffered;
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wire retain_fetch_pc;
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assign taking_branch = branch_occur_i & padv_i;
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assign bus_access_done = (ibus_ack_i | ibus_err_i) & !(taking_branch);
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assign pc_fetch_next = pc_fetch + 4;
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assign ibus_adr_o = pc_fetch;
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assign ibus_req_o = fetch_req;
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assign ibus_burst_o = 0;
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assign fetch_advancing_o = (padv_i | fetch_take_exception_branch_i |
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stepping_i) &
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next_fetch_done_o;
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// Early RF address fetch
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assign fetch_rfa_adr_o = insn_buffer[`OR1K_RA_SELECT];
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assign fetch_rfb_adr_o = insn_buffer[`OR1K_RB_SELECT];
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assign jal_buffered = insn_buffer[`OR1K_OPCODE_SELECT]==`OR1K_OPCODE_JALR ||
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insn_buffer[`OR1K_OPCODE_SELECT]==`OR1K_OPCODE_JAL;
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assign retain_fetch_pc = jal_buffered & bus_access_done;
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always @(posedge clk `OR_ASYNC_RST)
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if (rst)
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pc_fetch <= OPTION_RESET_PC;
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else if (fetch_take_exception_branch_i |
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(((bus_access_done & !ibus_err_i) | taking_branch) &
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(!execute_waiting_i | !next_insn_buffered) &
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!retain_fetch_pc) |
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awkward_transition_to_branch_target |
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du_restart_i)
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// next PC - are we going somewhere else or advancing?
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pc_fetch <= du_restart_i ? du_restart_pc_i :
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(fetch_take_exception_branch_i | taking_branch) ?
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branch_dest_i : pc_fetch_next;
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// Actually goes to pipeline control
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assign pc_fetch_o = pc_fetch;
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assign pc_fetch_next_o = pc_fetch_next;
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always @(posedge clk `OR_ASYNC_RST)
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if (rst)
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fetch_req <= 1;
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else if (fetch_take_exception_branch_i | du_restart_i)
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fetch_req <= 1;
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else if (padv_i)
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// Force de-assert of req signal when branching.
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// This is to stop (ironically) the case where we've got the
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// instruction we're branching to already coming in on the bus,
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// which we usually don't assume will happen.
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// TODO: fix things so that we don't have to force a penalty to make
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// it work properly.
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fetch_req <= !branch_occur_i & !du_stall_i;
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else if (du_stall_i)
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fetch_req <= fetch_req & !bus_access_done;
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else if (!fetch_req & !execute_waiting_i &
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!wait_for_exception_after_ibus_err & !retain_fetch_pc &
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!du_stall_i & !stepping_i)
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fetch_req <= 1;
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else if (bus_access_done & (fetch_take_exception_branch_i |
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execute_waiting_i | ibus_err_i | stepping_i))
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fetch_req <= 0;
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always @(posedge clk `OR_ASYNC_RST)
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if (rst)
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begin
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bus_access_done_r <= 0;
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branch_occur_r <= 0;
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end
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else
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begin
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bus_access_done_r <= bus_access_done;
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branch_occur_r <= branch_occur_i;
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end
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always @(posedge clk `OR_ASYNC_RST)
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if (rst)
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advancing_into_branch <= 0;
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else
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advancing_into_branch <= fetch_advancing_o & branch_occur_i;
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assign next_fetch_done_o = (bus_access_done_r | next_insn_buffered) &
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// Whenever we've just changed the fetch PC to
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// take a branch this will gate off any ACKs we
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// might get (legit or otherwise) from where we're
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// getting our instructions from (bus/cache).
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!(advancing_into_branch);
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assign branch_occur_re = branch_occur_i & !branch_occur_r;
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/* When this occurs we had the insn burst stream finish just as we
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had a new branch address requested. Because the control logic will
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immediately continue onto the delay slot instruction, the branch target
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is only valid for 1 cycle. The PC out to the bus/cache will then need
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to change 1 cycle after it requested the insn after the delay slot.
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This is annoying for the bus control/cache logic, but should result in
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less cycles wasted fetching something we don't need, and as well reduce
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the number of flops as we don't need to save the target PC which we had
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for only 1 cycle */
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assign awkward_transition_to_branch_target = branch_occur_re &
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bus_access_done_fe;
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always @(posedge clk `OR_ASYNC_RST)
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if (rst)
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decode_insn_o <= {`OR1K_OPCODE_NOP,26'd0};
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else if (fetch_take_exception_branch_i | (du_stall_i & !execute_waiting_i))
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// Put a NOP in the pipeline when starting exception - remove any state
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// which may be causing the exception
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decode_insn_o <= {`OR1K_OPCODE_NOP,26'd0};
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else if ((padv_i & (
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bus_access_done_r |
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bus_access_done |
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next_insn_buffered
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) &
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!branch_occur_r ) |
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// This case is when we stalled to get the delay-slot instruction
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// and we don't get enough padv to push it through the buffer
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(branch_occur_i & padv_i & bus_access_done_re_r) |
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(bus_access_done_fe & stepping_i))
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decode_insn_o <= insn_buffer;
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always @(posedge clk `OR_ASYNC_RST)
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if (rst)
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decode_except_ibus_err_o <= 0;
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else if ((padv_i | fetch_take_exception_branch_i) & branch_occur_i |
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du_stall_i)
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decode_except_ibus_err_o <= 0;
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else if (fetch_req)
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decode_except_ibus_err_o <= ibus_err_i;
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// Register rising edge on bus_access_done
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always @(posedge clk `OR_ASYNC_RST)
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if (rst)
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bus_access_done_re_r <= 0;
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else
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bus_access_done_re_r <= bus_access_done & !bus_access_done_r;
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assign bus_access_done_fe = !bus_access_done & bus_access_done_r;
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/* If insn_buffer contains the next insn we need, save that information
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here */
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always @(posedge clk `OR_ASYNC_RST)
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if (rst)
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next_insn_buffered <= 0;
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else if (fetch_take_exception_branch_i)
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next_insn_buffered <= 0;
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else if (padv_i)
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// Next instruction is usually buffered when we've got bus ack and
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// pipeline advance, except when we're branching (usually throw
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// away the fetch when branch is being indicated)
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next_insn_buffered <= ibus_ack_i & !branch_occur_i;
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else if (ibus_ack_i & execute_waiting_i)
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next_insn_buffered <= 1;
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always @(posedge clk `OR_ASYNC_RST)
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if (rst)
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insn_buffer <= {`OR1K_OPCODE_NOP,26'd0};
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else if (ibus_ack_i & (!execute_waiting_i | !next_insn_buffered) &
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// Don't buffer instruction after delay slot instruction
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// (usually we're receiving it as taking branch is asserted)
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// it could be another jump instruction and having it in
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// the insn_buffer has annoying side-effects.
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!taking_branch)
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insn_buffer <= ibus_dat_i;
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always @(posedge clk `OR_ASYNC_RST)
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if (rst)
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wait_for_exception_after_ibus_err <= 0;
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else if (fetch_take_exception_branch_i)
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wait_for_exception_after_ibus_err <= 0;
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else if (ibus_err_i)
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wait_for_exception_after_ibus_err <= 1;
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endmodule // mor1kx_fetch_espresso
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