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alirezamon |
/* ****************************************************************************
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This Source Code Form is subject to the terms of the
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Open Hardware Description License, v. 1.0. If a copy
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of the OHDL was not distributed with this file, You
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can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
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Description: mor1kx pronto espresso fetch unit for TCM memories
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This is the fetch unit for the pipeline, so begins at the reset address and,
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in lock-step with the pipeline, provides the instructions according to the
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program flow.
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It is designed to interface to a single-cycle memory system (usually referred
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to as a tightly-coupled memory, or TCM - a ROM or a RAM). As such, it
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attempts to maximise throughput of the fetch stage to the pipeline.
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It responds to branch/exception indications from the control stage and
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delivers the appropriate instructions to the decode stage when the pipeline
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is ready to advance.
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It will go to "sleep" when it hits a jump-to-self instruction (0x00000000).
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Assumptions:
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Relies _heavily_ on being attached to a single-cycle memory.
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The ibus_adr_o requests byte-addresses, ibus_req_o is analogous to a
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read-enable signal, and the ibus_ack_i should be aligned with the read-data
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coming back.
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indicate ibus errors
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Copyright (C) 2013 Authors
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Author(s): Julius Baxter <juliusbaxter@gmail.com>
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***************************************************************************** */
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`include "mor1kx-defines.v"
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module mor1kx_fetch_tcm_prontoespresso
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(/*AUTOARG*/
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// Outputs
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ibus_adr_o, ibus_req_o, decode_insn_o, fetched_pc_o, fetch_ready_o,
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fetch_rfa_adr_o, fetch_rfb_adr_o, fetch_rf_re_o, pc_fetch_next_o,
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decode_except_ibus_err_o, fetch_sleep_o,
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// Inputs
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clk, rst, ibus_err_i, ibus_ack_i, ibus_dat_i, padv_i,
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branch_occur_i, branch_dest_i, du_restart_i, du_restart_pc_i,
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fetch_take_exception_branch_i, execute_waiting_i, du_stall_i,
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stepping_i, flag_i, flag_clear_i, flag_set_i
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);
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parameter OPTION_OPERAND_WIDTH = 32;
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parameter OPTION_RF_ADDR_WIDTH = 5;
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parameter OPTION_RESET_PC = {{(OPTION_OPERAND_WIDTH-13){1'b0}},
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`OR1K_RESET_VECTOR,8'd0};
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input clk, rst;
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// interface to ibus
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output [OPTION_OPERAND_WIDTH-1:0] ibus_adr_o;
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output ibus_req_o;
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input ibus_err_i;
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input ibus_ack_i;
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input [`OR1K_INSN_WIDTH-1:0] ibus_dat_i;
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// pipeline control input
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input padv_i;
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// interface to decode unit
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output reg [`OR1K_INSN_WIDTH-1:0] decode_insn_o;
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// PC of the current instruction, SPR_PPC basically
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output reg [OPTION_OPERAND_WIDTH-1:0] fetched_pc_o;
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// Indication to pipeline control that the fetch stage is ready
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output fetch_ready_o;
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// Signals going to register file to do the read access as we
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// register the instruction out to the decode stage
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output [OPTION_RF_ADDR_WIDTH-1:0] fetch_rfa_adr_o;
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output [OPTION_RF_ADDR_WIDTH-1:0] fetch_rfb_adr_o;
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output fetch_rf_re_o;
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// Signal back to the control which pc we're goint to
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// deliver next
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output [OPTION_OPERAND_WIDTH-1:0] pc_fetch_next_o;
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// branch/jump indication
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input branch_occur_i;
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input [OPTION_OPERAND_WIDTH-1:0] branch_dest_i;
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// restart signals from debug unit
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input du_restart_i;
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input [OPTION_OPERAND_WIDTH-1:0] du_restart_pc_i;
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input fetch_take_exception_branch_i;
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input execute_waiting_i;
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// CPU is stalled
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input du_stall_i;
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// We're single stepping - this should cause us to fetch only a single insn
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input stepping_i;
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// Flag status information
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input flag_i, flag_clear_i, flag_set_i;
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// instruction ibus error indication out
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output reg decode_except_ibus_err_o;
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// fetch sleep mode enabled (due to jump-to-self instruction
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output fetch_sleep_o;
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reg [OPTION_OPERAND_WIDTH-1:0] current_bus_pc;
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wire [OPTION_OPERAND_WIDTH-1:0] next_bus_pc;
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reg [OPTION_OPERAND_WIDTH-1:0] insn_buffer;
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wire first_bus_req_cycle;
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reg addr_pipelined;
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reg bus_req, bus_req_r;
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wire [`OR1K_OPCODE_WIDTH-1:0] next_insn_opcode;
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reg next_insn_will_branch;
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reg jump_insn_in_decode;
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reg just_took_branch_addr;
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wire taking_branch_addr;
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reg insn_from_branch_on_input;
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reg insn_from_branch_in_pipeline;
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reg execute_waiting_r;
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wire execute_waiting_deasserted;
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wire execute_waiting_asserted;
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reg execute_waiting_asserted_r;
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wire execute_waited_single_cycle;
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reg just_waited_single_cycle;
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reg just_waited_single_cycle_r;
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reg insn_buffered;
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wire buffered_insn_is_jump;
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reg push_buffered_jump_through_pipeline;
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wire will_go_to_sleep;
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reg sleep;
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reg fetch_take_exception_branch_r;
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reg [3:0] padv_r;
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wire long_stall;
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assign next_bus_pc = current_bus_pc + 4;
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assign ibus_adr_o = addr_pipelined ? next_bus_pc : current_bus_pc;
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assign pc_fetch_next_o = ibus_adr_o;
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assign ibus_req_o = bus_req & !(stepping_i & ibus_ack_i) |
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(execute_waiting_deasserted &
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!(insn_buffered & next_insn_will_branch)) |
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fetch_take_exception_branch_r;
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// Signal rising edge on bus request signal
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assign first_bus_req_cycle = ibus_req_o & !bus_req_r;
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assign taking_branch_addr = (branch_occur_i & padv_i) |
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fetch_take_exception_branch_i;
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assign buffered_insn_is_jump = insn_buffered & next_insn_will_branch;
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always @(posedge clk `OR_ASYNC_RST)
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if (rst)
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begin
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current_bus_pc <= OPTION_RESET_PC;
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just_took_branch_addr <= 0;
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end
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else if (du_restart_i)
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begin
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current_bus_pc <= du_restart_pc_i;
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just_took_branch_addr <= 0;
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end
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else if (fetch_take_exception_branch_i)
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begin
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current_bus_pc <= branch_dest_i;
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just_took_branch_addr <= 1;
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end
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else if (branch_occur_i & padv_i)
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begin
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current_bus_pc <= branch_dest_i;
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just_took_branch_addr <= 1;
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end
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else if (ibus_ack_i & (padv_i | (just_waited_single_cycle_r &&
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!({padv_r[0],padv_i}==2'b00))) &
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!execute_waited_single_cycle & !stepping_i)
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begin
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current_bus_pc <= next_bus_pc;
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just_took_branch_addr <= 0;
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end
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else if (execute_waiting_asserted & ibus_ack_i & !just_took_branch_addr)
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begin
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current_bus_pc <= next_bus_pc;
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end
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else if (just_took_branch_addr)
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begin
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just_took_branch_addr <= 0;
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end
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else if (long_stall)
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begin
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// Long wait - this is a work around for an annoying bug which
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// I can't solve any other way!
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current_bus_pc <= fetched_pc_o + 4;
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end
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// BIG assumptions here - that the read only takes a single cycle!!
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always @(posedge clk `OR_ASYNC_RST)
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if (rst)
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begin
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insn_from_branch_on_input <= 0;
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insn_from_branch_in_pipeline <= 0;
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end
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else
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begin
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insn_from_branch_on_input <= just_took_branch_addr;
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insn_from_branch_in_pipeline <= insn_from_branch_on_input;
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end
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always @(posedge clk `OR_ASYNC_RST)
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if (rst)
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bus_req <= 1'b0;
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else if (stepping_i & ibus_ack_i)
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// Deassert on ack of stepping
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bus_req <= 1'b0;
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else if (du_stall_i)
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bus_req <= 1'b0;
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else if (ibus_err_i | decode_except_ibus_err_o)
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bus_req <= 1'b0;
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else if (sleep)
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bus_req <= 1'b0;
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else if (execute_waiting_i)
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bus_req <= 1'b0;
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else if (buffered_insn_is_jump)
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bus_req <= 1'b0;
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else
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bus_req <= 1'b1;
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always @(posedge clk `OR_ASYNC_RST)
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if (rst)
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bus_req_r <= 0;
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else
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bus_req_r <= ibus_req_o;
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always @(posedge clk `OR_ASYNC_RST)
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if (rst)
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addr_pipelined <= 0;
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else if (ibus_err_i | decode_except_ibus_err_o |
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fetch_take_exception_branch_i)
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addr_pipelined <= 0;
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else if (first_bus_req_cycle)
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addr_pipelined <= 1;
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else if (taking_branch_addr)
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addr_pipelined <= 0;
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else if (just_took_branch_addr)
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addr_pipelined <= 1;
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else if (just_waited_single_cycle)
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addr_pipelined <= 1;
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else if (!bus_req)
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addr_pipelined <= 0;
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always @(posedge clk `OR_ASYNC_RST)
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if (rst)
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begin
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decode_insn_o <= {`OR1K_OPCODE_NOP,26'd0};
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fetched_pc_o <= 0;
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end
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else if (sleep | (du_stall_i & !execute_waiting_i))
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begin
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decode_insn_o <= {`OR1K_OPCODE_NOP,26'd0};
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end
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else if (fetch_take_exception_branch_i & !du_stall_i)
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begin
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decode_insn_o <= {`OR1K_OPCODE_NOP,26'd0};
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end
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else if ((padv_i | stepping_i) & ibus_ack_i & (ibus_req_o | stepping_i) &
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((!jump_insn_in_decode & !just_took_branch_addr) |
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(insn_from_branch_on_input))
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& !(execute_waited_single_cycle | just_waited_single_cycle))
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begin
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decode_insn_o <= ibus_dat_i;
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fetched_pc_o <= current_bus_pc;
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end
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else if (just_waited_single_cycle_r & !execute_waiting_i)
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begin
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decode_insn_o <= ibus_dat_i;
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fetched_pc_o <= current_bus_pc;
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end
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else if (execute_waiting_deasserted & insn_buffered)
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begin
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decode_insn_o <= insn_buffer;
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fetched_pc_o <= fetched_pc_o + 4;
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end
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else if ((jump_insn_in_decode | branch_occur_i) & padv_i)
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// About to jump - remove this instruction from the pipeline
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decode_insn_o <= {`OR1K_OPCODE_NOP,26'd0};
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else if (fetch_take_exception_branch_i)
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decode_insn_o <= {`OR1K_OPCODE_NOP,26'd0};
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else if (push_buffered_jump_through_pipeline)
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decode_insn_o <= {`OR1K_OPCODE_NOP,26'd0};
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reg fetch_ready_r;
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always @(posedge clk `OR_ASYNC_RST)
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if (rst)
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fetch_ready_r <= 0;
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else
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fetch_ready_r <= fetch_ready_o;
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assign fetch_ready_o = (ibus_ack_i | insn_buffered ) &
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!(just_took_branch_addr) &
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!(just_waited_single_cycle) &
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!du_stall_i |
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push_buffered_jump_through_pipeline ;
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always @(posedge clk `OR_ASYNC_RST)
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if (rst)
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decode_except_ibus_err_o <= 0;
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else if ((padv_i | fetch_take_exception_branch_i) &
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branch_occur_i | du_stall_i)
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decode_except_ibus_err_o <= 0;
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else if (bus_req)
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decode_except_ibus_err_o <= ibus_err_i;
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assign fetch_sleep_o = sleep;
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always @(posedge clk `OR_ASYNC_RST)
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if (rst)
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execute_waiting_r <= 0;
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else
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execute_waiting_r <= execute_waiting_i;
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assign execute_waiting_deasserted = !execute_waiting_i & execute_waiting_r;
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assign execute_waiting_asserted = execute_waiting_i & !execute_waiting_r;
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339 |
|
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|
340 |
|
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|
341 |
|
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// Register file control
|
342 |
|
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assign fetch_rfa_adr_o = insn_buffered ? insn_buffer[`OR1K_RA_SELECT] :
|
343 |
|
|
ibus_dat_i[`OR1K_RA_SELECT];
|
344 |
|
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assign fetch_rfb_adr_o = insn_buffered ? insn_buffer[`OR1K_RB_SELECT] :
|
345 |
|
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ibus_dat_i[`OR1K_RB_SELECT];
|
346 |
|
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assign fetch_rf_re_o = (ibus_ack_i | execute_waiting_deasserted) &
|
347 |
|
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(padv_i | stepping_i);
|
348 |
|
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|
349 |
|
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// Pick out opcode of next instruction to go to decode stage
|
350 |
|
|
assign next_insn_opcode = insn_buffered ?
|
351 |
|
|
insn_buffer[`OR1K_OPCODE_SELECT] :
|
352 |
|
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ibus_dat_i[`OR1K_OPCODE_SELECT];
|
353 |
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|
354 |
|
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always @*
|
355 |
|
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if ((ibus_ack_i & !just_took_branch_addr) | insn_buffered)
|
356 |
|
|
case (next_insn_opcode)
|
357 |
|
|
`OR1K_OPCODE_J,
|
358 |
|
|
`OR1K_OPCODE_JAL: begin
|
359 |
|
|
next_insn_will_branch = 1;
|
360 |
|
|
end
|
361 |
|
|
`OR1K_OPCODE_JR,
|
362 |
|
|
`OR1K_OPCODE_JALR: begin
|
363 |
|
|
next_insn_will_branch = 1;
|
364 |
|
|
end
|
365 |
|
|
`OR1K_OPCODE_BNF: begin
|
366 |
|
|
next_insn_will_branch = !(flag_i | flag_set_i) | flag_clear_i;
|
367 |
|
|
end
|
368 |
|
|
`OR1K_OPCODE_BF: begin
|
369 |
|
|
next_insn_will_branch = !(!flag_i | flag_clear_i) |flag_set_i;
|
370 |
|
|
end
|
371 |
|
|
`OR1K_OPCODE_SYSTRAPSYNC,
|
372 |
|
|
`OR1K_OPCODE_RFE: begin
|
373 |
|
|
next_insn_will_branch = 1;
|
374 |
|
|
end
|
375 |
|
|
default: begin
|
376 |
|
|
next_insn_will_branch = 0;
|
377 |
|
|
end
|
378 |
|
|
endcase // case (next_insn_opcode)
|
379 |
|
|
else
|
380 |
|
|
begin
|
381 |
|
|
next_insn_will_branch = 0;
|
382 |
|
|
end
|
383 |
|
|
|
384 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
385 |
|
|
if (rst)
|
386 |
|
|
jump_insn_in_decode <= 0;
|
387 |
|
|
else if (sleep)
|
388 |
|
|
jump_insn_in_decode <= 0;
|
389 |
|
|
else if (!jump_insn_in_decode & next_insn_will_branch & ibus_ack_i)
|
390 |
|
|
jump_insn_in_decode <= 1;
|
391 |
|
|
else
|
392 |
|
|
jump_insn_in_decode <= 0;
|
393 |
|
|
|
394 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
395 |
|
|
if (rst)
|
396 |
|
|
insn_buffer <= 0;
|
397 |
|
|
else if (execute_waiting_asserted & ibus_ack_i & !just_took_branch_addr)
|
398 |
|
|
insn_buffer <= ibus_dat_i;
|
399 |
|
|
|
400 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
401 |
|
|
if (rst)
|
402 |
|
|
insn_buffered <= 0;
|
403 |
|
|
else if (execute_waiting_asserted & ibus_ack_i & !just_took_branch_addr)
|
404 |
|
|
insn_buffered <= 1;
|
405 |
|
|
else if (execute_waiting_deasserted)
|
406 |
|
|
insn_buffered <= 0;
|
407 |
|
|
else if (fetch_take_exception_branch_i)
|
408 |
|
|
insn_buffered <= 0;
|
409 |
|
|
else if (long_stall)
|
410 |
|
|
insn_buffered <= 0;
|
411 |
|
|
|
412 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
413 |
|
|
if (rst)
|
414 |
|
|
push_buffered_jump_through_pipeline <= 0;
|
415 |
|
|
else
|
416 |
|
|
push_buffered_jump_through_pipeline <= buffered_insn_is_jump &
|
417 |
|
|
execute_waiting_deasserted;
|
418 |
|
|
|
419 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
420 |
|
|
if (rst)
|
421 |
|
|
fetch_take_exception_branch_r <= 0;
|
422 |
|
|
else
|
423 |
|
|
fetch_take_exception_branch_r <= fetch_take_exception_branch_i;
|
424 |
|
|
|
425 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
426 |
|
|
if (rst)
|
427 |
|
|
sleep <= 1'b0;
|
428 |
|
|
else if (fetch_take_exception_branch_i)
|
429 |
|
|
sleep <= 1'b0;
|
430 |
|
|
else if (will_go_to_sleep)
|
431 |
|
|
sleep <= 1'b1;
|
432 |
|
|
|
433 |
|
|
assign will_go_to_sleep = ibus_dat_i==0 & padv_i & ibus_ack_i &
|
434 |
|
|
ibus_req_o & ((!jump_insn_in_decode &
|
435 |
|
|
!just_took_branch_addr) |
|
436 |
|
|
(insn_from_branch_on_input));
|
437 |
|
|
|
438 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
439 |
|
|
if (rst)
|
440 |
|
|
execute_waiting_asserted_r <= 0;
|
441 |
|
|
else
|
442 |
|
|
execute_waiting_asserted_r <= execute_waiting_asserted;
|
443 |
|
|
|
444 |
|
|
assign execute_waited_single_cycle = execute_waiting_asserted_r &
|
445 |
|
|
!execute_waiting_i;
|
446 |
|
|
|
447 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
448 |
|
|
if (rst)
|
449 |
|
|
begin
|
450 |
|
|
just_waited_single_cycle <= 0;
|
451 |
|
|
just_waited_single_cycle_r <= 0;
|
452 |
|
|
end
|
453 |
|
|
else
|
454 |
|
|
begin
|
455 |
|
|
just_waited_single_cycle <= execute_waited_single_cycle;
|
456 |
|
|
just_waited_single_cycle_r <= just_waited_single_cycle;
|
457 |
|
|
end
|
458 |
|
|
|
459 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
460 |
|
|
if (rst)
|
461 |
|
|
padv_r <= 4'd0;
|
462 |
|
|
else
|
463 |
|
|
padv_r <= {padv_r[2:0],padv_i};
|
464 |
|
|
|
465 |
|
|
assign long_stall = {padv_r,padv_i}==5'b10000 && execute_waiting_i;
|
466 |
|
|
|
467 |
|
|
endmodule // mor1kx_fetch_tcm_prontoespresso
|