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alirezamon |
/* ****************************************************************************
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This Source Code Form is subject to the terms of the
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Open Hardware Description License, v. 1.0. If a copy
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of the OHDL was not distributed with this file, You
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can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
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Description: mor1kx SPRs indicating configuration and version
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All registers are read only and configured at synthesis time.
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Note that the outputs do not have the usual "_o" prefix on the port names
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as this module is intended to be instantiated without a Verilog-mode
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AUTO_TEMPLATE, and as the module is providing read-only signals, there's
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no confusion about the direction of the ports.
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Copyright (C) 2012 Authors
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Author(s): Julius Baxter <juliusbaxter@gmail.com>
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***************************************************************************** */
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`include "mor1kx-defines.v"
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module mor1kx_cfgrs
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#(
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parameter FEATURE_SYSCALL = "ENABLED",
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parameter FEATURE_TRAP = "ENABLED",
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parameter FEATURE_RANGE = "ENABLED",
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parameter FEATURE_DATACACHE = "NONE",
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parameter OPTION_DCACHE_BLOCK_WIDTH = 5,
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parameter OPTION_DCACHE_SET_WIDTH = 9,
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parameter OPTION_DCACHE_WAYS = 2,
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parameter FEATURE_DMMU = "NONE",
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parameter [2:0] OPTION_DMMU_SET_WIDTH = 6,
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parameter OPTION_DMMU_WAYS = 1,
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parameter FEATURE_INSTRUCTIONCACHE = "NONE",
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parameter OPTION_ICACHE_BLOCK_WIDTH = 5,
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parameter OPTION_ICACHE_SET_WIDTH = 9,
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parameter OPTION_ICACHE_WAYS = 2,
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parameter FEATURE_IMMU = "NONE",
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parameter OPTION_IMMU_SET_WIDTH = 6,
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parameter OPTION_IMMU_WAYS = 1,
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parameter FEATURE_PIC = "ENABLED",
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parameter FEATURE_TIMER = "ENABLED",
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parameter FEATURE_DEBUGUNIT = "NONE",
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parameter FEATURE_PERFCOUNTERS = "NONE",
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parameter OPTION_PERFCOUNTERS_NUM = 0,
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parameter FEATURE_PMU = "NONE",
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parameter FEATURE_MAC = "NONE",
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parameter FEATURE_FPU = "NONE",
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parameter OPTION_PIC_TRIGGER = "LEVEL",
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parameter FEATURE_DSX = "NONE",
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parameter FEATURE_FASTCONTEXTS = "NONE",
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parameter OPTION_RF_NUM_SHADOW_GPR = 0,
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parameter FEATURE_OVERFLOW = "NONE",
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parameter FEATURE_DELAYSLOT = "NONE",
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parameter FEATURE_EVBAR = "NONE",
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parameter FEATURE_AECSR = "NONE"
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)
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(
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output [31:0] spr_vr,
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output [31:0] spr_vr2,
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output [31:0] spr_upr,
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output [31:0] spr_cpucfgr,
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output [31:0] spr_dmmucfgr,
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output [31:0] spr_immucfgr,
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output [31:0] spr_dccfgr,
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output [31:0] spr_iccfgr,
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output [31:0] spr_dcfgr,
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output [31:0] spr_pccfgr,
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output [31:0] spr_avr
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);
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assign spr_vr[`OR1K_SPR_VR_REV] = 0;
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assign spr_vr[`OR1K_SPR_VR_UVRP] = 1;
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assign spr_vr[`OR1K_SPR_VR_RESERVED] = 0;
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assign spr_vr[`OR1K_SPR_VR_CFG] = 0;
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assign spr_vr[`OR1K_SPR_VR_VER] = 8'h10;
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assign spr_upr[`OR1K_SPR_UPR_UP] = 1;
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assign spr_upr[`OR1K_SPR_UPR_DCP] = (FEATURE_DATACACHE!="NONE");
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assign spr_upr[`OR1K_SPR_UPR_ICP] = (FEATURE_INSTRUCTIONCACHE!="NONE");
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assign spr_upr[`OR1K_SPR_UPR_DMP] = (FEATURE_DMMU!="NONE");
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assign spr_upr[`OR1K_SPR_UPR_IMP] = (FEATURE_IMMU!="NONE");
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assign spr_upr[`OR1K_SPR_UPR_MP] = (FEATURE_MAC!="NONE");
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assign spr_upr[`OR1K_SPR_UPR_DUP] = (FEATURE_DEBUGUNIT!="NONE");
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assign spr_upr[`OR1K_SPR_UPR_PCUP] = (FEATURE_PERFCOUNTERS!="NONE");
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assign spr_upr[`OR1K_SPR_UPR_PICP] = (FEATURE_PIC!="NONE");
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assign spr_upr[`OR1K_SPR_UPR_PMP] = (FEATURE_PMU!="NONE");
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assign spr_upr[`OR1K_SPR_UPR_TTP] = (FEATURE_TIMER!="NONE");
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assign spr_upr[`OR1K_SPR_UPR_RESERVED] = 0;
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assign spr_upr[`OR1K_SPR_UPR_CUP] = 0;
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assign spr_cpucfgr[`OR1K_SPR_CPUCFGR_NSGF] = OPTION_RF_NUM_SHADOW_GPR;
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assign spr_cpucfgr[`OR1K_SPR_CPUCFGR_CFG] = 0;
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assign spr_cpucfgr[`OR1K_SPR_CPUCFGR_OB32S] = 1;
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assign spr_cpucfgr[`OR1K_SPR_CPUCFGR_OB64S] = 0;
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assign spr_cpucfgr[`OR1K_SPR_CPUCFGR_OF32S] = (FEATURE_FPU!="NONE");
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assign spr_cpucfgr[`OR1K_SPR_CPUCFGR_OF64S] = 0;
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assign spr_cpucfgr[`OR1K_SPR_CPUCFGR_OV64S] = 0;
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assign spr_cpucfgr[`OR1K_SPR_CPUCFGR_ND] = (FEATURE_DELAYSLOT=="NONE");
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/* AVR will always be present in mor1kx */
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assign spr_cpucfgr[`OR1K_SPR_CPUCFGR_AVRP] = 1;
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assign spr_cpucfgr[`OR1K_SPR_CPUCFGR_EVBARP] = (FEATURE_EVBAR!="NONE");
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/* ISRs will always be present */
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assign spr_cpucfgr[`OR1K_SPR_CPUCFGR_ISRP] = 1;
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assign spr_cpucfgr[`OR1K_SPR_CPUCFGR_AECSRP] = (FEATURE_AECSR!="NONE");
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assign spr_cpucfgr[`OR1K_SPR_CPUCFGR_RESERVED] = 0;
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/* Version register 2 */
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/* Implementation ID as per:
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http://opencores.org/or1k/OR1K_CPU_Cores#CPU_ID_Table
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mor1kx breaks up the VR2[23:0] to be 3 8-bit fields
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23:16 - Major version number
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15:8 - Minor version number
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7:0 - Pipeline implementation identifier (set outside of this module)
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*/
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assign spr_vr2[`OR1K_SPR_VR2_CPUID] = `MOR1KX_CPUID;
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assign spr_vr2[`OR1K_SPR_VR2_VER] = {`MOR1KX_VERSION_MAJOR,
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`MOR1KX_VERSION_MINOR,
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8'd0};
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/* Currently supporting OR1K version 1.1 rev0 */
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assign spr_avr[`OR1K_SPR_AVR_MAJ] = 8'd1;
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assign spr_avr[`OR1K_SPR_AVR_MIN] = 8'd1;
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assign spr_avr[`OR1K_SPR_AVR_REV] = 8'd0;
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assign spr_avr[`OR1K_SPR_AVR_RESERVED] = 0;
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/* Data MMU Configuration Register */
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/* Reserved */
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assign spr_dmmucfgr[31:12] = 0;
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/* Hardware TLB Reload */
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assign spr_dmmucfgr[`OR1K_SPR_DMMUFGR_HTR] = 0;
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/* TLB Entry Invalidate Register Implemented */
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assign spr_dmmucfgr[`OR1K_SPR_DMMUFGR_TEIRI] = 0;
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/* Protection Register Implemented */
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assign spr_dmmucfgr[`OR1K_SPR_DMMUFGR_PRI] = 0;
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/* Control Register Implemented */
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assign spr_dmmucfgr[`OR1K_SPR_DMMUFGR_CRI] = 0;
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/* Number of ATB entries */
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assign spr_dmmucfgr[`OR1K_SPR_DMMUFGR_NAE] = 0;
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/* Number of TLB sets */
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assign spr_dmmucfgr[`OR1K_SPR_DMMUFGR_NTS] = (FEATURE_DMMU!="NONE") ?
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OPTION_DMMU_SET_WIDTH : 0;
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/* Number of TLB ways */
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assign spr_dmmucfgr[`OR1K_SPR_DMMUFGR_NTW] = (FEATURE_DMMU!="NONE") ?
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OPTION_DMMU_WAYS-1 : 0;
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/* Instruction MMU Configuration Register */
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/* Reserved */
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assign spr_immucfgr[31:12] = 0;
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/* Hardware TLB Reload */
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assign spr_immucfgr[`OR1K_SPR_IMMUFGR_HTR] = 0;
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/* TLB Entry Invalidate Register Implemented */
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assign spr_immucfgr[`OR1K_SPR_IMMUFGR_TEIRI] = 0;
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/* Protection Register Implemented */
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assign spr_immucfgr[`OR1K_SPR_IMMUFGR_PRI] = 0;
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/* Control Register Implemented */
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assign spr_immucfgr[`OR1K_SPR_IMMUFGR_CRI] = 0;
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/* Number of ATB entries */
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assign spr_immucfgr[`OR1K_SPR_IMMUFGR_NAE] = 0;
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/* Number of TLB sets */
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assign spr_immucfgr[`OR1K_SPR_IMMUFGR_NTS] = (FEATURE_IMMU!="NONE") ?
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OPTION_IMMU_SET_WIDTH : 0;
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/* Number of TLB ways */
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assign spr_immucfgr[`OR1K_SPR_IMMUFGR_NTW] = (FEATURE_IMMU!="NONE") ?
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OPTION_IMMU_WAYS-1 : 0;
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/* Data Cache Configuration register */
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/* Reserved */
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assign spr_dccfgr[31:15] = 0;
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/* Cache Block Write-Back Register Implemented */
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assign spr_dccfgr[`OR1K_SPR_DCCFGR_CBWBRI] = 0;
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/* Cache Block Flush Register Implemented */
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assign spr_dccfgr[`OR1K_SPR_DCCFGR_CBFRI] = (FEATURE_DATACACHE!="NONE");
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/* Cache Block Lock Register Implemented */
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assign spr_dccfgr[`OR1K_SPR_DCCFGR_CBLRI] = 0;
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/* Cache Block Prefetch Register Implemented */
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assign spr_dccfgr[`OR1K_SPR_DCCFGR_CBPRI] = 0;
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/* Cache Block Invalidate Register Implemented */
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assign spr_dccfgr[`OR1K_SPR_DCCFGR_CBIRI] = (FEATURE_DATACACHE!="NONE");
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/* Cache Control Register Implemented */
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assign spr_dccfgr[`OR1K_SPR_DCCFGR_CCRI] = 0;
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/* Cache Write Strategy (0 = write-through, 1 = write-back) */
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assign spr_dccfgr[`OR1K_SPR_DCCFGR_CWS] = 0;
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/* Cache Block Size (0 = 16 bytes, 1 = 32 bytes) */
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assign spr_dccfgr[`OR1K_SPR_DCCFGR_CBS] = (FEATURE_DATACACHE!="NONE") ?
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(OPTION_DCACHE_BLOCK_WIDTH == 5 ?
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1 : 0) : 0;
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/* Number of Cache Sets */
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assign spr_dccfgr[`OR1K_SPR_DCCFGR_NCS] = (FEATURE_DATACACHE!="NONE") ?
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OPTION_DCACHE_SET_WIDTH : 0;
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/* Number of Cache Ways */
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assign spr_dccfgr[`OR1K_SPR_DCCFGR_NCW] = (FEATURE_DATACACHE!="NONE") ?
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(OPTION_DCACHE_WAYS == 1) ? 3'd0 :
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(OPTION_DCACHE_WAYS == 2) ? 3'd1 :
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(OPTION_DCACHE_WAYS == 4) ? 3'd2 :
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(OPTION_DCACHE_WAYS == 8) ? 3'd3 :
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(OPTION_DCACHE_WAYS == 16) ? 3'd4 :
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(OPTION_DCACHE_WAYS == 32) ? 3'd5 :
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3'd0 : 3'd0;
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/* Instruction Cache Configuration register */
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/* Reserved */
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assign spr_iccfgr[31:13] = 0;
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assign spr_iccfgr[8] = 0;
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/* Cache Block Lock Register Implemented */
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assign spr_iccfgr[`OR1K_SPR_ICCFGR_CBLRI] = 0;
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/* Cache Block Prefetch Register Implemented */
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assign spr_iccfgr[`OR1K_SPR_ICCFGR_CBPRI] = 0;
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/* Cache Block Invalidate Register Implemented */
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assign spr_iccfgr[`OR1K_SPR_ICCFGR_CBIRI] = (FEATURE_INSTRUCTIONCACHE!="NONE");
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/* Cache Control Register Implemented */
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assign spr_iccfgr[`OR1K_SPR_ICCFGR_CCRI] = 0;
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/* Cache Block Size (0 = 16 bytes, 1 = 32 bytes) */
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assign spr_iccfgr[`OR1K_SPR_ICCFGR_CBS] = (FEATURE_INSTRUCTIONCACHE!="NONE") ?
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(OPTION_ICACHE_BLOCK_WIDTH == 5 ?
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1 : 0) : 0;
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/* Number of Cache Sets */
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assign spr_iccfgr[`OR1K_SPR_ICCFGR_NCS] = (FEATURE_INSTRUCTIONCACHE!="NONE") ?
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OPTION_ICACHE_SET_WIDTH : 0;
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/* Number of Cache Ways */
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assign spr_iccfgr[`OR1K_SPR_ICCFGR_NCW] = (FEATURE_INSTRUCTIONCACHE!="NONE") ?
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(OPTION_ICACHE_WAYS == 1) ? 3'd0 :
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(OPTION_ICACHE_WAYS == 2) ? 3'd1 :
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(OPTION_ICACHE_WAYS == 4) ? 3'd2 :
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(OPTION_ICACHE_WAYS == 8) ? 3'd3 :
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(OPTION_ICACHE_WAYS == 16) ? 3'd4 :
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(OPTION_ICACHE_WAYS == 32) ? 3'd5 :
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3'd0 : 3'd0;
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assign spr_dcfgr = 0;
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assign spr_pccfgr = (FEATURE_PERFCOUNTERS!="NONE") ? OPTION_PERFCOUNTERS_NUM : 0;
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endmodule // mor1kx_cfgrs
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