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alirezamon |
/* ****************************************************************************
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This Source Code Form is subject to the terms of the
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Open Hardware Description License, v. 1.0. If a copy
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of the OHDL was not distributed with this file, You
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can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
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Description: mor1kx espresso pipeline control unit
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inputs from execute stage
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generate pipeline controls
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manage SPRs
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issue addresses for exceptions to fetch stage
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control branches going to fetch stage
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contains tick timer
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contains PIC logic
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Copyright (C) 2012 Authors
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Author(s): Julius Baxter <juliusbaxter@gmail.com>
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***************************************************************************** */
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`include "mor1kx-defines.v"
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module mor1kx_ctrl_espresso
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(/*AUTOARG*/
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// Outputs
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flag_o, spr_npc_o, spr_ppc_o, mfspr_dat_o, ctrl_mfspr_we_o,
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carry_o, pipeline_flush_o, padv_fetch_o, padv_decode_o,
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padv_execute_o, fetch_take_exception_branch_o, exception_taken_o,
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execute_waiting_o, stepping_o, du_dat_o, du_ack_o, du_stall_o,
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du_restart_pc_o, du_restart_o, spr_bus_addr_o, spr_bus_we_o,
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spr_bus_stb_o, spr_bus_dat_o, spr_sr_o, ctrl_branch_target_o,
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ctrl_branch_occur_o, rf_we_o,
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// Inputs
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clk, rst, ctrl_alu_result_i, ctrl_rfb_i, ctrl_flag_set_i,
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ctrl_flag_clear_i, ctrl_opc_insn_i, pc_fetch_i, fetch_advancing_i,
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except_ibus_err_i, except_illegal_i, except_syscall_i,
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except_dbus_i, except_trap_i, except_align_i, next_fetch_done_i,
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alu_valid_i, lsu_valid_i, op_lsu_load_i, op_lsu_store_i, op_jr_i,
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op_jbr_i, irq_i, carry_set_i, carry_clear_i, overflow_set_i,
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overflow_clear_i, du_addr_i, du_stb_i, du_dat_i, du_we_i,
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du_stall_i, spr_bus_dat_dc_i, spr_bus_ack_dc_i, spr_bus_dat_ic_i,
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spr_bus_ack_ic_i, spr_bus_dat_dmmu_i, spr_bus_ack_dmmu_i,
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spr_bus_dat_immu_i, spr_bus_ack_immu_i, spr_bus_dat_mac_i,
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spr_bus_ack_mac_i, spr_bus_dat_pmu_i, spr_bus_ack_pmu_i,
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spr_bus_dat_pcu_i, spr_bus_ack_pcu_i, spr_bus_dat_fpu_i,
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spr_bus_ack_fpu_i, multicore_coreid_i, rf_wb_i
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);
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parameter OPTION_OPERAND_WIDTH = 32;
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parameter OPTION_RESET_PC = {{(OPTION_OPERAND_WIDTH-13){1'b0}},
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`OR1K_RESET_VECTOR,8'd0};
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parameter FEATURE_SYSCALL = "ENABLED";
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parameter FEATURE_TRAP = "ENABLED";
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parameter FEATURE_RANGE = "ENABLED";
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parameter FEATURE_DATACACHE = "NONE";
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parameter OPTION_DCACHE_BLOCK_WIDTH = 5;
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parameter OPTION_DCACHE_SET_WIDTH = 9;
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parameter OPTION_DCACHE_WAYS = 2;
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parameter FEATURE_DMMU = "NONE";
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parameter FEATURE_INSTRUCTIONCACHE = "NONE";
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parameter OPTION_ICACHE_BLOCK_WIDTH = 5;
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parameter OPTION_ICACHE_SET_WIDTH = 9;
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parameter OPTION_ICACHE_WAYS = 2;
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parameter FEATURE_IMMU = "NONE";
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parameter FEATURE_TIMER = "ENABLED";
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parameter FEATURE_DEBUGUNIT = "NONE";
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parameter FEATURE_PERFCOUNTERS = "NONE";
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parameter FEATURE_PMU = "NONE";
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parameter FEATURE_MAC = "NONE";
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parameter FEATURE_FPU = "NONE";
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parameter FEATURE_MULTICORE = "NONE";
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parameter FEATURE_PIC = "ENABLED";
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parameter OPTION_PIC_TRIGGER = "LEVEL";
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parameter OPTION_PIC_NMI_WIDTH = 0;
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parameter FEATURE_DSX = "NONE";
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parameter FEATURE_FASTCONTEXTS = "NONE";
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parameter FEATURE_OVERFLOW = "NONE";
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parameter SPR_SR_WIDTH = 16;
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parameter SPR_SR_RESET_VALUE = 16'h8001;
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input clk, rst;
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// ALU result - either jump target, SPR address
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input [OPTION_OPERAND_WIDTH-1:0] ctrl_alu_result_i;
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// Operand B from RF might be jump address, might be value for SPR
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input [OPTION_OPERAND_WIDTH-1:0] ctrl_rfb_i;
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input ctrl_flag_set_i, ctrl_flag_clear_i;
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output flag_o;
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output [OPTION_OPERAND_WIDTH-1:0] spr_npc_o;
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output [OPTION_OPERAND_WIDTH-1:0] spr_ppc_o;
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input [`OR1K_OPCODE_WIDTH-1:0] ctrl_opc_insn_i;
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// PC of execute stage (NPC)
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input [OPTION_OPERAND_WIDTH-1:0] pc_fetch_i;
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input fetch_advancing_i;
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// Exception inputs, registered on output of execute stage
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input except_ibus_err_i,
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except_illegal_i,
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except_syscall_i, except_dbus_i,
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except_trap_i, except_align_i;
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// Inputs from two units that can stall proceedings
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input next_fetch_done_i;
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input alu_valid_i, lsu_valid_i;
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input op_lsu_load_i, op_lsu_store_i;
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input op_jr_i, op_jbr_i;
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// External IRQ lines in
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input [31:0] irq_i;
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// SPR data out
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output [OPTION_OPERAND_WIDTH-1:0] mfspr_dat_o;
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// WE to RF for l.mfspr
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output ctrl_mfspr_we_o;
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// Flag out to branch control, combinatorial
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reg flag;
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// Arithmetic flags to and from ALU
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output carry_o;
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input carry_set_i;
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input carry_clear_i;
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input overflow_set_i;
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input overflow_clear_i;
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// Branch indicator from control unit (l.rfe/exception)
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wire ctrl_branch_exception;
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// PC out to fetch stage for l.rfe, exceptions
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wire [OPTION_OPERAND_WIDTH-1:0] ctrl_branch_except_pc;
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// Clear instructions from decode and fetch stage
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output pipeline_flush_o;
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output padv_fetch_o;
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output padv_decode_o;
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output padv_execute_o;
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// This indicates to the fetch unit only that it should basically interrupt
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// whatever it's doing and start fetching the exception
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output fetch_take_exception_branch_o;
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// This indicates to other parts of the CPU that we've handled an excption
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// so can be used to clear exception indication registers
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output exception_taken_o;
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output execute_waiting_o;
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output stepping_o;
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// Debug bus
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input [15:0] du_addr_i;
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input du_stb_i;
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input [OPTION_OPERAND_WIDTH-1:0] du_dat_i;
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input du_we_i;
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output [OPTION_OPERAND_WIDTH-1:0] du_dat_o;
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output du_ack_o;
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// Stall control from debug interface
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input du_stall_i;
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output du_stall_o;
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output [OPTION_OPERAND_WIDTH-1:0] du_restart_pc_o;
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output du_restart_o;
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// SPR accesses to external units (cache, mmu, etc.)
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output [15:0] spr_bus_addr_o;
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output spr_bus_we_o;
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output spr_bus_stb_o;
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output [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_o;
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input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_dc_i;
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input spr_bus_ack_dc_i;
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input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_ic_i;
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input spr_bus_ack_ic_i;
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input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_dmmu_i;
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input spr_bus_ack_dmmu_i;
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input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_immu_i;
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input spr_bus_ack_immu_i;
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input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_mac_i;
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input spr_bus_ack_mac_i;
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input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_pmu_i;
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input spr_bus_ack_pmu_i;
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input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_pcu_i;
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input spr_bus_ack_pcu_i;
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input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_fpu_i;
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input spr_bus_ack_fpu_i;
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output [15:0] spr_sr_o;
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// The multicore core identifier
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input [OPTION_OPERAND_WIDTH-1:0] multicore_coreid_i;
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// Internal signals
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reg [SPR_SR_WIDTH-1:0] spr_sr;
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reg [SPR_SR_WIDTH-1:0] spr_esr;
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reg [OPTION_OPERAND_WIDTH-1:0] spr_epcr;
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reg [OPTION_OPERAND_WIDTH-1:0] spr_eear;
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// Programmable Interrupt Control SPRs
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wire [31:0] spr_picmr;
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wire [31:0] spr_picsr;
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// Tick Timer SPRs
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wire [31:0] spr_ttmr;
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wire [31:0] spr_ttcr;
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reg [OPTION_OPERAND_WIDTH-1:0] spr_ppc;
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reg [OPTION_OPERAND_WIDTH-1:0] spr_npc;
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reg execute_delay_slot;
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reg delay_slot_rf_we_done;
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output [OPTION_OPERAND_WIDTH-1:0] ctrl_branch_target_o;
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reg execute_go;
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wire execute_done;
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reg execute_waiting_r;
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reg decode_execute_halt;
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reg exception_taken;
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reg [OPTION_OPERAND_WIDTH-1:0] last_branch_insn_pc;
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reg [OPTION_OPERAND_WIDTH-1:0] last_branch_target_pc;
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reg take_exception;
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reg exception_r;
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reg [OPTION_OPERAND_WIDTH-1:0] exception_pc_addr;
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reg waiting_for_fetch;
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reg branched_and_waiting_for_fetch;
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reg doing_rfe_r;
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wire doing_rfe;
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wire deassert_doing_rfe;
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wire exception, exception_pending;
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wire execute_stage_exceptions;
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wire decode_stage_exceptions;
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wire exception_re;
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wire except_ticktimer;
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wire except_pic;
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wire except_ticktimer_nonsrmasked;
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wire except_pic_nonsrmasked;
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wire except_range;
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wire [15:0] spr_addr;
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wire op_mtspr;
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wire op_mfspr;
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wire op_rfe;
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wire [OPTION_OPERAND_WIDTH-1:0] b;
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wire execute_waiting;
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wire execute_valid;
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wire deassert_decode_execute_halt;
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wire ctrl_branch_occur;
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wire new_branch;
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output ctrl_branch_occur_o;
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output rf_we_o;
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input rf_wb_i;
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wire except_ibus_align;
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wire fetch_advance;
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wire rfete;
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wire stall_on_trap;
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/* Debug SPRs */
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reg [31:0] spr_dmr1;
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reg [31:0] spr_dmr2;
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reg [31:0] spr_dsr;
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reg [31:0] spr_drr;
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/* DU internal control signals */
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wire du_access;
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wire cpu_stall;
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wire du_restart_from_stall;
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wire [1:0] pstep;
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wire stepping;
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wire stepped_into_delay_slot;
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wire du_npc_write;
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reg du_npc_written;
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reg [OPTION_OPERAND_WIDTH-1:0] du_spr_npc;
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/* Wires for SPR management */
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wire spr_group_present;
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wire [3:0] spr_group;
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wire spr_we;
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wire spr_read;
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wire [OPTION_OPERAND_WIDTH-1:0] spr_write_dat;
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wire [11:0] spr_access_ack;
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wire [31:0] spr_internal_read_dat [0:12];
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wire spr_read_access;
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wire spr_write_access;
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wire spr_bus_access;
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reg [OPTION_OPERAND_WIDTH-1:0] spr_sys_group_read;
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/* Wires from mor1kx_cfgrs module */
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wire [31:0] spr_vr;
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wire [31:0] spr_vr2;
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wire [31:0] spr_avr;
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wire [31:0] spr_upr;
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wire [31:0] spr_cpucfgr;
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wire [31:0] spr_dmmucfgr;
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wire [31:0] spr_immucfgr;
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wire [31:0] spr_dccfgr;
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wire [31:0] spr_iccfgr;
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wire [31:0] spr_dcfgr;
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wire [31:0] spr_pccfgr;
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wire [31:0] spr_fpcsr = 0;
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wire [31:0] spr_isr [0:7];
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|
|
|
338 |
|
|
assign b = ctrl_rfb_i;
|
339 |
|
|
|
340 |
|
|
assign ctrl_branch_exception = (exception_r | (op_rfe | doing_rfe)) &
|
341 |
|
|
!exception_taken;
|
342 |
|
|
assign exception_pending = (except_ibus_err_i | except_ibus_align |
|
343 |
|
|
except_illegal_i | except_syscall_i |
|
344 |
|
|
except_dbus_i | except_align_i |
|
345 |
|
|
except_ticktimer | except_range |
|
346 |
|
|
except_pic | except_trap_i );
|
347 |
|
|
|
348 |
|
|
assign exception = exception_pending;
|
349 |
|
|
|
350 |
|
|
assign fetch_take_exception_branch_o = (take_exception | op_rfe) &
|
351 |
|
|
!stepping;
|
352 |
|
|
|
353 |
|
|
assign execute_stage_exceptions = except_dbus_i | except_align_i |
|
354 |
|
|
except_range;
|
355 |
|
|
assign decode_stage_exceptions = except_trap_i | except_illegal_i;
|
356 |
|
|
|
357 |
|
|
assign exception_re = exception & !exception_r & !exception_taken;
|
358 |
|
|
|
359 |
|
|
assign deassert_decode_execute_halt = ctrl_branch_occur &
|
360 |
|
|
decode_execute_halt;
|
361 |
|
|
|
362 |
|
|
assign ctrl_branch_except_pc = (op_rfe | doing_rfe) & !rfete ? spr_epcr :
|
363 |
|
|
exception_pc_addr;
|
364 |
|
|
|
365 |
|
|
// Exceptions take precedence
|
366 |
|
|
assign ctrl_branch_occur = // instruction is branch, and flag is right
|
367 |
|
|
(op_jbr_i &
|
368 |
|
|
// is l.j or l.jal
|
369 |
|
|
(!(|ctrl_opc_insn_i[2:1]) |
|
370 |
|
|
// is l.bf/bnf and flag is right
|
371 |
|
|
(ctrl_opc_insn_i[2]==flag))) |
|
372 |
|
|
(op_jr_i & !(except_ibus_align));
|
373 |
|
|
|
374 |
|
|
assign ctrl_branch_occur_o = // Usual branch signaling
|
375 |
|
|
((ctrl_branch_occur | ctrl_branch_exception) &
|
376 |
|
|
fetch_advance) |
|
377 |
|
|
// Need to tell the fetch stage to branch
|
378 |
|
|
// when it gets the next instruction because
|
379 |
|
|
// there was fetch stalls between the branch
|
380 |
|
|
// and the delay slot insn
|
381 |
|
|
(execute_delay_slot);
|
382 |
|
|
|
383 |
|
|
assign ctrl_branch_target_o = ctrl_branch_exception ?
|
384 |
|
|
ctrl_branch_except_pc :
|
385 |
|
|
// jump or branch?
|
386 |
|
|
op_jbr_i ? ctrl_alu_result_i :
|
387 |
|
|
ctrl_rfb_i;
|
388 |
|
|
|
389 |
|
|
// Do writeback when we register our output to the next stage, or if
|
390 |
|
|
// we're doing mfspr
|
391 |
|
|
assign rf_we_o = (execute_done & !delay_slot_rf_we_done) &
|
392 |
|
|
((rf_wb_i & !op_mfspr
|
393 |
|
|
& !((op_lsu_load_i | op_lsu_store_i) &
|
394 |
|
|
except_dbus_i | except_align_i)) |
|
395 |
|
|
(op_mfspr));
|
396 |
|
|
|
397 |
|
|
assign except_range = (FEATURE_RANGE!="NONE") ? spr_sr[`OR1K_SPR_SR_OVE] &&
|
398 |
|
|
(spr_sr[`OR1K_SPR_SR_OV] | overflow_set_i &
|
399 |
|
|
execute_done) & !doing_rfe : 0;
|
400 |
|
|
|
401 |
|
|
// Check for unaligned jump address from register
|
402 |
|
|
assign except_ibus_align = op_jr_i & (|ctrl_rfb_i[1:0]);
|
403 |
|
|
|
404 |
|
|
// Return from exception to exception (if pending tick or PIC ints)
|
405 |
|
|
assign rfete = (spr_esr[`OR1K_SPR_SR_IEE] & except_pic_nonsrmasked) |
|
406 |
|
|
(spr_esr[`OR1K_SPR_SR_TEE] & except_ticktimer_nonsrmasked);
|
407 |
|
|
|
408 |
|
|
always @(posedge clk)
|
409 |
|
|
if (rst)
|
410 |
|
|
exception_pc_addr <= OPTION_RESET_PC;
|
411 |
|
|
else if (exception_re | (rfete & execute_done))
|
412 |
|
|
casez(
|
413 |
|
|
{except_ibus_err_i,
|
414 |
|
|
except_illegal_i,
|
415 |
|
|
except_align_i,
|
416 |
|
|
except_ibus_align,
|
417 |
|
|
except_syscall_i,
|
418 |
|
|
except_trap_i,
|
419 |
|
|
except_dbus_i,
|
420 |
|
|
except_range,
|
421 |
|
|
except_pic_nonsrmasked,
|
422 |
|
|
except_ticktimer_nonsrmasked
|
423 |
|
|
}
|
424 |
|
|
)
|
425 |
|
|
10'b1?????????:
|
426 |
|
|
exception_pc_addr <= {19'd0,`OR1K_BERR_VECTOR,8'd0};
|
427 |
|
|
10'b01????????:
|
428 |
|
|
exception_pc_addr <= {19'd0,`OR1K_ILLEGAL_VECTOR,8'd0};
|
429 |
|
|
10'b001???????,
|
430 |
|
|
10'b0001??????:
|
431 |
|
|
exception_pc_addr <= {19'd0,`OR1K_ALIGN_VECTOR,8'd0};
|
432 |
|
|
10'b00001?????:
|
433 |
|
|
exception_pc_addr <= {19'd0,`OR1K_SYSCALL_VECTOR,8'd0};
|
434 |
|
|
10'b000001????:
|
435 |
|
|
exception_pc_addr <= {19'd0,`OR1K_TRAP_VECTOR,8'd0};
|
436 |
|
|
10'b0000001???:
|
437 |
|
|
exception_pc_addr <= {19'd0,`OR1K_BERR_VECTOR,8'd0};
|
438 |
|
|
10'b00000001??:
|
439 |
|
|
exception_pc_addr <= {19'd0,`OR1K_RANGE_VECTOR,8'd0};
|
440 |
|
|
10'b000000001?:
|
441 |
|
|
exception_pc_addr <= {19'd0,`OR1K_INT_VECTOR,8'd0};
|
442 |
|
|
//10'b0000000001:
|
443 |
|
|
default:
|
444 |
|
|
exception_pc_addr <= {19'd0,`OR1K_TT_VECTOR,8'd0};
|
445 |
|
|
endcase // casex (...
|
446 |
|
|
|
447 |
|
|
assign op_mtspr = ctrl_opc_insn_i==`OR1K_OPCODE_MTSPR;
|
448 |
|
|
assign op_mfspr = ctrl_opc_insn_i==`OR1K_OPCODE_MFSPR;
|
449 |
|
|
assign op_rfe = ctrl_opc_insn_i==`OR1K_OPCODE_RFE;
|
450 |
|
|
|
451 |
|
|
reg waiting_for_except_fetch;
|
452 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
453 |
|
|
if (rst)
|
454 |
|
|
waiting_for_except_fetch <= 0;
|
455 |
|
|
else if (waiting_for_except_fetch & next_fetch_done_i)
|
456 |
|
|
waiting_for_except_fetch <= 0;
|
457 |
|
|
else if (fetch_take_exception_branch_o)
|
458 |
|
|
waiting_for_except_fetch <= 1;
|
459 |
|
|
|
460 |
|
|
assign fetch_advance = (next_fetch_done_i | except_ibus_err_i) &
|
461 |
|
|
!execute_waiting & !cpu_stall &
|
462 |
|
|
(!stepping |
|
463 |
|
|
(stepping & pstep[0] & !next_fetch_done_i));
|
464 |
|
|
|
465 |
|
|
assign padv_fetch_o = fetch_advance & !exception_pending & !doing_rfe_r &
|
466 |
|
|
!cpu_stall;
|
467 |
|
|
|
468 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
469 |
|
|
if (rst)
|
470 |
|
|
take_exception <= 0;
|
471 |
|
|
else
|
472 |
|
|
take_exception <= (exception_pending | exception_r) &
|
473 |
|
|
(fetch_advance |
|
474 |
|
|
// Cause exception to always be 'taken' if stepping
|
475 |
|
|
(stepping & execute_done)
|
476 |
|
|
) &
|
477 |
|
|
// Would like this as only a single pulse
|
478 |
|
|
!take_exception;
|
479 |
|
|
|
480 |
|
|
reg padv_decode_r;
|
481 |
|
|
// Some bits of the pipeline (execute_alu for instance) require a falling
|
482 |
|
|
// edge of the decode signal to start work on multi-cycle ops.
|
483 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
484 |
|
|
if (rst)
|
485 |
|
|
padv_decode_r <= 0;
|
486 |
|
|
else
|
487 |
|
|
padv_decode_r <= padv_fetch_o;
|
488 |
|
|
|
489 |
|
|
assign padv_decode_o = padv_decode_r;
|
490 |
|
|
|
491 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
492 |
|
|
if (rst)
|
493 |
|
|
execute_go <= 0;
|
494 |
|
|
else
|
495 |
|
|
execute_go <= padv_fetch_o | execute_waiting |
|
496 |
|
|
(stepping & next_fetch_done_i);
|
497 |
|
|
|
498 |
|
|
assign execute_done = execute_go & !execute_waiting;
|
499 |
|
|
|
500 |
|
|
// ALU or LSU stall execution, nothing else can
|
501 |
|
|
assign execute_valid = !((op_lsu_load_i | op_lsu_store_i) & !lsu_valid_i |
|
502 |
|
|
!alu_valid_i);
|
503 |
|
|
|
504 |
|
|
assign execute_waiting = !execute_valid & !waiting_for_fetch;
|
505 |
|
|
assign execute_waiting_o = execute_waiting;
|
506 |
|
|
|
507 |
|
|
|
508 |
|
|
assign padv_execute_o = execute_done;
|
509 |
|
|
|
510 |
|
|
assign spr_addr = du_access ? du_addr_i : ctrl_alu_result_i[15:0];
|
511 |
|
|
assign ctrl_mfspr_we_o = op_mfspr & execute_go;
|
512 |
|
|
|
513 |
|
|
// Pipeline flush
|
514 |
|
|
assign pipeline_flush_o = (execute_done & op_rfe) |
|
515 |
|
|
(exception_re) |
|
516 |
|
|
cpu_stall;
|
517 |
|
|
|
518 |
|
|
// Flag
|
519 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
520 |
|
|
if (rst)
|
521 |
|
|
flag <= 0;
|
522 |
|
|
else if (execute_done)
|
523 |
|
|
flag <= ctrl_flag_clear_i ? 0 :
|
524 |
|
|
ctrl_flag_set_i ? 1 : flag;
|
525 |
|
|
|
526 |
|
|
assign flag_o = flag;
|
527 |
|
|
|
528 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
529 |
|
|
if (rst)
|
530 |
|
|
execute_waiting_r <= 0;
|
531 |
|
|
else if (!execute_waiting)
|
532 |
|
|
execute_waiting_r <= 0;
|
533 |
|
|
else if (execute_waiting)
|
534 |
|
|
execute_waiting_r <= 1;
|
535 |
|
|
|
536 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
537 |
|
|
if (rst)
|
538 |
|
|
decode_execute_halt <= 0;
|
539 |
|
|
else if (du_restart_from_stall)
|
540 |
|
|
decode_execute_halt <= 0;
|
541 |
|
|
else if (decode_execute_halt & deassert_decode_execute_halt)
|
542 |
|
|
decode_execute_halt <= 0;
|
543 |
|
|
else if ((op_rfe | exception) & !decode_execute_halt & !exception_taken)
|
544 |
|
|
decode_execute_halt <= 1;
|
545 |
|
|
|
546 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
547 |
|
|
if (rst)
|
548 |
|
|
exception_r <= 0;
|
549 |
|
|
else if (exception_taken | du_restart_from_stall)
|
550 |
|
|
exception_r <= 0;
|
551 |
|
|
else if (exception & !exception_r)
|
552 |
|
|
exception_r <= 1;
|
553 |
|
|
|
554 |
|
|
// Signal to indicate that the incoming exception or l.rfe has been taken
|
555 |
|
|
// and we're waiting for it to propagate through the pipeline.
|
556 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
557 |
|
|
if (rst)
|
558 |
|
|
exception_taken <= 0;
|
559 |
|
|
else if (exception_taken)
|
560 |
|
|
exception_taken <= 0;
|
561 |
|
|
else if (exception_r & take_exception)
|
562 |
|
|
exception_taken <= 1;
|
563 |
|
|
|
564 |
|
|
assign exception_taken_o = exception_taken;
|
565 |
|
|
|
566 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
567 |
|
|
if (rst)
|
568 |
|
|
last_branch_insn_pc <= 0;
|
569 |
|
|
else if (fetch_advance & ctrl_branch_occur)
|
570 |
|
|
last_branch_insn_pc <= spr_ppc;
|
571 |
|
|
|
572 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
573 |
|
|
if (rst)
|
574 |
|
|
last_branch_target_pc <= 0;
|
575 |
|
|
else if (execute_done & ctrl_branch_occur & stepping)
|
576 |
|
|
last_branch_target_pc <= ctrl_branch_target_o;
|
577 |
|
|
|
578 |
|
|
// Used to gate execute stage's advance signal in the case where a LSU op has
|
579 |
|
|
// finished before the next instruction has been fetched. Typically this
|
580 |
|
|
// occurs when not using icache and doing lots of memory accesses.
|
581 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
582 |
|
|
if (rst)
|
583 |
|
|
waiting_for_fetch <= 0;
|
584 |
|
|
else if (next_fetch_done_i)
|
585 |
|
|
waiting_for_fetch <= 0;
|
586 |
|
|
else if (!execute_waiting & execute_waiting_r & !next_fetch_done_i)
|
587 |
|
|
waiting_for_fetch <= 1;
|
588 |
|
|
|
589 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
590 |
|
|
if (rst)
|
591 |
|
|
branched_and_waiting_for_fetch <= 0;
|
592 |
|
|
else if (exception_re)
|
593 |
|
|
branched_and_waiting_for_fetch <= 0;
|
594 |
|
|
else if (padv_fetch_o & ctrl_branch_occur_o)
|
595 |
|
|
branched_and_waiting_for_fetch <= 1;
|
596 |
|
|
else if (branched_and_waiting_for_fetch)
|
597 |
|
|
branched_and_waiting_for_fetch <= !next_fetch_done_i;
|
598 |
|
|
|
599 |
|
|
|
600 |
|
|
|
601 |
|
|
assign doing_rfe = ((execute_done & op_rfe) | doing_rfe_r) &
|
602 |
|
|
!deassert_doing_rfe;
|
603 |
|
|
|
604 |
|
|
// Basically, the fetch stage should always take the rfe immediately
|
605 |
|
|
assign deassert_doing_rfe = doing_rfe_r;
|
606 |
|
|
|
607 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
608 |
|
|
if (rst)
|
609 |
|
|
doing_rfe_r <= 0;
|
610 |
|
|
else if (deassert_doing_rfe)
|
611 |
|
|
doing_rfe_r <= 0;
|
612 |
|
|
else if (execute_done)
|
613 |
|
|
doing_rfe_r <= op_rfe;
|
614 |
|
|
|
615 |
|
|
assign spr_sr_o = spr_sr;
|
616 |
|
|
|
617 |
|
|
// Supervision register
|
618 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
619 |
|
|
if (rst)
|
620 |
|
|
spr_sr <= SPR_SR_RESET_VALUE;
|
621 |
|
|
else if (fetch_take_exception_branch_o)
|
622 |
|
|
begin
|
623 |
|
|
if (op_rfe & !rfete)
|
624 |
|
|
begin
|
625 |
|
|
spr_sr <= spr_esr;
|
626 |
|
|
end
|
627 |
|
|
else
|
628 |
|
|
begin
|
629 |
|
|
// Go into supervisor mode, disable interrupts, MMUs
|
630 |
|
|
spr_sr[`OR1K_SPR_SR_SM ] <= 1'b1;
|
631 |
|
|
if (FEATURE_TIMER!="NONE")
|
632 |
|
|
spr_sr[`OR1K_SPR_SR_TEE ] <= 1'b0;
|
633 |
|
|
if (FEATURE_PIC!="NONE")
|
634 |
|
|
spr_sr[`OR1K_SPR_SR_IEE ] <= 1'b0;
|
635 |
|
|
if (FEATURE_DMMU!="NONE")
|
636 |
|
|
spr_sr[`OR1K_SPR_SR_DME ] <= 1'b0;
|
637 |
|
|
if (FEATURE_IMMU!="NONE")
|
638 |
|
|
spr_sr[`OR1K_SPR_SR_IME ] <= 1'b0;
|
639 |
|
|
if (FEATURE_OVERFLOW!="NONE")
|
640 |
|
|
spr_sr[`OR1K_SPR_SR_OVE ] <= 1'b0;
|
641 |
|
|
end
|
642 |
|
|
end
|
643 |
|
|
else if (execute_done)
|
644 |
|
|
begin
|
645 |
|
|
spr_sr[`OR1K_SPR_SR_F ] <= ctrl_flag_set_i ? 1 :
|
646 |
|
|
ctrl_flag_clear_i ? 0 :
|
647 |
|
|
spr_sr[`OR1K_SPR_SR_F ];
|
648 |
|
|
spr_sr[`OR1K_SPR_SR_CY ] <= carry_set_i ? 1 :
|
649 |
|
|
carry_clear_i ? 0 :
|
650 |
|
|
spr_sr[`OR1K_SPR_SR_CY ];
|
651 |
|
|
|
652 |
|
|
if (FEATURE_OVERFLOW!="NONE")
|
653 |
|
|
spr_sr[`OR1K_SPR_SR_OV ] <= overflow_set_i ? 1 :
|
654 |
|
|
overflow_clear_i ? 0 :
|
655 |
|
|
spr_sr[`OR1K_SPR_SR_OV ];
|
656 |
|
|
|
657 |
|
|
if ((spr_we & (spr_sr[`OR1K_SPR_SR_SM] | du_access)) &&
|
658 |
|
|
spr_addr==`OR1K_SPR_SR_ADDR)
|
659 |
|
|
begin
|
660 |
|
|
spr_sr[`OR1K_SPR_SR_SM ] <= spr_write_dat[`OR1K_SPR_SR_SM ];
|
661 |
|
|
|
662 |
|
|
spr_sr[`OR1K_SPR_SR_F ] <= spr_write_dat[`OR1K_SPR_SR_F ];
|
663 |
|
|
|
664 |
|
|
if (FEATURE_TIMER!="NONE")
|
665 |
|
|
spr_sr[`OR1K_SPR_SR_TEE ] <= spr_write_dat[`OR1K_SPR_SR_TEE ];
|
666 |
|
|
|
667 |
|
|
if (FEATURE_PIC!="NONE")
|
668 |
|
|
spr_sr[`OR1K_SPR_SR_IEE ] <= spr_write_dat[`OR1K_SPR_SR_IEE ];
|
669 |
|
|
|
670 |
|
|
if (FEATURE_DATACACHE!="NONE")
|
671 |
|
|
spr_sr[`OR1K_SPR_SR_DCE ] <= spr_write_dat[`OR1K_SPR_SR_DCE ];
|
672 |
|
|
|
673 |
|
|
if (FEATURE_INSTRUCTIONCACHE!="NONE")
|
674 |
|
|
spr_sr[`OR1K_SPR_SR_ICE ] <= spr_write_dat[`OR1K_SPR_SR_ICE ];
|
675 |
|
|
|
676 |
|
|
if (FEATURE_DMMU!="NONE")
|
677 |
|
|
spr_sr[`OR1K_SPR_SR_DME ] <= spr_write_dat[`OR1K_SPR_SR_DME ];
|
678 |
|
|
|
679 |
|
|
if (FEATURE_IMMU!="NONE")
|
680 |
|
|
spr_sr[`OR1K_SPR_SR_IME ] <= spr_write_dat[`OR1K_SPR_SR_IME ];
|
681 |
|
|
|
682 |
|
|
if (FEATURE_FASTCONTEXTS!="NONE")
|
683 |
|
|
spr_sr[`OR1K_SPR_SR_CE ] <= spr_write_dat[`OR1K_SPR_SR_CE ];
|
684 |
|
|
|
685 |
|
|
spr_sr[`OR1K_SPR_SR_CY ] <= spr_write_dat[`OR1K_SPR_SR_CY ];
|
686 |
|
|
|
687 |
|
|
if (FEATURE_OVERFLOW!="NONE") begin
|
688 |
|
|
spr_sr[`OR1K_SPR_SR_OV ] <= spr_write_dat[`OR1K_SPR_SR_OV ];
|
689 |
|
|
spr_sr[`OR1K_SPR_SR_OVE ] <= spr_write_dat[`OR1K_SPR_SR_OVE ];
|
690 |
|
|
end
|
691 |
|
|
|
692 |
|
|
if (FEATURE_DSX!="NONE")
|
693 |
|
|
spr_sr[`OR1K_SPR_SR_DSX ] <= spr_write_dat[`OR1K_SPR_SR_DSX ];
|
694 |
|
|
|
695 |
|
|
spr_sr[`OR1K_SPR_SR_EPH ] <= spr_write_dat[`OR1K_SPR_SR_EPH ];
|
696 |
|
|
|
697 |
|
|
end // if ((spr_we & (spr_sr[`OR1K_SPR_SR_SM] | du_access)) &&...
|
698 |
|
|
|
699 |
|
|
/* Need to check for DSX being set on exception entry on execute_done
|
700 |
|
|
as the delay slot information is gone after it goes high */
|
701 |
|
|
if (FEATURE_DSX!="NONE")
|
702 |
|
|
if (exception_r || exception_re)
|
703 |
|
|
spr_sr[`OR1K_SPR_SR_DSX ] <= execute_delay_slot;
|
704 |
|
|
|
705 |
|
|
end // if (execute_done)
|
706 |
|
|
|
707 |
|
|
assign carry_o = spr_sr[`OR1K_SPR_SR_CY];
|
708 |
|
|
|
709 |
|
|
// Exception SR
|
710 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
711 |
|
|
if (rst)
|
712 |
|
|
spr_esr <= SPR_SR_RESET_VALUE;
|
713 |
|
|
else if (exception_re)
|
714 |
|
|
begin
|
715 |
|
|
spr_esr <= spr_sr;
|
716 |
|
|
/*
|
717 |
|
|
A bit odd, but if we had a l.sf instruction on an exception rising
|
718 |
|
|
edge, EPCR will point to the insn past the l.sf but the flag will
|
719 |
|
|
not have been saved to the SR properly. So we must put it in here
|
720 |
|
|
so it can be restored correctly.
|
721 |
|
|
Ditto for the other flags which may have been changed in a similar
|
722 |
|
|
fashion.
|
723 |
|
|
*/
|
724 |
|
|
if (execute_done)
|
725 |
|
|
begin
|
726 |
|
|
if (ctrl_flag_set_i)
|
727 |
|
|
spr_esr[`OR1K_SPR_SR_F ] <= 1'b1;
|
728 |
|
|
else if (ctrl_flag_clear_i)
|
729 |
|
|
spr_esr[`OR1K_SPR_SR_F ] <= 1'b0;
|
730 |
|
|
if (FEATURE_OVERFLOW!="NONE")
|
731 |
|
|
begin
|
732 |
|
|
if (overflow_set_i)
|
733 |
|
|
spr_esr[`OR1K_SPR_SR_OV ] <= 1'b1;
|
734 |
|
|
else if (overflow_clear_i)
|
735 |
|
|
spr_esr[`OR1K_SPR_SR_OV ] <= 1'b0;
|
736 |
|
|
end
|
737 |
|
|
if (carry_set_i)
|
738 |
|
|
spr_esr[`OR1K_SPR_SR_CY ] <= 1'b1;
|
739 |
|
|
else if (carry_clear_i)
|
740 |
|
|
spr_esr[`OR1K_SPR_SR_CY ] <= 1'b0;
|
741 |
|
|
end
|
742 |
|
|
end
|
743 |
|
|
else if (spr_we & spr_addr==`OR1K_SPR_ESR0_ADDR)
|
744 |
|
|
spr_esr <= spr_write_dat[SPR_SR_WIDTH-1:0];
|
745 |
|
|
|
746 |
|
|
// Exception PC
|
747 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
748 |
|
|
if (rst)
|
749 |
|
|
spr_epcr <= OPTION_RESET_PC;
|
750 |
|
|
else if (exception_re & !(rfete & (op_rfe | deassert_doing_rfe)))
|
751 |
|
|
begin
|
752 |
|
|
if (except_ibus_err_i)
|
753 |
|
|
spr_epcr <= spr_ppc-4;
|
754 |
|
|
else if (except_syscall_i)
|
755 |
|
|
// EPCR after syscall is address of next not executed insn.
|
756 |
|
|
spr_epcr <= spr_npc;
|
757 |
|
|
else if (except_ticktimer | except_pic)
|
758 |
|
|
spr_epcr <= branched_and_waiting_for_fetch ? spr_npc :
|
759 |
|
|
execute_delay_slot ? spr_ppc-4 : spr_ppc+4;
|
760 |
|
|
else if (execute_stage_exceptions |
|
761 |
|
|
// Don't update EPCR on software breakpoint
|
762 |
|
|
(decode_stage_exceptions & !(stall_on_trap & except_trap_i)))
|
763 |
|
|
spr_epcr <= execute_delay_slot ? spr_ppc-4 : spr_ppc;
|
764 |
|
|
else if (!(stall_on_trap & except_trap_i))
|
765 |
|
|
spr_epcr <= execute_delay_slot ? spr_ppc-4 : spr_ppc;
|
766 |
|
|
end
|
767 |
|
|
else if (spr_we && spr_addr==`OR1K_SPR_EPCR0_ADDR)
|
768 |
|
|
spr_epcr <= spr_write_dat;
|
769 |
|
|
|
770 |
|
|
// Exception Effective Address
|
771 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
772 |
|
|
if (rst)
|
773 |
|
|
spr_eear <= {OPTION_OPERAND_WIDTH{1'b0}};
|
774 |
|
|
else if (exception_re)
|
775 |
|
|
begin
|
776 |
|
|
if (except_ibus_err_i)
|
777 |
|
|
spr_eear <= pc_fetch_i;
|
778 |
|
|
else
|
779 |
|
|
spr_eear <= ctrl_alu_result_i;
|
780 |
|
|
end
|
781 |
|
|
|
782 |
|
|
// Next PC (NPC)
|
783 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
784 |
|
|
if (rst)
|
785 |
|
|
spr_npc <= OPTION_RESET_PC;
|
786 |
|
|
else if (deassert_doing_rfe)
|
787 |
|
|
spr_npc <= rfete ? exception_pc_addr : spr_epcr;
|
788 |
|
|
else if (du_restart_o)
|
789 |
|
|
spr_npc <= du_restart_pc_o;
|
790 |
|
|
else if (stepping & next_fetch_done_i)
|
791 |
|
|
spr_npc <= execute_delay_slot ? last_branch_target_pc : pc_fetch_i;
|
792 |
|
|
else if (stepping & exception_r)
|
793 |
|
|
spr_npc <= exception_pc_addr;
|
794 |
|
|
else if (fetch_advance)
|
795 |
|
|
// PC we're now executing
|
796 |
|
|
spr_npc <= fetch_take_exception_branch_o ? exception_pc_addr :
|
797 |
|
|
ctrl_branch_occur ? ctrl_branch_target_o : pc_fetch_i;
|
798 |
|
|
|
799 |
|
|
// Previous PC (PPC)
|
800 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
801 |
|
|
if (rst)
|
802 |
|
|
spr_ppc <= OPTION_RESET_PC;
|
803 |
|
|
else if (padv_fetch_o | (stepping & next_fetch_done_i))
|
804 |
|
|
spr_ppc <= spr_npc; // PC we've got in execute stage (about to finish)
|
805 |
|
|
|
806 |
|
|
assign spr_npc_o = spr_npc;
|
807 |
|
|
assign spr_ppc_o = spr_ppc;
|
808 |
|
|
|
809 |
|
|
// Remember when we're in a delay slot in execute stage.
|
810 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
811 |
|
|
if (rst)
|
812 |
|
|
execute_delay_slot <= 0;
|
813 |
|
|
else if (execute_done)
|
814 |
|
|
execute_delay_slot <= execute_delay_slot ? 0 :
|
815 |
|
|
ctrl_branch_occur;
|
816 |
|
|
|
817 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
818 |
|
|
if (rst)
|
819 |
|
|
delay_slot_rf_we_done <= 0;
|
820 |
|
|
else
|
821 |
|
|
delay_slot_rf_we_done <= rf_we_o & execute_delay_slot;
|
822 |
|
|
|
823 |
|
|
mor1kx_cfgrs
|
824 |
|
|
#(.FEATURE_PIC (FEATURE_PIC),
|
825 |
|
|
.FEATURE_TIMER (FEATURE_TIMER),
|
826 |
|
|
.OPTION_PIC_TRIGGER (OPTION_PIC_TRIGGER),
|
827 |
|
|
.FEATURE_DSX (FEATURE_DSX),
|
828 |
|
|
.FEATURE_FASTCONTEXTS (FEATURE_FASTCONTEXTS),
|
829 |
|
|
.FEATURE_OVERFLOW (FEATURE_OVERFLOW),
|
830 |
|
|
.FEATURE_DATACACHE (FEATURE_DATACACHE),
|
831 |
|
|
.OPTION_DCACHE_BLOCK_WIDTH (OPTION_DCACHE_BLOCK_WIDTH),
|
832 |
|
|
.OPTION_DCACHE_SET_WIDTH (OPTION_DCACHE_SET_WIDTH),
|
833 |
|
|
.OPTION_DCACHE_WAYS (OPTION_DCACHE_WAYS),
|
834 |
|
|
.FEATURE_DMMU (FEATURE_DMMU),
|
835 |
|
|
.FEATURE_INSTRUCTIONCACHE (FEATURE_INSTRUCTIONCACHE),
|
836 |
|
|
.OPTION_ICACHE_BLOCK_WIDTH (OPTION_ICACHE_BLOCK_WIDTH),
|
837 |
|
|
.OPTION_ICACHE_SET_WIDTH (OPTION_ICACHE_SET_WIDTH),
|
838 |
|
|
.OPTION_ICACHE_WAYS (OPTION_ICACHE_WAYS),
|
839 |
|
|
.FEATURE_IMMU (FEATURE_IMMU),
|
840 |
|
|
.FEATURE_DEBUGUNIT (FEATURE_DEBUGUNIT),
|
841 |
|
|
.FEATURE_PERFCOUNTERS (FEATURE_PERFCOUNTERS),
|
842 |
|
|
.FEATURE_MAC (FEATURE_MAC),
|
843 |
|
|
.FEATURE_SYSCALL (FEATURE_SYSCALL),
|
844 |
|
|
.FEATURE_TRAP (FEATURE_TRAP),
|
845 |
|
|
.FEATURE_RANGE (FEATURE_RANGE),
|
846 |
|
|
.FEATURE_DELAYSLOT ("ENABLED")
|
847 |
|
|
)
|
848 |
|
|
mor1kx_cfgrs
|
849 |
|
|
(/*AUTOINST*/
|
850 |
|
|
// Outputs
|
851 |
|
|
.spr_vr (spr_vr[31:0]),
|
852 |
|
|
.spr_vr2 (spr_vr2[31:0]),
|
853 |
|
|
.spr_upr (spr_upr[31:0]),
|
854 |
|
|
.spr_cpucfgr (spr_cpucfgr[31:0]),
|
855 |
|
|
.spr_dmmucfgr (spr_dmmucfgr[31:0]),
|
856 |
|
|
.spr_immucfgr (spr_immucfgr[31:0]),
|
857 |
|
|
.spr_dccfgr (spr_dccfgr[31:0]),
|
858 |
|
|
.spr_iccfgr (spr_iccfgr[31:0]),
|
859 |
|
|
.spr_dcfgr (spr_dcfgr[31:0]),
|
860 |
|
|
.spr_pccfgr (spr_pccfgr[31:0]),
|
861 |
|
|
.spr_avr (spr_avr[31:0]));
|
862 |
|
|
|
863 |
|
|
/* Implementation-specific registers */
|
864 |
|
|
assign spr_isr[0] = 0;
|
865 |
|
|
assign spr_isr[1] = 0;
|
866 |
|
|
assign spr_isr[2] = 0;
|
867 |
|
|
assign spr_isr[3] = 0;
|
868 |
|
|
assign spr_isr[4] = 0;
|
869 |
|
|
assign spr_isr[5] = 0;
|
870 |
|
|
assign spr_isr[6] = 0;
|
871 |
|
|
assign spr_isr[7] = 0;
|
872 |
|
|
|
873 |
|
|
// System group (0) SPR data out
|
874 |
|
|
always @*
|
875 |
|
|
case(spr_addr)
|
876 |
|
|
`OR1K_SPR_VR_ADDR:
|
877 |
|
|
spr_sys_group_read = spr_vr;
|
878 |
|
|
`OR1K_SPR_VR2_ADDR:
|
879 |
|
|
spr_sys_group_read = {spr_vr2[31:8], `MOR1KX_PIPEID_ESPRESSO};
|
880 |
|
|
`OR1K_SPR_AVR_ADDR:
|
881 |
|
|
spr_sys_group_read = spr_avr;
|
882 |
|
|
`OR1K_SPR_UPR_ADDR:
|
883 |
|
|
spr_sys_group_read = spr_upr;
|
884 |
|
|
`OR1K_SPR_CPUCFGR_ADDR:
|
885 |
|
|
spr_sys_group_read = spr_cpucfgr;
|
886 |
|
|
`OR1K_SPR_DMMUCFGR_ADDR:
|
887 |
|
|
spr_sys_group_read = spr_dmmucfgr;
|
888 |
|
|
`OR1K_SPR_IMMUCFGR_ADDR:
|
889 |
|
|
spr_sys_group_read = spr_immucfgr;
|
890 |
|
|
`OR1K_SPR_DCCFGR_ADDR:
|
891 |
|
|
spr_sys_group_read = spr_dccfgr;
|
892 |
|
|
`OR1K_SPR_ICCFGR_ADDR:
|
893 |
|
|
spr_sys_group_read = spr_iccfgr;
|
894 |
|
|
`OR1K_SPR_DCFGR_ADDR:
|
895 |
|
|
spr_sys_group_read = spr_dcfgr;
|
896 |
|
|
`OR1K_SPR_PCCFGR_ADDR:
|
897 |
|
|
spr_sys_group_read = spr_pccfgr;
|
898 |
|
|
`OR1K_SPR_NPC_ADDR:
|
899 |
|
|
spr_sys_group_read = spr_npc;
|
900 |
|
|
`OR1K_SPR_SR_ADDR:
|
901 |
|
|
spr_sys_group_read = {{(OPTION_OPERAND_WIDTH-SPR_SR_WIDTH){1'b0}},
|
902 |
|
|
spr_sr};
|
903 |
|
|
|
904 |
|
|
`OR1K_SPR_PPC_ADDR:
|
905 |
|
|
spr_sys_group_read = spr_ppc;
|
906 |
|
|
`OR1K_SPR_FPCSR_ADDR:
|
907 |
|
|
spr_sys_group_read = spr_fpcsr;
|
908 |
|
|
`OR1K_SPR_EPCR0_ADDR:
|
909 |
|
|
spr_sys_group_read = spr_epcr;
|
910 |
|
|
`OR1K_SPR_EEAR0_ADDR:
|
911 |
|
|
spr_sys_group_read = spr_eear;
|
912 |
|
|
`OR1K_SPR_ESR0_ADDR:
|
913 |
|
|
spr_sys_group_read = {{(OPTION_OPERAND_WIDTH-SPR_SR_WIDTH){1'b0}},
|
914 |
|
|
spr_esr};
|
915 |
|
|
`OR1K_SPR_ISR0_ADDR:
|
916 |
|
|
spr_sys_group_read = spr_isr[0];
|
917 |
|
|
`OR1K_SPR_ISR0_ADDR +1:
|
918 |
|
|
spr_sys_group_read = spr_isr[1];
|
919 |
|
|
`OR1K_SPR_ISR0_ADDR +2:
|
920 |
|
|
spr_sys_group_read = spr_isr[2];
|
921 |
|
|
`OR1K_SPR_ISR0_ADDR +3:
|
922 |
|
|
spr_sys_group_read = spr_isr[3];
|
923 |
|
|
`OR1K_SPR_ISR0_ADDR +4:
|
924 |
|
|
spr_sys_group_read = spr_isr[4];
|
925 |
|
|
`OR1K_SPR_ISR0_ADDR +5:
|
926 |
|
|
spr_sys_group_read = spr_isr[5];
|
927 |
|
|
`OR1K_SPR_ISR0_ADDR +6:
|
928 |
|
|
spr_sys_group_read = spr_isr[6];
|
929 |
|
|
`OR1K_SPR_ISR0_ADDR +7:
|
930 |
|
|
spr_sys_group_read = spr_isr[7];
|
931 |
|
|
|
932 |
|
|
`OR1K_SPR_COREID_ADDR:
|
933 |
|
|
// If the multicore feature is activated this address returns the
|
934 |
|
|
// core identifier, 0 otherwise
|
935 |
|
|
spr_sys_group_read = (FEATURE_MULTICORE != "NONE") ?
|
936 |
|
|
multicore_coreid_i : 0;
|
937 |
|
|
|
938 |
|
|
default: begin
|
939 |
|
|
/* GPR read */
|
940 |
|
|
if (spr_addr >= `OR1K_SPR_GPR0_ADDR &&
|
941 |
|
|
spr_addr <= (`OR1K_SPR_GPR0_ADDR + 32))
|
942 |
|
|
spr_sys_group_read = b; /* Register file */
|
943 |
|
|
else
|
944 |
|
|
/* Invalid address - read as zero*/
|
945 |
|
|
spr_sys_group_read = 0;
|
946 |
|
|
end
|
947 |
|
|
endcase // case (spr_addr)
|
948 |
|
|
|
949 |
|
|
/* System group read data MUX in */
|
950 |
|
|
assign spr_internal_read_dat[0] = spr_sys_group_read;
|
951 |
|
|
/* System group ack generation */
|
952 |
|
|
/* TODO - might be delay for register file reads! */
|
953 |
|
|
assign spr_access_ack[0] = 1;
|
954 |
|
|
|
955 |
|
|
|
956 |
|
|
|
957 |
|
|
/* Generate data to the register file for mfspr operations */
|
958 |
|
|
assign mfspr_dat_o = spr_internal_read_dat[spr_addr[14:11]];
|
959 |
|
|
|
960 |
|
|
// PIC SPR control
|
961 |
|
|
generate
|
962 |
|
|
if (FEATURE_PIC !="NONE") begin : pic
|
963 |
|
|
|
964 |
|
|
/* mor1kx_pic AUTO_TEMPLATE (
|
965 |
|
|
.spr_picsr_o (spr_picsr),
|
966 |
|
|
.spr_picmr_o (spr_picmr),
|
967 |
|
|
.spr_bus_ack (spr_access_ack[9]),
|
968 |
|
|
.spr_dat_o (spr_internal_read_dat[9]),
|
969 |
|
|
// Inputs
|
970 |
|
|
.spr_we_i (spr_we),
|
971 |
|
|
.spr_access_i (1'b1),
|
972 |
|
|
.spr_addr_i (spr_addr),
|
973 |
|
|
.spr_dat_i (spr_write_dat),
|
974 |
|
|
);*/
|
975 |
|
|
mor1kx_pic
|
976 |
|
|
#(
|
977 |
|
|
.OPTION_PIC_TRIGGER(OPTION_PIC_TRIGGER),
|
978 |
|
|
.OPTION_PIC_NMI_WIDTH(OPTION_PIC_NMI_WIDTH)
|
979 |
|
|
)
|
980 |
|
|
mor1kx_pic
|
981 |
|
|
(/*AUTOINST*/
|
982 |
|
|
// Outputs
|
983 |
|
|
.spr_picmr_o (spr_picmr), // Templated
|
984 |
|
|
.spr_picsr_o (spr_picsr), // Templated
|
985 |
|
|
.spr_bus_ack (spr_access_ack[9]), // Templated
|
986 |
|
|
.spr_dat_o (spr_internal_read_dat[9]), // Templated
|
987 |
|
|
// Inputs
|
988 |
|
|
.clk (clk),
|
989 |
|
|
.rst (rst),
|
990 |
|
|
.irq_i (irq_i[31:0]),
|
991 |
|
|
.spr_access_i (1'b1), // Templated
|
992 |
|
|
.spr_we_i (spr_we), // Templated
|
993 |
|
|
.spr_addr_i (spr_addr), // Templated
|
994 |
|
|
.spr_dat_i (spr_write_dat)); // Templated
|
995 |
|
|
|
996 |
|
|
assign except_pic_nonsrmasked = (|spr_picsr) &
|
997 |
|
|
!op_mtspr &
|
998 |
|
|
// Stops back-to-back branch addresses going to
|
999 |
|
|
// fetch stage
|
1000 |
|
|
!ctrl_branch_occur &
|
1001 |
|
|
// Stops issues with PC when branching
|
1002 |
|
|
!execute_delay_slot;
|
1003 |
|
|
|
1004 |
|
|
assign except_pic = spr_sr[`OR1K_SPR_SR_IEE] & except_pic_nonsrmasked &
|
1005 |
|
|
!doing_rfe;
|
1006 |
|
|
end
|
1007 |
|
|
else begin
|
1008 |
|
|
assign except_pic_nonsrmasked = 0;
|
1009 |
|
|
assign except_pic = 0;
|
1010 |
|
|
assign spr_picsr = 0;
|
1011 |
|
|
assign spr_picmr = 0;
|
1012 |
|
|
assign spr_access_ack[9] = 0;
|
1013 |
|
|
assign spr_internal_read_dat[9] = 0;
|
1014 |
|
|
end // else: !if(FEATURE_PIC !="NONE")
|
1015 |
|
|
endgenerate
|
1016 |
|
|
|
1017 |
|
|
|
1018 |
|
|
generate
|
1019 |
|
|
if (FEATURE_TIMER!="NONE") begin : tt
|
1020 |
|
|
|
1021 |
|
|
/* mor1kx_ticktimer AUTO_TEMPLATE (
|
1022 |
|
|
.spr_ttmr_o (spr_ttmr),
|
1023 |
|
|
.spr_ttcr_o (spr_ttcr),
|
1024 |
|
|
.spr_bus_ack (spr_access_ack[10]),
|
1025 |
|
|
.spr_dat_o (spr_internal_read_dat[10]),
|
1026 |
|
|
// Inputs
|
1027 |
|
|
.spr_we_i (spr_we),
|
1028 |
|
|
.spr_access_i (1'b1),
|
1029 |
|
|
.spr_addr_i (spr_addr),
|
1030 |
|
|
.spr_dat_i (spr_write_dat),
|
1031 |
|
|
);*/
|
1032 |
|
|
mor1kx_ticktimer mor1kx_ticktimer
|
1033 |
|
|
(/*AUTOINST*/
|
1034 |
|
|
// Outputs
|
1035 |
|
|
.spr_ttmr_o (spr_ttmr), // Templated
|
1036 |
|
|
.spr_ttcr_o (spr_ttcr), // Templated
|
1037 |
|
|
.spr_bus_ack (spr_access_ack[10]), // Templated
|
1038 |
|
|
.spr_dat_o (spr_internal_read_dat[10]), // Templated
|
1039 |
|
|
// Inputs
|
1040 |
|
|
.clk (clk),
|
1041 |
|
|
.rst (rst),
|
1042 |
|
|
.spr_access_i (1'b1), // Templated
|
1043 |
|
|
.spr_we_i (spr_we), // Templated
|
1044 |
|
|
.spr_addr_i (spr_addr), // Templated
|
1045 |
|
|
.spr_dat_i (spr_write_dat)); // Templated
|
1046 |
|
|
|
1047 |
|
|
assign except_ticktimer_nonsrmasked = spr_ttmr[28] &
|
1048 |
|
|
(!op_mtspr & !(spr_esr[`OR1K_SPR_SR_TEE] & execute_done)) &
|
1049 |
|
|
// Stops back-to-back branch addresses to
|
1050 |
|
|
// fetch stage.
|
1051 |
|
|
!ctrl_branch_occur &
|
1052 |
|
|
// Stops issues with PC when branching
|
1053 |
|
|
!execute_delay_slot;
|
1054 |
|
|
|
1055 |
|
|
assign except_ticktimer = except_ticktimer_nonsrmasked &
|
1056 |
|
|
spr_sr[`OR1K_SPR_SR_TEE] & !doing_rfe;
|
1057 |
|
|
end // if (FEATURE_TIMER!="NONE")
|
1058 |
|
|
else begin
|
1059 |
|
|
assign except_ticktimer_nonsrmasked = 0;
|
1060 |
|
|
assign except_ticktimer = 0;
|
1061 |
|
|
assign spr_ttmr = 0;
|
1062 |
|
|
assign spr_ttcr = 0;
|
1063 |
|
|
assign spr_access_ack[10] = 0;
|
1064 |
|
|
assign spr_internal_read_dat[10] = 0;
|
1065 |
|
|
end // else: !if(FEATURE_TIMER!="NONE")
|
1066 |
|
|
endgenerate
|
1067 |
|
|
|
1068 |
|
|
/* SPR access control - allow accesses from either the instructions or from
|
1069 |
|
|
the debug interface */
|
1070 |
|
|
assign spr_read_access = (op_mfspr | (du_access & !du_we_i));
|
1071 |
|
|
assign spr_write_access = ((execute_done & op_mtspr) | (du_access & du_we_i));
|
1072 |
|
|
|
1073 |
|
|
assign spr_write_dat = du_access ? du_dat_i : b;
|
1074 |
|
|
assign spr_we = spr_write_access & spr_group_present;
|
1075 |
|
|
assign spr_read = spr_read_access & spr_group_present;
|
1076 |
|
|
|
1077 |
|
|
/* A bus out to other units that live outside of the control unit */
|
1078 |
|
|
assign spr_bus_addr_o = spr_addr;
|
1079 |
|
|
assign spr_bus_we_o = spr_write_access & spr_group_present & spr_bus_access;
|
1080 |
|
|
assign spr_bus_stb_o = (spr_read_access | spr_write_access) &
|
1081 |
|
|
spr_group_present & spr_bus_access;
|
1082 |
|
|
assign spr_bus_dat_o = spr_write_dat;
|
1083 |
|
|
|
1084 |
|
|
/* Is the SPR in the design? */
|
1085 |
|
|
assign spr_group_present = (// System group
|
1086 |
|
|
(spr_addr[15:11]==5'h00) ||
|
1087 |
|
|
// DMMU
|
1088 |
|
|
(spr_addr[15:11]==5'h01 &&
|
1089 |
|
|
FEATURE_DMMU!="NONE") ||
|
1090 |
|
|
// IMMU
|
1091 |
|
|
(spr_addr[15:11]==5'h02 &&
|
1092 |
|
|
FEATURE_IMMU!="NONE") ||
|
1093 |
|
|
// Data cache
|
1094 |
|
|
(spr_addr[15:11]==5'h03 &&
|
1095 |
|
|
FEATURE_DATACACHE!="NONE") ||
|
1096 |
|
|
// Instruction cache
|
1097 |
|
|
(spr_addr[15:11]==5'h04 &&
|
1098 |
|
|
FEATURE_INSTRUCTIONCACHE!= "NONE") ||
|
1099 |
|
|
// MAC unit
|
1100 |
|
|
(spr_addr[15:11]==5'h05 &&
|
1101 |
|
|
FEATURE_MAC!="NONE") ||
|
1102 |
|
|
// Debug unit
|
1103 |
|
|
(spr_addr[15:11]==5'h06 &&
|
1104 |
|
|
FEATURE_DEBUGUNIT!="NONE") ||
|
1105 |
|
|
// Performance counters
|
1106 |
|
|
(spr_addr[15:11]==5'h07 &&
|
1107 |
|
|
FEATURE_PERFCOUNTERS!="NONE") ||
|
1108 |
|
|
// Power Management
|
1109 |
|
|
(spr_addr[15:11]==5'h08 &&
|
1110 |
|
|
FEATURE_PMU!="NONE") ||
|
1111 |
|
|
// PIC
|
1112 |
|
|
(spr_addr[15:11]==5'h09 &&
|
1113 |
|
|
FEATURE_PIC!="NONE") ||
|
1114 |
|
|
// Tick timer
|
1115 |
|
|
(spr_addr[15:11]==5'h0a &&
|
1116 |
|
|
FEATURE_TIMER!="NONE") ||
|
1117 |
|
|
// FPU
|
1118 |
|
|
(spr_addr[15:11]==5'h0b &&
|
1119 |
|
|
FEATURE_FPU!="NONE")
|
1120 |
|
|
);
|
1121 |
|
|
|
1122 |
|
|
/* Generate a SPR group signal - generate invalid if the group is not
|
1123 |
|
|
present in the design */
|
1124 |
|
|
assign spr_group = (spr_group_present) ? spr_addr[14:11] : 4'd12;
|
1125 |
|
|
|
1126 |
|
|
/* Default group when a selected one is not present - it reads as zero */
|
1127 |
|
|
assign spr_internal_read_dat[12] = 0;
|
1128 |
|
|
|
1129 |
|
|
/* Is a SPR bus access needed, or is the requested SPR in this file? */
|
1130 |
|
|
assign spr_bus_access = /* Any of the units we don't have in this file */
|
1131 |
|
|
/* System group */
|
1132 |
|
|
!(spr_addr[15:11]==5'h00 ||
|
1133 |
|
|
/* Debug Group */
|
1134 |
|
|
spr_addr[15:11]==5'h06 ||
|
1135 |
|
|
/* PIC Group */
|
1136 |
|
|
spr_addr[15:11]==5'h09 ||
|
1137 |
|
|
/* Tick Group */
|
1138 |
|
|
spr_addr[15:11]==5'h0a);
|
1139 |
|
|
|
1140 |
|
|
assign stepping_o = stepping;
|
1141 |
|
|
|
1142 |
|
|
generate
|
1143 |
|
|
if (FEATURE_DEBUGUNIT!="NONE") begin : du
|
1144 |
|
|
|
1145 |
|
|
reg [OPTION_OPERAND_WIDTH-1:0] du_read_dat;
|
1146 |
|
|
|
1147 |
|
|
reg du_ack;
|
1148 |
|
|
reg du_stall_r;
|
1149 |
|
|
reg [1:0] pstep_r;
|
1150 |
|
|
reg [1:0] branch_step;
|
1151 |
|
|
reg stepped_into_exception;
|
1152 |
|
|
reg stepped_into_rfe;
|
1153 |
|
|
|
1154 |
|
|
assign du_access = du_stb_i;
|
1155 |
|
|
|
1156 |
|
|
// Generate ack back to the debug interface bus
|
1157 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
1158 |
|
|
if (rst)
|
1159 |
|
|
du_ack <= 0;
|
1160 |
|
|
else if (du_ack)
|
1161 |
|
|
du_ack <= 0;
|
1162 |
|
|
else if (du_stb_i) begin
|
1163 |
|
|
if (!spr_group_present)
|
1164 |
|
|
/* Unit doesn't exist, ACK to clear the access, nothing done */
|
1165 |
|
|
du_ack <= 1;
|
1166 |
|
|
else if (spr_access_ack[spr_group])
|
1167 |
|
|
/* actual access occurred */
|
1168 |
|
|
du_ack <= 1;
|
1169 |
|
|
end
|
1170 |
|
|
|
1171 |
|
|
assign du_ack_o = du_ack;
|
1172 |
|
|
|
1173 |
|
|
/* Data back to the debug bus */
|
1174 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
1175 |
|
|
if (rst)
|
1176 |
|
|
du_read_dat <= 0;
|
1177 |
|
|
else if (spr_access_ack[spr_group]) begin
|
1178 |
|
|
du_read_dat <= spr_internal_read_dat[spr_group];
|
1179 |
|
|
end
|
1180 |
|
|
|
1181 |
|
|
assign du_dat_o = du_read_dat;
|
1182 |
|
|
/* TODO: check into only letting stall go high when we've gracefully
|
1183 |
|
|
completed the instruction currently in the ctrl stage.
|
1184 |
|
|
Why? Potentially an instruction like l.mfspr from an external unit
|
1185 |
|
|
hasn't completed fully, gets interrupted, and it's assumed it's
|
1186 |
|
|
completed, but actually hasn't. */
|
1187 |
|
|
assign cpu_stall = du_stall_i | du_restart_from_stall;
|
1188 |
|
|
|
1189 |
|
|
/* goes out to the debug interface and comes back 1 cycle later
|
1190 |
|
|
via du_stall_i */
|
1191 |
|
|
assign du_stall_o = (stepping & execute_done)|
|
1192 |
|
|
(stall_on_trap & execute_done & except_trap_i);
|
1193 |
|
|
|
1194 |
|
|
/* Pulse to indicate we're restarting after a stall */
|
1195 |
|
|
assign du_restart_from_stall = du_stall_r & !du_stall_i;
|
1196 |
|
|
|
1197 |
|
|
/* NPC debug control logic */
|
1198 |
|
|
assign du_npc_write = (du_we_i && du_addr_i==`OR1K_SPR_NPC_ADDR &&
|
1199 |
|
|
du_ack_o);
|
1200 |
|
|
|
1201 |
|
|
/* Pick the traps-cause-stall bit out of the DSR */
|
1202 |
|
|
assign stall_on_trap = spr_dsr[`OR1K_SPR_DSR_TE];
|
1203 |
|
|
|
1204 |
|
|
/* record if NPC was written while we were stalled.
|
1205 |
|
|
If so, we will use this value for restarting */
|
1206 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
1207 |
|
|
if (rst)
|
1208 |
|
|
du_npc_written <= 0;
|
1209 |
|
|
else if (du_restart_from_stall)
|
1210 |
|
|
du_npc_written <= 0;
|
1211 |
|
|
else if (du_npc_write)
|
1212 |
|
|
du_npc_written <= 1;
|
1213 |
|
|
|
1214 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
1215 |
|
|
if (rst)
|
1216 |
|
|
du_spr_npc <= 0;
|
1217 |
|
|
else if (du_npc_write)
|
1218 |
|
|
du_spr_npc <= du_dat_i;
|
1219 |
|
|
|
1220 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
1221 |
|
|
if (rst)
|
1222 |
|
|
stepped_into_exception <= 0;
|
1223 |
|
|
else if (du_restart_from_stall)
|
1224 |
|
|
stepped_into_exception <= 0;
|
1225 |
|
|
else if (stepping & execute_done)
|
1226 |
|
|
stepped_into_exception <= exception;
|
1227 |
|
|
|
1228 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
1229 |
|
|
if (rst)
|
1230 |
|
|
stepped_into_rfe <= 0;
|
1231 |
|
|
else if (du_restart_from_stall)
|
1232 |
|
|
stepped_into_rfe <= 0;
|
1233 |
|
|
else if (stepping & execute_done)
|
1234 |
|
|
stepped_into_rfe <= op_rfe;
|
1235 |
|
|
|
1236 |
|
|
assign du_restart_pc_o = du_npc_written ? du_spr_npc :
|
1237 |
|
|
stepped_into_rfe ? spr_epcr :
|
1238 |
|
|
stepped_into_delay_slot ?
|
1239 |
|
|
last_branch_target_pc : spr_npc;
|
1240 |
|
|
|
1241 |
|
|
assign du_restart_o = du_restart_from_stall;
|
1242 |
|
|
|
1243 |
|
|
/* Indicate when we're stepping */
|
1244 |
|
|
assign stepping = spr_dmr1[`OR1K_SPR_DMR1_ST] &
|
1245 |
|
|
spr_dsr[`OR1K_SPR_DSR_TE];
|
1246 |
|
|
|
1247 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
1248 |
|
|
if (rst)
|
1249 |
|
|
pstep_r <= 0;
|
1250 |
|
|
else if (du_restart_from_stall & stepping)
|
1251 |
|
|
pstep_r <= 2'd1;
|
1252 |
|
|
else if ((pstep[0] & next_fetch_done_i) |
|
1253 |
|
|
/* decode is always single cycle */
|
1254 |
|
|
(pstep[1] & execute_done))
|
1255 |
|
|
pstep_r <= {pstep_r[0],1'b0};
|
1256 |
|
|
|
1257 |
|
|
assign pstep = pstep_r;
|
1258 |
|
|
|
1259 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
1260 |
|
|
if (rst)
|
1261 |
|
|
branch_step <= 0;
|
1262 |
|
|
else if (stepping & pstep[1])
|
1263 |
|
|
branch_step <= {branch_step[0], ctrl_branch_occur};
|
1264 |
|
|
else if (!stepping & execute_done)
|
1265 |
|
|
branch_step <= {branch_step[0], execute_delay_slot};
|
1266 |
|
|
|
1267 |
|
|
assign stepped_into_delay_slot = branch_step[1];
|
1268 |
|
|
|
1269 |
|
|
/* Signals for waveform debuging */
|
1270 |
|
|
wire [31:0] spr_read_data_group_0;
|
1271 |
|
|
assign spr_read_data_group_0 = spr_internal_read_dat[0];
|
1272 |
|
|
wire [31:0] spr_read_data_group_1;
|
1273 |
|
|
assign spr_read_data_group_1 = spr_internal_read_dat[1];
|
1274 |
|
|
wire [31:0] spr_read_data_group_2;
|
1275 |
|
|
assign spr_read_data_group_2 = spr_internal_read_dat[2];
|
1276 |
|
|
wire [31:0] spr_read_data_group_3;
|
1277 |
|
|
assign spr_read_data_group_3 = spr_internal_read_dat[3];
|
1278 |
|
|
wire [31:0] spr_read_data_group_4;
|
1279 |
|
|
assign spr_read_data_group_4 = spr_internal_read_dat[4];
|
1280 |
|
|
wire [31:0] spr_read_data_group_5;
|
1281 |
|
|
assign spr_read_data_group_5 = spr_internal_read_dat[5];
|
1282 |
|
|
wire [31:0] spr_read_data_group_6;
|
1283 |
|
|
assign spr_read_data_group_6 = spr_internal_read_dat[6];
|
1284 |
|
|
wire [31:0] spr_read_data_group_7;
|
1285 |
|
|
assign spr_read_data_group_7 = spr_internal_read_dat[7];
|
1286 |
|
|
wire [31:0] spr_read_data_group_8;
|
1287 |
|
|
assign spr_read_data_group_8 = spr_internal_read_dat[8];
|
1288 |
|
|
wire [31:0] spr_read_data_group_9;
|
1289 |
|
|
assign spr_read_data_group_9 = spr_internal_read_dat[9];
|
1290 |
|
|
|
1291 |
|
|
|
1292 |
|
|
/* always single cycle access */
|
1293 |
|
|
assign spr_access_ack[6] = 1;
|
1294 |
|
|
assign spr_internal_read_dat[6] = (spr_addr==`OR1K_SPR_DMR1_ADDR) ?
|
1295 |
|
|
spr_dmr1 :
|
1296 |
|
|
(spr_addr==`OR1K_SPR_DMR2_ADDR) ?
|
1297 |
|
|
spr_dmr2 :
|
1298 |
|
|
(spr_addr==`OR1K_SPR_DSR_ADDR) ?
|
1299 |
|
|
spr_dsr :
|
1300 |
|
|
(spr_addr==`OR1K_SPR_DRR_ADDR) ?
|
1301 |
|
|
spr_drr : 0;
|
1302 |
|
|
|
1303 |
|
|
/* Put the incoming stall signal through a register to detect FE */
|
1304 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
1305 |
|
|
if (rst)
|
1306 |
|
|
du_stall_r <= 0;
|
1307 |
|
|
else
|
1308 |
|
|
du_stall_r <= du_stall_i;
|
1309 |
|
|
|
1310 |
|
|
/* DMR1 */
|
1311 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
1312 |
|
|
if (rst)
|
1313 |
|
|
spr_dmr1 <= 0;
|
1314 |
|
|
else if (spr_we && spr_addr==`OR1K_SPR_DMR1_ADDR)
|
1315 |
|
|
spr_dmr1[23:0] <= spr_write_dat[23:0];
|
1316 |
|
|
|
1317 |
|
|
/* DMR2 */
|
1318 |
|
|
always @(posedge clk)
|
1319 |
|
|
spr_dmr2 <= 0;
|
1320 |
|
|
|
1321 |
|
|
/* DSR */
|
1322 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
1323 |
|
|
if (rst)
|
1324 |
|
|
spr_dsr <= 0;
|
1325 |
|
|
else if (spr_we && spr_addr==`OR1K_SPR_DSR_ADDR)
|
1326 |
|
|
spr_dsr[13:0] <= spr_write_dat[13:0];
|
1327 |
|
|
|
1328 |
|
|
/* DRR */
|
1329 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
1330 |
|
|
if (rst)
|
1331 |
|
|
spr_drr <= 0;
|
1332 |
|
|
else if (spr_we && spr_addr==`OR1K_SPR_DRR_ADDR)
|
1333 |
|
|
spr_drr[13:0] <= spr_write_dat[13:0];
|
1334 |
|
|
else if (stall_on_trap & execute_done & except_trap_i)
|
1335 |
|
|
spr_drr[`OR1K_SPR_DRR_TE] <= 1;
|
1336 |
|
|
|
1337 |
|
|
end // block: du
|
1338 |
|
|
else
|
1339 |
|
|
begin : no_du
|
1340 |
|
|
assign du_access = 0;
|
1341 |
|
|
assign cpu_stall = 0;
|
1342 |
|
|
assign du_stall_o = 0;
|
1343 |
|
|
assign du_ack_o = 0;
|
1344 |
|
|
assign du_restart_o = 0;
|
1345 |
|
|
assign du_restart_pc_o = 0;
|
1346 |
|
|
assign stepping = 0;
|
1347 |
|
|
assign du_npc_write = 0;
|
1348 |
|
|
assign stepped_into_delay_slot = 0;
|
1349 |
|
|
assign du_dat_o = 0;
|
1350 |
|
|
assign du_restart_from_stall = 0;
|
1351 |
|
|
assign spr_access_ack[6] = 0;
|
1352 |
|
|
|
1353 |
|
|
always @(posedge clk)
|
1354 |
|
|
begin
|
1355 |
|
|
spr_dmr1 <= 0;
|
1356 |
|
|
spr_dmr2 <= 0;
|
1357 |
|
|
spr_dsr <= 0;
|
1358 |
|
|
spr_drr <= 0;
|
1359 |
|
|
du_npc_written <= 0;
|
1360 |
|
|
end
|
1361 |
|
|
end
|
1362 |
|
|
endgenerate
|
1363 |
|
|
|
1364 |
|
|
/* Controls to generate ACKs from units that are external to this module */
|
1365 |
|
|
generate
|
1366 |
|
|
if (FEATURE_DMMU!="NONE") begin : dmmu_ctrl
|
1367 |
|
|
assign spr_access_ack[1] = spr_bus_ack_dmmu_i;
|
1368 |
|
|
assign spr_internal_read_dat[1] = spr_bus_dat_dmmu_i;
|
1369 |
|
|
end
|
1370 |
|
|
else begin
|
1371 |
|
|
assign spr_access_ack[1] = 0;
|
1372 |
|
|
assign spr_internal_read_dat[1] = 0;
|
1373 |
|
|
end
|
1374 |
|
|
endgenerate
|
1375 |
|
|
|
1376 |
|
|
generate
|
1377 |
|
|
if (FEATURE_IMMU!="NONE") begin : immu_ctrl
|
1378 |
|
|
assign spr_access_ack[2] = spr_bus_ack_immu_i;
|
1379 |
|
|
assign spr_internal_read_dat[2] = spr_bus_dat_immu_i;
|
1380 |
|
|
end
|
1381 |
|
|
else begin
|
1382 |
|
|
assign spr_access_ack[2] = 0;
|
1383 |
|
|
assign spr_internal_read_dat[2] = 0;
|
1384 |
|
|
end
|
1385 |
|
|
endgenerate
|
1386 |
|
|
|
1387 |
|
|
generate
|
1388 |
|
|
if (FEATURE_DATACACHE!="NONE") begin : datacache_ctrl
|
1389 |
|
|
assign spr_access_ack[3] = spr_bus_ack_dc_i;
|
1390 |
|
|
assign spr_internal_read_dat[3] = spr_bus_dat_dc_i;
|
1391 |
|
|
end
|
1392 |
|
|
else begin
|
1393 |
|
|
assign spr_access_ack[3] = 0;
|
1394 |
|
|
assign spr_internal_read_dat[3] = 0;
|
1395 |
|
|
end
|
1396 |
|
|
endgenerate
|
1397 |
|
|
|
1398 |
|
|
generate
|
1399 |
|
|
if (FEATURE_INSTRUCTIONCACHE!="NONE") begin : instructioncache_ctrl
|
1400 |
|
|
assign spr_access_ack[4] = spr_bus_ack_ic_i;
|
1401 |
|
|
assign spr_internal_read_dat[4] = spr_bus_dat_ic_i;
|
1402 |
|
|
end
|
1403 |
|
|
else begin
|
1404 |
|
|
assign spr_access_ack[4] = 0;
|
1405 |
|
|
assign spr_internal_read_dat[4] = 0;
|
1406 |
|
|
end
|
1407 |
|
|
endgenerate
|
1408 |
|
|
|
1409 |
|
|
generate
|
1410 |
|
|
if (FEATURE_MAC!="NONE") begin : mac_ctrl
|
1411 |
|
|
assign spr_access_ack[5] = spr_bus_ack_mac_i;
|
1412 |
|
|
assign spr_internal_read_dat[5] = spr_bus_dat_mac_i;
|
1413 |
|
|
end
|
1414 |
|
|
else begin
|
1415 |
|
|
assign spr_access_ack[5] = 0;
|
1416 |
|
|
assign spr_internal_read_dat[5] = 0;
|
1417 |
|
|
end
|
1418 |
|
|
endgenerate
|
1419 |
|
|
|
1420 |
|
|
generate
|
1421 |
|
|
if (FEATURE_PERFCOUNTERS!="NONE") begin : perfcounters_ctrl
|
1422 |
|
|
assign spr_access_ack[7] = spr_bus_ack_pcu_i;
|
1423 |
|
|
assign spr_internal_read_dat[7] = spr_bus_dat_pcu_i;
|
1424 |
|
|
end
|
1425 |
|
|
else begin
|
1426 |
|
|
assign spr_access_ack[7] = 0;
|
1427 |
|
|
assign spr_internal_read_dat[7] = 0;
|
1428 |
|
|
end
|
1429 |
|
|
endgenerate
|
1430 |
|
|
|
1431 |
|
|
generate
|
1432 |
|
|
if (FEATURE_PMU!="NONE") begin : pmu_ctrl
|
1433 |
|
|
assign spr_access_ack[8] = spr_bus_ack_pmu_i;
|
1434 |
|
|
assign spr_internal_read_dat[8] = spr_bus_dat_pcu_i;
|
1435 |
|
|
end
|
1436 |
|
|
else begin
|
1437 |
|
|
assign spr_access_ack[8] = 0;
|
1438 |
|
|
assign spr_internal_read_dat[8] = 0;
|
1439 |
|
|
end
|
1440 |
|
|
endgenerate
|
1441 |
|
|
|
1442 |
|
|
generate
|
1443 |
|
|
if (FEATURE_FPU!="NONE") begin : fpu_ctrl
|
1444 |
|
|
assign spr_access_ack[11] = spr_bus_ack_fpu_i;
|
1445 |
|
|
assign spr_internal_read_dat[11] = spr_bus_dat_fpu_i;
|
1446 |
|
|
end
|
1447 |
|
|
else begin
|
1448 |
|
|
assign spr_access_ack[11] = 0;
|
1449 |
|
|
assign spr_internal_read_dat[11] = 0;
|
1450 |
|
|
end
|
1451 |
|
|
endgenerate
|
1452 |
|
|
|
1453 |
|
|
endmodule // mor1kx_ctrl_espresso
|