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alirezamon |
/* ****************************************************************************
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This Source Code Form is subject to the terms of the
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Open Hardware Description License, v. 1.0. If a copy
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of the OHDL was not distributed with this file, You
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can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
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Description: mor1kx decode unit
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Completely combinatorial.
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Outputs:
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- ALU operation
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- indication of other type of op - LSU/SPR
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- immediates
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- register file addresses
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- exception decodes: illegal, system call
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Copyright (C) 2012 Julius Baxter <juliusbaxter@gmail.com>
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Copyright (C) 2013 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
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***************************************************************************** */
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`include "mor1kx-defines.v"
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module mor1kx_decode
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#(
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parameter OPTION_OPERAND_WIDTH = 32,
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parameter OPTION_RESET_PC = {{(OPTION_OPERAND_WIDTH-13){1'b0}},
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`OR1K_RESET_VECTOR,8'd0},
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parameter OPTION_RF_ADDR_WIDTH = 5,
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parameter FEATURE_SYSCALL = "ENABLED",
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parameter FEATURE_TRAP = "ENABLED",
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parameter FEATURE_RANGE = "ENABLED",
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parameter FEATURE_MAC = "NONE",
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parameter FEATURE_MULTIPLIER = "PARALLEL",
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parameter FEATURE_DIVIDER = "NONE",
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parameter FEATURE_ADDC = "NONE",
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parameter FEATURE_SRA = "ENABLED",
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parameter FEATURE_ROR = "NONE",
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parameter FEATURE_EXT = "NONE",
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parameter FEATURE_CMOV = "NONE",
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parameter FEATURE_FFL1 = "NONE",
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parameter FEATURE_ATOMIC = "ENABLED",
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parameter FEATURE_MSYNC = "ENABLED",
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parameter FEATURE_PSYNC = "NONE",
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parameter FEATURE_CSYNC = "NONE",
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parameter FEATURE_FPU = "NONE", // ENABLED|NONE
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parameter FEATURE_CUST1 = "NONE",
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parameter FEATURE_CUST2 = "NONE",
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parameter FEATURE_CUST3 = "NONE",
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parameter FEATURE_CUST4 = "NONE",
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parameter FEATURE_CUST5 = "NONE",
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parameter FEATURE_CUST6 = "NONE",
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parameter FEATURE_CUST7 = "NONE",
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parameter FEATURE_CUST8 = "NONE"
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)
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(
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input clk,
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input rst,
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// input from fetch stage
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input [`OR1K_INSN_WIDTH-1:0] decode_insn_i,
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// ALU opcodes
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output [`OR1K_ALU_OPC_WIDTH-1:0] decode_opc_alu_o,
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output [`OR1K_ALU_OPC_WIDTH-1:0] decode_opc_alu_secondary_o,
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output [`OR1K_IMM_WIDTH-1:0] decode_imm16_o,
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output [OPTION_OPERAND_WIDTH-1:0] decode_immediate_o,
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output decode_immediate_sel_o,
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// Upper 10 bits of immediate for jumps and branches
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output [9:0] decode_immjbr_upper_o,
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// GPR numbers
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output [OPTION_RF_ADDR_WIDTH-1:0] decode_rfd_adr_o,
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output [OPTION_RF_ADDR_WIDTH-1:0] decode_rfa_adr_o,
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output [OPTION_RF_ADDR_WIDTH-1:0] decode_rfb_adr_o,
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output decode_rf_wb_o,
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output decode_op_jbr_o,
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output decode_op_jr_o,
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output decode_op_jal_o,
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output decode_op_bf_o,
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output decode_op_bnf_o,
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output decode_op_brcond_o,
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output decode_op_branch_o,
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output decode_op_alu_o,
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output decode_op_lsu_load_o,
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output decode_op_lsu_store_o,
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output decode_op_lsu_atomic_o,
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output reg [1:0] decode_lsu_length_o,
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output decode_lsu_zext_o,
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output decode_op_mfspr_o,
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output decode_op_mtspr_o,
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output decode_op_rfe_o,
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output decode_op_setflag_o,
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output decode_op_add_o,
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output decode_op_mul_o,
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output decode_op_mul_signed_o,
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output decode_op_mul_unsigned_o,
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output decode_op_div_o,
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output decode_op_div_signed_o,
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output decode_op_div_unsigned_o,
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output decode_op_shift_o,
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output decode_op_ffl1_o,
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output decode_op_movhi_o,
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output decode_op_ext_o,
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// Sync operations
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output decode_op_msync_o,
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output [`OR1K_FPUOP_WIDTH-1:0] decode_op_fpu_o,
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// Adder control logic
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output decode_adder_do_sub_o,
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output decode_adder_do_carry_o,
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// exception output -
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output reg decode_except_illegal_o,
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output decode_except_syscall_o,
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output decode_except_trap_o,
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output [`OR1K_OPCODE_WIDTH-1:0] decode_opc_insn_o
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);
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wire [`OR1K_OPCODE_WIDTH-1:0] opc_insn;
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wire [`OR1K_ALU_OPC_WIDTH-1:0] opc_alu;
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wire [OPTION_OPERAND_WIDTH-1:0] imm_sext;
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wire imm_sext_sel;
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wire [OPTION_OPERAND_WIDTH-1:0] imm_zext;
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wire imm_zext_sel;
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wire [OPTION_OPERAND_WIDTH-1:0] imm_high;
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wire imm_high_sel;
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wire decode_except_ibus_align;
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// Insn opcode
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assign opc_insn = decode_insn_i[`OR1K_OPCODE_SELECT];
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assign decode_opc_insn_o = opc_insn;
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// load opcodes are 6'b10_0000 to 6'b10_0110, 0 to 6, so check for 7 and up
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assign decode_op_lsu_load_o = (decode_insn_i[31:30] == 2'b10) &
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!(&decode_insn_i[28:26]) &
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!decode_insn_i[29] ||
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((opc_insn == `OR1K_OPCODE_LWA) &
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(FEATURE_ATOMIC!="NONE"));
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// Detect when instruction is store
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assign decode_op_lsu_store_o = (opc_insn == `OR1K_OPCODE_SW) ||
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(opc_insn == `OR1K_OPCODE_SB) ||
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(opc_insn == `OR1K_OPCODE_SH) ||
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((opc_insn == `OR1K_OPCODE_SWA) &
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(FEATURE_ATOMIC!="NONE"));
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assign decode_op_lsu_atomic_o = ((opc_insn == `OR1K_OPCODE_LWA) ||
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(opc_insn == `OR1K_OPCODE_SWA)) &
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(FEATURE_ATOMIC!="NONE");
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// Decode length of load/store operation
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always @(*)
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case (opc_insn)
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`OR1K_OPCODE_SB,
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`OR1K_OPCODE_LBZ,
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`OR1K_OPCODE_LBS:
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decode_lsu_length_o = 2'b00;
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`OR1K_OPCODE_SH,
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`OR1K_OPCODE_LHZ,
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`OR1K_OPCODE_LHS:
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decode_lsu_length_o = 2'b01;
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`OR1K_OPCODE_SW,
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`OR1K_OPCODE_SWA,
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`OR1K_OPCODE_LWZ,
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`OR1K_OPCODE_LWS,
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`OR1K_OPCODE_LWA:
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decode_lsu_length_o = 2'b10;
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default:
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decode_lsu_length_o = 2'b10;
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endcase
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assign decode_lsu_zext_o = opc_insn[0];
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assign decode_op_msync_o = FEATURE_MSYNC!="NONE" &&
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opc_insn == `OR1K_OPCODE_SYSTRAPSYNC &&
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decode_insn_i[`OR1K_SYSTRAPSYNC_OPC_SELECT] ==
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`OR1K_SYSTRAPSYNC_OPC_MSYNC;
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assign decode_op_mtspr_o = opc_insn == `OR1K_OPCODE_MTSPR;
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// Detect when setflag instruction
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assign decode_op_setflag_o = opc_insn == `OR1K_OPCODE_SF ||
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opc_insn == `OR1K_OPCODE_SFIMM;
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assign decode_op_alu_o = opc_insn == `OR1K_OPCODE_ALU ||
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opc_insn == `OR1K_OPCODE_ORI ||
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opc_insn == `OR1K_OPCODE_ANDI ||
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opc_insn == `OR1K_OPCODE_XORI;
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// Bottom 4 opcodes branch against an immediate
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assign decode_op_jbr_o = opc_insn < `OR1K_OPCODE_NOP;
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assign decode_op_jr_o = opc_insn == `OR1K_OPCODE_JR |
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opc_insn == `OR1K_OPCODE_JALR;
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assign decode_op_jal_o = opc_insn == `OR1K_OPCODE_JALR |
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opc_insn == `OR1K_OPCODE_JAL;
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assign decode_op_bf_o = opc_insn == `OR1K_OPCODE_BF;
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assign decode_op_bnf_o = opc_insn == `OR1K_OPCODE_BNF;
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assign decode_op_brcond_o = decode_op_bf_o | decode_op_bnf_o;
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// All branch instructions combined
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assign decode_op_branch_o = decode_op_jbr_o |
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decode_op_jr_o |
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decode_op_jal_o;
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assign decode_op_mfspr_o = opc_insn == `OR1K_OPCODE_MFSPR;
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assign decode_op_rfe_o = opc_insn == `OR1K_OPCODE_RFE;
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assign decode_op_add_o = (opc_insn == `OR1K_OPCODE_ALU &&
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(opc_alu == `OR1K_ALU_OPC_ADDC ||
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opc_alu == `OR1K_ALU_OPC_ADD ||
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opc_alu == `OR1K_ALU_OPC_SUB)) ||
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opc_insn == `OR1K_OPCODE_ADDIC ||
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opc_insn == `OR1K_OPCODE_ADDI;
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assign decode_op_mul_signed_o = (opc_insn == `OR1K_OPCODE_ALU &&
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opc_alu == `OR1K_ALU_OPC_MUL) ||
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opc_insn == `OR1K_OPCODE_MULI;
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assign decode_op_mul_unsigned_o = opc_insn == `OR1K_OPCODE_ALU &&
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opc_alu == `OR1K_ALU_OPC_MULU;
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assign decode_op_mul_o = decode_op_mul_signed_o | decode_op_mul_unsigned_o;
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assign decode_op_div_signed_o = opc_insn == `OR1K_OPCODE_ALU &&
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opc_alu == `OR1K_ALU_OPC_DIV;
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assign decode_op_div_unsigned_o = opc_insn == `OR1K_OPCODE_ALU &&
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opc_alu == `OR1K_ALU_OPC_DIVU;
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assign decode_op_div_o = decode_op_div_signed_o | decode_op_div_unsigned_o;
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assign decode_op_shift_o = opc_insn == `OR1K_OPCODE_ALU &&
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opc_alu == `OR1K_ALU_OPC_SHRT ||
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opc_insn == `OR1K_OPCODE_SHRTI;
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/* check bit 9 to verify valid l.fl1/l.ff1 instruction */
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assign decode_op_ffl1_o = opc_insn == `OR1K_OPCODE_ALU &&
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(decode_insn_i[9:8] == 2'b00 || decode_insn_i[9:8] == 2'b01) &&
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opc_alu == `OR1K_ALU_OPC_FFL1;
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assign decode_op_movhi_o = opc_insn == `OR1K_OPCODE_MOVHI;
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assign decode_op_ext_o = opc_insn == `OR1K_OPCODE_ALU &&
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(opc_alu == `OR1K_ALU_OPC_EXTBH ||
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opc_alu == `OR1K_ALU_OPC_EXTW) &&
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(FEATURE_EXT!="NONE");
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// FPU related
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generate
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/* verilator lint_off WIDTH */
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if (FEATURE_FPU!="NONE") begin : fpu_decode_ena
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/* verilator lint_on WIDTH */
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// Only single precision FP-instructions are supported
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assign decode_op_fpu_o = { ((opc_insn == `OR1K_OPCODE_FPU) &
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~decode_insn_i[`OR1K_FPUOP_DOUBLE_BIT]),
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decode_insn_i[`OR1K_FPUOP_WIDTH-2:0] };
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end
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else begin : fpu_decode_none
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assign decode_op_fpu_o = {`OR1K_FPUOP_WIDTH{1'b0}};
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end
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endgenerate // FPU related
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// Which instructions cause writeback?
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assign decode_rf_wb_o = (opc_insn == `OR1K_OPCODE_JAL |
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opc_insn == `OR1K_OPCODE_MOVHI |
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opc_insn == `OR1K_OPCODE_JALR |
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opc_insn == `OR1K_OPCODE_LWA) |
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// All '10????' opcodes except l.sfxxi
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(decode_insn_i[31:30] == 2'b10 &
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!(opc_insn == `OR1K_OPCODE_SFIMM)) |
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// All '11????' opcodes except l.sfxx and l.mtspr and lf.sfxx.s
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(decode_insn_i[31:30] == 2'b11 &
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!(opc_insn == `OR1K_OPCODE_SF |
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decode_op_mtspr_o | decode_op_lsu_store_o) &
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!(decode_op_fpu_o[`OR1K_FPUOP_WIDTH-1] & decode_insn_i[3]));
|
| 302 |
|
|
|
| 303 |
|
|
// Register file addresses
|
| 304 |
|
|
assign decode_rfa_adr_o = decode_insn_i[`OR1K_RA_SELECT];
|
| 305 |
|
|
assign decode_rfb_adr_o = decode_insn_i[`OR1K_RB_SELECT];
|
| 306 |
|
|
|
| 307 |
|
|
assign decode_rfd_adr_o = decode_op_jal_o ? 5'd9 :
|
| 308 |
|
|
decode_insn_i[`OR1K_RD_SELECT];
|
| 309 |
|
|
|
| 310 |
|
|
// Immediate in l.mtspr is broken up, reassemble
|
| 311 |
|
|
assign decode_imm16_o = (decode_op_mtspr_o | decode_op_lsu_store_o) ?
|
| 312 |
|
|
{decode_insn_i[25:21],decode_insn_i[10:0]} :
|
| 313 |
|
|
decode_insn_i[`OR1K_IMM_SELECT];
|
| 314 |
|
|
|
| 315 |
|
|
|
| 316 |
|
|
// Upper 10 bits for jump/branch instructions
|
| 317 |
|
|
assign decode_immjbr_upper_o = decode_insn_i[25:16];
|
| 318 |
|
|
|
| 319 |
|
|
assign imm_sext = {{16{decode_imm16_o[15]}}, decode_imm16_o[15:0]};
|
| 320 |
|
|
assign imm_sext_sel = ((opc_insn[5:4] == 2'b10) &
|
| 321 |
|
|
~(opc_insn == `OR1K_OPCODE_ORI) &
|
| 322 |
|
|
~(opc_insn == `OR1K_OPCODE_ANDI)) |
|
| 323 |
|
|
(opc_insn == `OR1K_OPCODE_SWA) |
|
| 324 |
|
|
(opc_insn == `OR1K_OPCODE_LWA) |
|
| 325 |
|
|
(opc_insn == `OR1K_OPCODE_SW) |
|
| 326 |
|
|
(opc_insn == `OR1K_OPCODE_SH) |
|
| 327 |
|
|
(opc_insn == `OR1K_OPCODE_SB);
|
| 328 |
|
|
|
| 329 |
|
|
assign imm_zext = {{16{1'b0}}, decode_imm16_o[15:0]};
|
| 330 |
|
|
assign imm_zext_sel = ((opc_insn[5:4] == 2'b10) &
|
| 331 |
|
|
((opc_insn == `OR1K_OPCODE_ORI) |
|
| 332 |
|
|
(opc_insn == `OR1K_OPCODE_ANDI))) |
|
| 333 |
|
|
(opc_insn == `OR1K_OPCODE_MTSPR);
|
| 334 |
|
|
|
| 335 |
|
|
assign imm_high = {decode_imm16_o, 16'd0};
|
| 336 |
|
|
assign imm_high_sel = decode_op_movhi_o;
|
| 337 |
|
|
|
| 338 |
|
|
assign decode_immediate_o = imm_sext_sel ? imm_sext :
|
| 339 |
|
|
imm_zext_sel ? imm_zext : imm_high;
|
| 340 |
|
|
|
| 341 |
|
|
assign decode_immediate_sel_o = imm_sext_sel | imm_zext_sel | imm_high_sel;
|
| 342 |
|
|
|
| 343 |
|
|
// ALU opcode
|
| 344 |
|
|
assign opc_alu = decode_insn_i[`OR1K_ALU_OPC_SELECT];
|
| 345 |
|
|
assign decode_opc_alu_o = opc_insn == `OR1K_OPCODE_ORI ? `OR1K_ALU_OPC_OR :
|
| 346 |
|
|
opc_insn == `OR1K_OPCODE_ANDI ? `OR1K_ALU_OPC_AND :
|
| 347 |
|
|
opc_insn == `OR1K_OPCODE_XORI ? `OR1K_ALU_OPC_XOR :
|
| 348 |
|
|
opc_alu;
|
| 349 |
|
|
|
| 350 |
|
|
assign decode_opc_alu_secondary_o = decode_op_setflag_o ?
|
| 351 |
|
|
decode_insn_i[`OR1K_COMP_OPC_SELECT]:
|
| 352 |
|
|
{1'b0,
|
| 353 |
|
|
decode_insn_i[`OR1K_ALU_OPC_SECONDARY_SELECT]};
|
| 354 |
|
|
|
| 355 |
|
|
assign decode_except_syscall_o = opc_insn == `OR1K_OPCODE_SYSTRAPSYNC &&
|
| 356 |
|
|
decode_insn_i[`OR1K_SYSTRAPSYNC_OPC_SELECT] ==
|
| 357 |
|
|
`OR1K_SYSTRAPSYNC_OPC_SYSCALL;
|
| 358 |
|
|
|
| 359 |
|
|
assign decode_except_trap_o = opc_insn == `OR1K_OPCODE_SYSTRAPSYNC &&
|
| 360 |
|
|
decode_insn_i[`OR1K_SYSTRAPSYNC_OPC_SELECT] ==
|
| 361 |
|
|
`OR1K_SYSTRAPSYNC_OPC_TRAP;
|
| 362 |
|
|
|
| 363 |
|
|
// Illegal instruction decode
|
| 364 |
|
|
always @*
|
| 365 |
|
|
case (opc_insn)
|
| 366 |
|
|
`OR1K_OPCODE_J,
|
| 367 |
|
|
`OR1K_OPCODE_JAL,
|
| 368 |
|
|
`OR1K_OPCODE_BNF,
|
| 369 |
|
|
`OR1K_OPCODE_BF,
|
| 370 |
|
|
`OR1K_OPCODE_MOVHI,
|
| 371 |
|
|
`OR1K_OPCODE_RFE,
|
| 372 |
|
|
`OR1K_OPCODE_JR,
|
| 373 |
|
|
`OR1K_OPCODE_JALR,
|
| 374 |
|
|
`OR1K_OPCODE_LWZ,
|
| 375 |
|
|
`OR1K_OPCODE_LWS,
|
| 376 |
|
|
`OR1K_OPCODE_LBZ,
|
| 377 |
|
|
`OR1K_OPCODE_LBS,
|
| 378 |
|
|
`OR1K_OPCODE_LHZ,
|
| 379 |
|
|
`OR1K_OPCODE_LHS,
|
| 380 |
|
|
`OR1K_OPCODE_ADDI,
|
| 381 |
|
|
`OR1K_OPCODE_ANDI,
|
| 382 |
|
|
`OR1K_OPCODE_ORI,
|
| 383 |
|
|
`OR1K_OPCODE_XORI,
|
| 384 |
|
|
`OR1K_OPCODE_MFSPR,
|
| 385 |
|
|
/*
|
| 386 |
|
|
`OR1K_OPCODE_SLLI,
|
| 387 |
|
|
`OR1K_OPCODE_SRLI,
|
| 388 |
|
|
`OR1K_OPCODE_SRAI,
|
| 389 |
|
|
`OR1K_OPCODE_RORI,
|
| 390 |
|
|
*/
|
| 391 |
|
|
`OR1K_OPCODE_SFIMM,
|
| 392 |
|
|
`OR1K_OPCODE_MTSPR,
|
| 393 |
|
|
`OR1K_OPCODE_SW,
|
| 394 |
|
|
`OR1K_OPCODE_SB,
|
| 395 |
|
|
`OR1K_OPCODE_SH,
|
| 396 |
|
|
/*
|
| 397 |
|
|
`OR1K_OPCODE_SFEQ,
|
| 398 |
|
|
`OR1K_OPCODE_SFNE,
|
| 399 |
|
|
`OR1K_OPCODE_SFGTU,
|
| 400 |
|
|
`OR1K_OPCODE_SFGEU,
|
| 401 |
|
|
`OR1K_OPCODE_SFLTU,
|
| 402 |
|
|
`OR1K_OPCODE_SFLEU,
|
| 403 |
|
|
`OR1K_OPCODE_SFGTS,
|
| 404 |
|
|
`OR1K_OPCODE_SFGES,
|
| 405 |
|
|
`OR1K_OPCODE_SFLTS,
|
| 406 |
|
|
`OR1K_OPCODE_SFLES,
|
| 407 |
|
|
*/
|
| 408 |
|
|
`OR1K_OPCODE_SF,
|
| 409 |
|
|
`OR1K_OPCODE_NOP:
|
| 410 |
|
|
decode_except_illegal_o = 1'b0;
|
| 411 |
|
|
|
| 412 |
|
|
`OR1K_OPCODE_SWA,
|
| 413 |
|
|
`OR1K_OPCODE_LWA:
|
| 414 |
|
|
decode_except_illegal_o = (FEATURE_ATOMIC=="NONE");
|
| 415 |
|
|
|
| 416 |
|
|
`OR1K_OPCODE_CUST1:
|
| 417 |
|
|
decode_except_illegal_o = (FEATURE_CUST1=="NONE");
|
| 418 |
|
|
`OR1K_OPCODE_CUST2:
|
| 419 |
|
|
decode_except_illegal_o = (FEATURE_CUST2=="NONE");
|
| 420 |
|
|
`OR1K_OPCODE_CUST3:
|
| 421 |
|
|
decode_except_illegal_o = (FEATURE_CUST3=="NONE");
|
| 422 |
|
|
`OR1K_OPCODE_CUST4:
|
| 423 |
|
|
decode_except_illegal_o = (FEATURE_CUST4=="NONE");
|
| 424 |
|
|
`OR1K_OPCODE_CUST5:
|
| 425 |
|
|
decode_except_illegal_o = (FEATURE_CUST5=="NONE");
|
| 426 |
|
|
`OR1K_OPCODE_CUST6:
|
| 427 |
|
|
decode_except_illegal_o = (FEATURE_CUST6=="NONE");
|
| 428 |
|
|
`OR1K_OPCODE_CUST7:
|
| 429 |
|
|
decode_except_illegal_o = (FEATURE_CUST7=="NONE");
|
| 430 |
|
|
`OR1K_OPCODE_CUST8:
|
| 431 |
|
|
decode_except_illegal_o = (FEATURE_CUST8=="NONE");
|
| 432 |
|
|
`OR1K_OPCODE_FPU:
|
| 433 |
|
|
decode_except_illegal_o = (FEATURE_FPU=="NONE") |
|
| 434 |
|
|
decode_insn_i[`OR1K_FPUOP_DOUBLE_BIT];
|
| 435 |
|
|
|
| 436 |
|
|
`OR1K_OPCODE_LD,
|
| 437 |
|
|
`OR1K_OPCODE_SD:
|
| 438 |
|
|
decode_except_illegal_o = !(OPTION_OPERAND_WIDTH==64);
|
| 439 |
|
|
|
| 440 |
|
|
`OR1K_OPCODE_ADDIC:
|
| 441 |
|
|
decode_except_illegal_o = (FEATURE_ADDC=="NONE");
|
| 442 |
|
|
|
| 443 |
|
|
//`OR1K_OPCODE_MACRC, // Same as movhi - check!
|
| 444 |
|
|
`OR1K_OPCODE_MACI,
|
| 445 |
|
|
`OR1K_OPCODE_MAC:
|
| 446 |
|
|
decode_except_illegal_o = (FEATURE_MAC=="NONE");
|
| 447 |
|
|
|
| 448 |
|
|
`OR1K_OPCODE_MULI:
|
| 449 |
|
|
decode_except_illegal_o = (FEATURE_MULTIPLIER=="NONE");
|
| 450 |
|
|
|
| 451 |
|
|
`OR1K_OPCODE_SHRTI:
|
| 452 |
|
|
case(decode_insn_i[`OR1K_ALU_OPC_SECONDARY_SELECT])
|
| 453 |
|
|
`OR1K_ALU_OPC_SECONDARY_SHRT_SLL,
|
| 454 |
|
|
`OR1K_ALU_OPC_SECONDARY_SHRT_SRL:
|
| 455 |
|
|
decode_except_illegal_o = 1'b0;
|
| 456 |
|
|
`OR1K_ALU_OPC_SECONDARY_SHRT_SRA:
|
| 457 |
|
|
decode_except_illegal_o = (FEATURE_SRA=="NONE");
|
| 458 |
|
|
|
| 459 |
|
|
`OR1K_ALU_OPC_SECONDARY_SHRT_ROR:
|
| 460 |
|
|
decode_except_illegal_o = (FEATURE_ROR=="NONE");
|
| 461 |
|
|
default:
|
| 462 |
|
|
decode_except_illegal_o = 1'b1;
|
| 463 |
|
|
endcase // case (decode_insn_i[`OR1K_ALU_OPC_SECONDARY_SELECT])
|
| 464 |
|
|
|
| 465 |
|
|
`OR1K_OPCODE_ALU:
|
| 466 |
|
|
case(decode_insn_i[`OR1K_ALU_OPC_SELECT])
|
| 467 |
|
|
`OR1K_ALU_OPC_ADD,
|
| 468 |
|
|
`OR1K_ALU_OPC_SUB,
|
| 469 |
|
|
`OR1K_ALU_OPC_OR,
|
| 470 |
|
|
`OR1K_ALU_OPC_XOR,
|
| 471 |
|
|
`OR1K_ALU_OPC_AND:
|
| 472 |
|
|
decode_except_illegal_o = 1'b0;
|
| 473 |
|
|
`OR1K_ALU_OPC_CMOV:
|
| 474 |
|
|
decode_except_illegal_o = (FEATURE_CMOV=="NONE");
|
| 475 |
|
|
`OR1K_ALU_OPC_FFL1:
|
| 476 |
|
|
decode_except_illegal_o = (FEATURE_FFL1=="NONE");
|
| 477 |
|
|
`OR1K_ALU_OPC_DIV,
|
| 478 |
|
|
`OR1K_ALU_OPC_DIVU:
|
| 479 |
|
|
decode_except_illegal_o = (FEATURE_DIVIDER=="NONE");
|
| 480 |
|
|
`OR1K_ALU_OPC_ADDC:
|
| 481 |
|
|
decode_except_illegal_o = (FEATURE_ADDC=="NONE");
|
| 482 |
|
|
`OR1K_ALU_OPC_MUL,
|
| 483 |
|
|
`OR1K_ALU_OPC_MULU:
|
| 484 |
|
|
decode_except_illegal_o = (FEATURE_MULTIPLIER=="NONE");
|
| 485 |
|
|
`OR1K_ALU_OPC_EXTBH,
|
| 486 |
|
|
`OR1K_ALU_OPC_EXTW:
|
| 487 |
|
|
decode_except_illegal_o = (FEATURE_EXT=="NONE");
|
| 488 |
|
|
`OR1K_ALU_OPC_SHRT:
|
| 489 |
|
|
case(decode_insn_i[`OR1K_ALU_OPC_SECONDARY_SELECT])
|
| 490 |
|
|
`OR1K_ALU_OPC_SECONDARY_SHRT_SLL,
|
| 491 |
|
|
`OR1K_ALU_OPC_SECONDARY_SHRT_SRL:
|
| 492 |
|
|
decode_except_illegal_o = 1'b0;
|
| 493 |
|
|
`OR1K_ALU_OPC_SECONDARY_SHRT_SRA:
|
| 494 |
|
|
decode_except_illegal_o = (FEATURE_SRA=="NONE");
|
| 495 |
|
|
`OR1K_ALU_OPC_SECONDARY_SHRT_ROR:
|
| 496 |
|
|
decode_except_illegal_o = (FEATURE_ROR=="NONE");
|
| 497 |
|
|
default:
|
| 498 |
|
|
decode_except_illegal_o = 1'b1;
|
| 499 |
|
|
endcase // case (decode_insn_i[`OR1K_ALU_OPC_SECONDARY_SELECT])
|
| 500 |
|
|
default:
|
| 501 |
|
|
decode_except_illegal_o = 1'b1;
|
| 502 |
|
|
endcase // case (decode_insn_i[`OR1K_ALU_OPC_SELECT])
|
| 503 |
|
|
|
| 504 |
|
|
`OR1K_OPCODE_SYSTRAPSYNC: begin
|
| 505 |
|
|
if ((decode_insn_i[`OR1K_SYSTRAPSYNC_OPC_SELECT] ==
|
| 506 |
|
|
`OR1K_SYSTRAPSYNC_OPC_SYSCALL &&
|
| 507 |
|
|
FEATURE_SYSCALL=="ENABLED") ||
|
| 508 |
|
|
(decode_insn_i[`OR1K_SYSTRAPSYNC_OPC_SELECT] ==
|
| 509 |
|
|
`OR1K_SYSTRAPSYNC_OPC_TRAP &&
|
| 510 |
|
|
FEATURE_TRAP=="ENABLED") ||
|
| 511 |
|
|
(decode_insn_i[`OR1K_SYSTRAPSYNC_OPC_SELECT] ==
|
| 512 |
|
|
`OR1K_SYSTRAPSYNC_OPC_MSYNC) ||
|
| 513 |
|
|
(decode_insn_i[`OR1K_SYSTRAPSYNC_OPC_SELECT] ==
|
| 514 |
|
|
`OR1K_SYSTRAPSYNC_OPC_PSYNC &&
|
| 515 |
|
|
FEATURE_PSYNC!="NONE") ||
|
| 516 |
|
|
(decode_insn_i[`OR1K_SYSTRAPSYNC_OPC_SELECT] ==
|
| 517 |
|
|
`OR1K_SYSTRAPSYNC_OPC_CSYNC &&
|
| 518 |
|
|
FEATURE_CSYNC!="NONE"))
|
| 519 |
|
|
decode_except_illegal_o = 1'b0;
|
| 520 |
|
|
else
|
| 521 |
|
|
decode_except_illegal_o = 1'b1;
|
| 522 |
|
|
end // case: endcase...
|
| 523 |
|
|
default:
|
| 524 |
|
|
decode_except_illegal_o = 1'b1;
|
| 525 |
|
|
|
| 526 |
|
|
endcase // case (decode_insn_i[`OR1K_OPCODE_SELECT])
|
| 527 |
|
|
|
| 528 |
|
|
// Adder control logic
|
| 529 |
|
|
// Subtract when comparing to check if equal
|
| 530 |
|
|
assign decode_adder_do_sub_o = (opc_insn == `OR1K_OPCODE_ALU &
|
| 531 |
|
|
opc_alu == `OR1K_ALU_OPC_SUB) |
|
| 532 |
|
|
decode_op_setflag_o;
|
| 533 |
|
|
|
| 534 |
|
|
// Generate carry-in select
|
| 535 |
|
|
assign decode_adder_do_carry_o = (FEATURE_ADDC!="NONE") &&
|
| 536 |
|
|
((opc_insn == `OR1K_OPCODE_ALU &
|
| 537 |
|
|
opc_alu == `OR1K_ALU_OPC_ADDC) ||
|
| 538 |
|
|
(opc_insn == `OR1K_OPCODE_ADDIC));
|
| 539 |
|
|
|
| 540 |
|
|
endmodule // mor1kx_decode
|
