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/******************************************************************************
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This Source Code Form is subject to the terms of the
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Open Hardware Description License, v. 1.0. If a copy
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of the OHDL was not distributed with this file, You
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can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
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Description: Data MMU implementation
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Copyright (C) 2013 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
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******************************************************************************/
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`include "mor1kx-defines.v"
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module mor1kx_dmmu
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#(
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parameter FEATURE_DMMU_HW_TLB_RELOAD = "NONE",
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parameter OPTION_OPERAND_WIDTH = 32,
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parameter OPTION_DMMU_SET_WIDTH = 6,
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parameter OPTION_DMMU_WAYS = 1
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)
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(
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input clk,
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input rst,
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input enable_i,
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input [OPTION_OPERAND_WIDTH-1:0] virt_addr_i,
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input [OPTION_OPERAND_WIDTH-1:0] virt_addr_match_i,
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output reg [OPTION_OPERAND_WIDTH-1:0] phys_addr_o,
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output reg cache_inhibit_o,
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input op_store_i,
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input op_load_i,
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input supervisor_mode_i,
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output reg tlb_miss_o,
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output pagefault_o,
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output reg tlb_reload_req_o,
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output tlb_reload_busy_o,
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input tlb_reload_ack_i,
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output reg [OPTION_OPERAND_WIDTH-1:0] tlb_reload_addr_o,
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input [OPTION_OPERAND_WIDTH-1:0] tlb_reload_data_i,
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output tlb_reload_pagefault_o,
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input tlb_reload_pagefault_clear_i,
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// SPR interface
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input [15:0] spr_bus_addr_i,
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input spr_bus_we_i,
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input spr_bus_stb_i,
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input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_i,
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output [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_o,
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output spr_bus_ack_o
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);
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localparam WAYS_WIDTH = (OPTION_DMMU_WAYS < 2) ? 1 : 2;
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wire [OPTION_OPERAND_WIDTH-1:0] dtlb_match_dout[OPTION_DMMU_WAYS-1:0];
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wire [OPTION_DMMU_SET_WIDTH-1:0] dtlb_match_addr;
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reg [OPTION_DMMU_WAYS-1:0] dtlb_match_we;
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wire [OPTION_OPERAND_WIDTH-1:0] dtlb_match_din;
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wire [OPTION_OPERAND_WIDTH-1:0] dtlb_match_huge_dout[OPTION_DMMU_WAYS-1:0];
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wire [OPTION_DMMU_SET_WIDTH-1:0] dtlb_match_huge_addr;
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wire dtlb_match_huge_we;
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wire [OPTION_OPERAND_WIDTH-1:0] dtlb_trans_dout[OPTION_DMMU_WAYS-1:0];
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wire [OPTION_DMMU_SET_WIDTH-1:0] dtlb_trans_addr;
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reg [OPTION_DMMU_WAYS-1:0] dtlb_trans_we;
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wire [OPTION_OPERAND_WIDTH-1:0] dtlb_trans_din;
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wire [OPTION_OPERAND_WIDTH-1:0] dtlb_trans_huge_dout[OPTION_DMMU_WAYS-1:0];
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wire [OPTION_DMMU_SET_WIDTH-1:0] dtlb_trans_huge_addr;
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wire dtlb_trans_huge_we;
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reg dtlb_match_reload_we;
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reg [OPTION_OPERAND_WIDTH-1:0] dtlb_match_reload_din;
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reg dtlb_trans_reload_we;
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reg [OPTION_OPERAND_WIDTH-1:0] dtlb_trans_reload_din;
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wire dtlb_match_spr_cs;
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reg dtlb_match_spr_cs_r;
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wire dtlb_trans_spr_cs;
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reg dtlb_trans_spr_cs_r;
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wire dmmucr_spr_cs;
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reg dmmucr_spr_cs_r;
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reg [OPTION_OPERAND_WIDTH-1:0] dmmucr;
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wire [1:0] spr_way_idx_full;
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wire [WAYS_WIDTH-1:0] spr_way_idx;
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reg [WAYS_WIDTH-1:0] spr_way_idx_r;
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wire [OPTION_DMMU_WAYS-1:0] way_huge;
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wire [OPTION_DMMU_WAYS-1:0] way_hit;
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wire [OPTION_DMMU_WAYS-1:0] way_huge_hit;
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reg tlb_reload_pagefault;
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reg tlb_reload_huge;
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// ure: user read enable
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// uwe: user write enable
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// sre: supervisor read enable
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// swe: supervisor write enable
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reg ure;
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reg uwe;
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reg sre;
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reg swe;
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reg spr_bus_ack;
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genvar i;
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always @(posedge clk `OR_ASYNC_RST)
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if (rst)
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spr_bus_ack <= 0;
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else if (spr_bus_stb_i & spr_bus_addr_i[15:11] == 5'd1)
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spr_bus_ack <= 1;
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else
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spr_bus_ack <= 0;
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assign spr_bus_ack_o = spr_bus_ack & spr_bus_stb_i &
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spr_bus_addr_i[15:11] == 5'd1;
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generate
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for (i = 0; i < OPTION_DMMU_WAYS; i=i+1) begin : ways
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assign way_huge[i] = &dtlb_match_huge_dout[i][1:0]; // huge & valid
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assign way_hit[i] = (dtlb_match_dout[i][31:13] == virt_addr_match_i[31:13]) &
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dtlb_match_dout[i][0]; // valid bit
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assign way_huge_hit[i] = (dtlb_match_huge_dout[i][31:24] ==
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virt_addr_match_i[31:24]) &
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dtlb_match_huge_dout[i][0];
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end
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endgenerate
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integer j;
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always @(*) begin
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tlb_miss_o = !tlb_reload_pagefault;
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phys_addr_o = {OPTION_OPERAND_WIDTH{1'b0}};
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phys_addr_o[23:0] = virt_addr_match_i[23:0];
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ure = 0;
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uwe = 0;
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sre = 0;
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swe = 0;
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cache_inhibit_o = 0;
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for (j = 0; j < OPTION_DMMU_WAYS; j=j+1) begin
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if (way_huge[j] & way_huge_hit[j] | !way_huge[j] & way_hit[j])
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tlb_miss_o = 0;
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if (way_huge[j] & way_huge_hit[j]) begin
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phys_addr_o = {dtlb_trans_huge_dout[j][31:24], virt_addr_match_i[23:0]};
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ure = dtlb_trans_huge_dout[j][6];
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uwe = dtlb_trans_huge_dout[j][7];
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sre = dtlb_trans_huge_dout[j][8];
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swe = dtlb_trans_huge_dout[j][9];
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cache_inhibit_o = dtlb_trans_huge_dout[j][1];
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end else if (!way_huge[j] & way_hit[j])begin
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phys_addr_o = {dtlb_trans_dout[j][31:13], virt_addr_match_i[12:0]};
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ure = dtlb_trans_dout[j][6];
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uwe = dtlb_trans_dout[j][7];
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sre = dtlb_trans_dout[j][8];
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swe = dtlb_trans_dout[j][9];
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cache_inhibit_o = dtlb_trans_dout[j][1];
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end
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dtlb_match_we[j] = 0;
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if (dtlb_match_reload_we)
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dtlb_match_we[j] = 1;
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if (j[WAYS_WIDTH-1:0] == spr_way_idx)
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dtlb_match_we[j] = dtlb_match_spr_cs & spr_bus_we_i;
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dtlb_trans_we[j] = 0;
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if (dtlb_trans_reload_we)
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dtlb_trans_we[j] = 1;
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if (j[WAYS_WIDTH-1:0] == spr_way_idx)
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dtlb_trans_we[j] = dtlb_trans_spr_cs & spr_bus_we_i;
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end
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end
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assign pagefault_o = (supervisor_mode_i ?
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!swe & op_store_i || !sre & op_load_i :
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!uwe & op_store_i || !ure & op_load_i) &
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!tlb_reload_busy_o;
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assign spr_way_idx_full = {spr_bus_addr_i[10], spr_bus_addr_i[8]};
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assign spr_way_idx = spr_way_idx_full[WAYS_WIDTH-1:0];
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always @(posedge clk `OR_ASYNC_RST)
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if (rst) begin
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dtlb_match_spr_cs_r <= 0;
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dtlb_trans_spr_cs_r <= 0;
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dmmucr_spr_cs_r <= 0;
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spr_way_idx_r <= 0;
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end else begin
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dtlb_match_spr_cs_r <= dtlb_match_spr_cs;
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dtlb_trans_spr_cs_r <= dtlb_trans_spr_cs;
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dmmucr_spr_cs_r <= dmmucr_spr_cs;
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spr_way_idx_r <= spr_way_idx;
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end
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generate /* verilator lint_off WIDTH */
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if (FEATURE_DMMU_HW_TLB_RELOAD == "ENABLED") begin
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/* verilator lint_on WIDTH */
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assign dmmucr_spr_cs = spr_bus_stb_i &
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spr_bus_addr_i == `OR1K_SPR_DMMUCR_ADDR;
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always @(posedge clk `OR_ASYNC_RST)
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if (rst)
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dmmucr <= 0;
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else if (dmmucr_spr_cs & spr_bus_we_i)
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dmmucr <= spr_bus_dat_i;
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end else begin
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assign dmmucr_spr_cs = 0;
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always @(posedge clk)
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dmmucr <= 0;
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end
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endgenerate
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assign dtlb_match_spr_cs = spr_bus_stb_i & (spr_bus_addr_i[15:11] == 5'd1) &
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|spr_bus_addr_i[10:9] & !spr_bus_addr_i[7];
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assign dtlb_trans_spr_cs = spr_bus_stb_i & (spr_bus_addr_i[15:11] == 5'd1) &
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|spr_bus_addr_i[10:9] & spr_bus_addr_i[7];
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assign dtlb_match_addr = dtlb_match_spr_cs ?
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spr_bus_addr_i[OPTION_DMMU_SET_WIDTH-1:0] :
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virt_addr_i[13+(OPTION_DMMU_SET_WIDTH-1):13];
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assign dtlb_trans_addr = dtlb_trans_spr_cs ?
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spr_bus_addr_i[OPTION_DMMU_SET_WIDTH-1:0] :
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virt_addr_i[13+(OPTION_DMMU_SET_WIDTH-1):13];
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assign dtlb_match_din = dtlb_match_reload_we ? dtlb_match_reload_din :
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spr_bus_dat_i;
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assign dtlb_trans_din = dtlb_trans_reload_we ? dtlb_trans_reload_din :
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spr_bus_dat_i;
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assign dtlb_match_huge_addr = virt_addr_i[24+(OPTION_DMMU_SET_WIDTH-1):24];
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assign dtlb_trans_huge_addr = virt_addr_i[24+(OPTION_DMMU_SET_WIDTH-1):24];
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assign dtlb_match_huge_we = dtlb_match_reload_we & tlb_reload_huge;
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assign dtlb_trans_huge_we = dtlb_trans_reload_we & tlb_reload_huge;
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assign spr_bus_dat_o = dtlb_match_spr_cs_r ? dtlb_match_dout[spr_way_idx_r] :
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dtlb_trans_spr_cs_r ? dtlb_trans_dout[spr_way_idx_r] :
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dmmucr_spr_cs_r ? dmmucr : 0;
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localparam TLB_IDLE = 2'd0;
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localparam TLB_GET_PTE_POINTER = 2'd1;
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localparam TLB_GET_PTE = 2'd2;
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localparam TLB_READ = 2'd3;
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generate /* verilator lint_off WIDTH */
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if (FEATURE_DMMU_HW_TLB_RELOAD == "ENABLED") begin
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/* verilator lint_on WIDTH */
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// Hardware TLB reload
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// Compliant with the suggestion outlined in this thread:
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// http://lists.openrisc.net/pipermail/openrisc/2013-July/001806.html
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//
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// PTE layout:
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// | 31 ... 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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// | PPN | Reserved |PRESENT| L | X | W | U | D | A |WOM|WBC|CI |CC |
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//
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// Where X/W/U maps into SWE/SRE/UWE/URE like this:
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// X | W | U SWE | SRE | UWE | URE
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// ---------- ---------------------
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// x | 0 | 0 = 0 | 1 | 0 | 0
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// x | 0 | 1 = 0 | 1 | 0 | 1
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// x | 1 | 0 = 1 | 1 | 0 | 0
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// x | 1 | 1 = 1 | 1 | 1 | 1
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reg [1:0] tlb_reload_state = TLB_IDLE;
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wire do_reload;
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assign do_reload = enable_i & tlb_miss_o & (dmmucr[31:10] != 0) &
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(op_load_i | op_store_i);
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assign tlb_reload_busy_o = enable_i & (tlb_reload_state != TLB_IDLE) | do_reload;
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assign tlb_reload_pagefault_o = tlb_reload_pagefault &
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!tlb_reload_pagefault_clear_i;
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always @(posedge clk) begin
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if (tlb_reload_pagefault_clear_i)
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tlb_reload_pagefault <= 0;
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dtlb_trans_reload_we <= 0;
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dtlb_trans_reload_din <= 0;
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dtlb_match_reload_we <= 0;
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dtlb_match_reload_din <= 0;
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case (tlb_reload_state)
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TLB_IDLE: begin
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tlb_reload_huge <= 0;
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tlb_reload_req_o <= 0;
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if (do_reload) begin
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tlb_reload_req_o <= 1;
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tlb_reload_addr_o <= {dmmucr[31:10],
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virt_addr_match_i[31:24], 2'b00};
|
307 |
|
|
tlb_reload_state <= TLB_GET_PTE_POINTER;
|
308 |
|
|
end
|
309 |
|
|
end
|
310 |
|
|
|
311 |
|
|
//
|
312 |
|
|
// Here we get the pointer to the PTE table, next is to fetch
|
313 |
|
|
// the actual pte from the offset in the table.
|
314 |
|
|
// The offset is calculated by:
|
315 |
|
|
// ((virt_addr_match >> PAGE_BITS) & (PTE_CNT-1)) << 2
|
316 |
|
|
// Where PAGE_BITS is 13 (8 kb page) and PTE_CNT is 2048
|
317 |
|
|
// (number of PTEs in the PTE table)
|
318 |
|
|
//
|
319 |
|
|
TLB_GET_PTE_POINTER: begin
|
320 |
|
|
tlb_reload_huge <= 0;
|
321 |
|
|
if (tlb_reload_ack_i) begin
|
322 |
|
|
if (tlb_reload_data_i[31:13] == 0) begin
|
323 |
|
|
tlb_reload_pagefault <= 1;
|
324 |
|
|
tlb_reload_req_o <= 0;
|
325 |
|
|
tlb_reload_state <= TLB_IDLE;
|
326 |
|
|
end else if (tlb_reload_data_i[9]) begin
|
327 |
|
|
tlb_reload_huge <= 1;
|
328 |
|
|
tlb_reload_req_o <= 0;
|
329 |
|
|
tlb_reload_state <= TLB_GET_PTE;
|
330 |
|
|
end else begin
|
331 |
|
|
tlb_reload_addr_o <= {tlb_reload_data_i[31:13],
|
332 |
|
|
virt_addr_match_i[23:13], 2'b00};
|
333 |
|
|
tlb_reload_state <= TLB_GET_PTE;
|
334 |
|
|
end
|
335 |
|
|
end
|
336 |
|
|
end
|
337 |
|
|
|
338 |
|
|
//
|
339 |
|
|
// Here we get the actual PTE, left to do is to translate the
|
340 |
|
|
// PTE data into our translate and match registers.
|
341 |
|
|
//
|
342 |
|
|
TLB_GET_PTE: begin
|
343 |
|
|
if (tlb_reload_ack_i) begin
|
344 |
|
|
tlb_reload_req_o <= 0;
|
345 |
|
|
// Check PRESENT bit
|
346 |
|
|
if (!tlb_reload_data_i[10]) begin
|
347 |
|
|
tlb_reload_pagefault <= 1;
|
348 |
|
|
tlb_reload_state <= TLB_IDLE;
|
349 |
|
|
end else begin
|
350 |
|
|
// Translate register generation.
|
351 |
|
|
// PPN
|
352 |
|
|
dtlb_trans_reload_din[31:13] <= tlb_reload_data_i[31:13];
|
353 |
|
|
// SWE = W
|
354 |
|
|
dtlb_trans_reload_din[9] <= tlb_reload_data_i[7];
|
355 |
|
|
// SRE = 1
|
356 |
|
|
dtlb_trans_reload_din[8] <= 1'b1;
|
357 |
|
|
// UWE = W & U
|
358 |
|
|
dtlb_trans_reload_din[7] <= tlb_reload_data_i[7] &
|
359 |
|
|
tlb_reload_data_i[6];
|
360 |
|
|
// URE = U
|
361 |
|
|
dtlb_trans_reload_din[6] <= tlb_reload_data_i[6];
|
362 |
|
|
// Dirty, Accessed, Weakly-Ordered-Memory, Writeback cache,
|
363 |
|
|
// Cache inhibit, Cache coherent
|
364 |
|
|
dtlb_trans_reload_din[5:0] <= tlb_reload_data_i[5:0];
|
365 |
|
|
dtlb_trans_reload_we <= 1;
|
366 |
|
|
|
367 |
|
|
// Match register generation.
|
368 |
|
|
// VPN
|
369 |
|
|
dtlb_match_reload_din[31:13] <= virt_addr_match_i[31:13];
|
370 |
|
|
// Valid
|
371 |
|
|
dtlb_match_reload_din[0] <= 1;
|
372 |
|
|
dtlb_match_reload_we <= 1;
|
373 |
|
|
|
374 |
|
|
tlb_reload_state <= TLB_READ;
|
375 |
|
|
end
|
376 |
|
|
end
|
377 |
|
|
end
|
378 |
|
|
|
379 |
|
|
// Let the just written values propagate out on the read ports
|
380 |
|
|
TLB_READ: begin
|
381 |
|
|
tlb_reload_state <= TLB_IDLE;
|
382 |
|
|
end
|
383 |
|
|
|
384 |
|
|
default:
|
385 |
|
|
tlb_reload_state <= TLB_IDLE;
|
386 |
|
|
endcase
|
387 |
|
|
|
388 |
|
|
// Abort if enable deasserts in the middle of a reload
|
389 |
|
|
if (!enable_i | (dmmucr[31:10] == 0))
|
390 |
|
|
tlb_reload_state <= TLB_IDLE;
|
391 |
|
|
|
392 |
|
|
end
|
393 |
|
|
end else begin // if (FEATURE_DMMU_HW_TLB_RELOAD == "ENABLED")
|
394 |
|
|
assign tlb_reload_pagefault_o = 0;
|
395 |
|
|
assign tlb_reload_busy_o = 0;
|
396 |
|
|
always @(posedge clk) begin
|
397 |
|
|
tlb_reload_req_o <= 0;
|
398 |
|
|
tlb_reload_addr_o <= 0;
|
399 |
|
|
tlb_reload_pagefault <= 0;
|
400 |
|
|
dtlb_trans_reload_we <= 0;
|
401 |
|
|
dtlb_trans_reload_din <= 0;
|
402 |
|
|
dtlb_match_reload_we <= 0;
|
403 |
|
|
dtlb_match_reload_din <= 0;
|
404 |
|
|
end
|
405 |
|
|
end
|
406 |
|
|
endgenerate
|
407 |
|
|
|
408 |
|
|
generate
|
409 |
|
|
for (i = 0; i < OPTION_DMMU_WAYS; i=i+1) begin : dtlb
|
410 |
|
|
// DTLB match registers
|
411 |
|
|
mor1kx_true_dpram_sclk
|
412 |
|
|
#(
|
413 |
|
|
.ADDR_WIDTH(OPTION_DMMU_SET_WIDTH),
|
414 |
|
|
.DATA_WIDTH(OPTION_OPERAND_WIDTH)
|
415 |
|
|
)
|
416 |
|
|
dtlb_match_regs
|
417 |
|
|
(
|
418 |
|
|
// Outputs
|
419 |
|
|
.dout_a (dtlb_match_dout[i]),
|
420 |
|
|
.dout_b (dtlb_match_huge_dout[i]),
|
421 |
|
|
// Inputs
|
422 |
|
|
.clk_a (clk),
|
423 |
|
|
.addr_a (dtlb_match_addr),
|
424 |
|
|
.we_a (dtlb_match_we[i]),
|
425 |
|
|
.din_a (dtlb_match_din),
|
426 |
|
|
.clk_b (clk),
|
427 |
|
|
.addr_b (dtlb_match_huge_addr),
|
428 |
|
|
.we_b (dtlb_match_huge_we),
|
429 |
|
|
.din_b (dtlb_match_reload_din)
|
430 |
|
|
);
|
431 |
|
|
|
432 |
|
|
|
433 |
|
|
// DTLB translate registers
|
434 |
|
|
mor1kx_true_dpram_sclk
|
435 |
|
|
#(
|
436 |
|
|
.ADDR_WIDTH(OPTION_DMMU_SET_WIDTH),
|
437 |
|
|
.DATA_WIDTH(OPTION_OPERAND_WIDTH)
|
438 |
|
|
)
|
439 |
|
|
dtlb_translate_regs
|
440 |
|
|
(
|
441 |
|
|
// Outputs
|
442 |
|
|
.dout_a (dtlb_trans_dout[i]),
|
443 |
|
|
.dout_b (dtlb_trans_huge_dout[i]),
|
444 |
|
|
// Inputs
|
445 |
|
|
.clk_a (clk),
|
446 |
|
|
.addr_a (dtlb_trans_addr),
|
447 |
|
|
.we_a (dtlb_trans_we[i]),
|
448 |
|
|
.din_a (dtlb_trans_din),
|
449 |
|
|
.clk_b (clk),
|
450 |
|
|
.addr_b (dtlb_trans_huge_addr),
|
451 |
|
|
.we_b (dtlb_trans_huge_we),
|
452 |
|
|
.din_b (dtlb_trans_reload_din)
|
453 |
|
|
);
|
454 |
|
|
end
|
455 |
|
|
endgenerate
|
456 |
|
|
|
457 |
|
|
endmodule // mor1kx_dmmu
|