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Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [new_lm32/] [rtl/] [lm32_debug.v] - Blame information for rev 48

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//   ==================================================================
//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
//   ------------------------------------------------------------------
//   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
//   ALL RIGHTS RESERVED
//   ------------------------------------------------------------------
//
//   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
//
//   Permission:
//
//      Lattice Semiconductor grants permission to use this code
//      pursuant to the terms of the Lattice Semiconductor Corporation
//      Open Source License Agreement.
//
//   Disclaimer:
//
//      Lattice Semiconductor provides no warranty regarding the use or
//      functionality of this code. It is the user's responsibility to
//      verify the user's design for consistency and functionality through
//      the use of formal verification methods.
//
//   --------------------------------------------------------------------
//
//                  Lattice Semiconductor Corporation
//                  5555 NE Moore Court
//                  Hillsboro, OR 97214
//                  U.S.A
//
//                  TEL: 1-800-Lattice (USA and Canada)
//                         503-286-8001 (other locations)
//
//                  web: http://www.latticesemi.com/
//                  email: techsupport@latticesemi.com
//
//   --------------------------------------------------------------------
//                         FILE DETAILS
// Project          : LatticeMico32
// File             : lm32_debug.v
// Title            : Hardware debug registers and associated logic.
// Dependencies     : lm32_include.v
// Version          : 6.1.17
//                  : Initial Release
// Version          : 7.0SP2, 3.0
//                  : No Change
// Version          : 3.1
//                  : No Change
// Version          : 3.2
//                  : Fixed simulation bug which flares up when number of
//                  : watchpoints is zero.
// =============================================================================
 
`include "lm32_include.v"
 
`ifdef CFG_DEBUG_ENABLED
 
// States for single-step FSM
`define LM32_DEBUG_SS_STATE_RNG                 2:0
`define LM32_DEBUG_SS_STATE_IDLE                3'b000
`define LM32_DEBUG_SS_STATE_WAIT_FOR_RET        3'b001
`define LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN    3'b010
`define LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT    3'b011
`define LM32_DEBUG_SS_STATE_RESTART             3'b100
 
/////////////////////////////////////////////////////
// Module interface
/////////////////////////////////////////////////////
 
module lm32_debug (
    // ----- Inputs -------
    clk_i,
    rst_i,
    pc_x,
    load_x,
    store_x,
    load_store_address_x,
    csr_write_enable_x,
    csr_write_data,
    csr_x,
`ifdef CFG_HW_DEBUG_ENABLED
    jtag_csr_write_enable,
    jtag_csr_write_data,
    jtag_csr,
`endif
`ifdef LM32_SINGLE_STEP_ENABLED
    eret_q_x,
    bret_q_x,
    stall_x,
    exception_x,
    q_x,
`ifdef CFG_DCACHE_ENABLED
    dcache_refill_request,
`endif
`endif
    // ----- Outputs -------
`ifdef LM32_SINGLE_STEP_ENABLED
    dc_ss,
`endif
    dc_re,
    bp_match,
    wp_match
    );
 
/////////////////////////////////////////////////////
// Parameters
/////////////////////////////////////////////////////
 
parameter breakpoints = 0;                      // Number of breakpoint CSRs
parameter watchpoints = 0;                      // Number of watchpoint CSRs
 
/////////////////////////////////////////////////////
// Inputs
/////////////////////////////////////////////////////
 
input clk_i;                                    // Clock
input rst_i;                                    // Reset
 
input [`LM32_PC_RNG] pc_x;                      // X stage PC
input load_x;                                   // Load instruction in X stage
input store_x;                                  // Store instruction in X stage
input [`LM32_WORD_RNG] load_store_address_x;    // Load or store effective address
input csr_write_enable_x;                       // wcsr instruction in X stage
input [`LM32_WORD_RNG] csr_write_data;          // Data to write to CSR
input [`LM32_CSR_RNG] csr_x;                    // Which CSR to write
`ifdef CFG_HW_DEBUG_ENABLED
input jtag_csr_write_enable;                    // JTAG interface CSR write enable
input [`LM32_WORD_RNG] jtag_csr_write_data;     // Data to write to CSR
input [`LM32_CSR_RNG] jtag_csr;                 // Which CSR to write
`endif
`ifdef LM32_SINGLE_STEP_ENABLED
input eret_q_x;                                 // eret instruction in X stage
input bret_q_x;                                 // bret instruction in X stage
input stall_x;                                  // Instruction in X stage is stalled
input exception_x;                              // An exception has occured in X stage
input q_x;                                      // Indicates the instruction in the X stage is qualified
`ifdef CFG_DCACHE_ENABLED
input dcache_refill_request;                    // Indicates data cache wants to be refilled
`endif
`endif
 
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
 
`ifdef LM32_SINGLE_STEP_ENABLED
output dc_ss;                                   // Single-step enable
reg    dc_ss;
`endif
output dc_re;                                   // Remap exceptions
reg    dc_re;
output bp_match;                                // Indicates a breakpoint has matched
wire   bp_match;
output wp_match;                                // Indicates a watchpoint has matched
wire   wp_match;
 
/////////////////////////////////////////////////////
// Internal nets and registers
/////////////////////////////////////////////////////
 
genvar i;                                       // Loop index for generate statements
 
// Debug CSRs
 
reg [`LM32_PC_RNG] bp_a[0:breakpoints-1];       // Instruction breakpoint address
reg bp_e[0:breakpoints-1];                      // Instruction breakpoint enable
wire [0:breakpoints-1]bp_match_n;               // Indicates if a h/w instruction breakpoint matched
 
reg [`LM32_WPC_C_RNG] wpc_c[0:watchpoints-1];   // Watchpoint enable
reg [`LM32_WORD_RNG] wp[0:watchpoints-1];       // Watchpoint address
wire [0:watchpoints-1]wp_match_n;               // Indicates if a h/w data watchpoint matched
 
wire debug_csr_write_enable;                    // Debug CSR write enable (from either a wcsr instruction of external debugger)
wire [`LM32_WORD_RNG] debug_csr_write_data;     // Data to write to debug CSR
wire [`LM32_CSR_RNG] debug_csr;                 // Debug CSR to write to
 
`ifdef LM32_SINGLE_STEP_ENABLED
// FIXME: Declaring this as a reg causes ModelSim 6.1.15b to crash, so use integer for now
//reg [`LM32_DEBUG_SS_STATE_RNG] state;           // State of single-step FSM
integer state;                                  // State of single-step FSM
`endif
 
/////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////
 
/////////////////////////////////////////////////////
// Combinational Logic
/////////////////////////////////////////////////////
 
// Check for breakpoints
generate
    for (i = 0; i < breakpoints; i = i + 1)
    begin : bp_comb
assign bp_match_n[i] = ((bp_a[i] == pc_x) && (bp_e[i] == `TRUE));
    end
endgenerate
generate
`ifdef LM32_SINGLE_STEP_ENABLED
    if (breakpoints > 0)
assign bp_match = (|bp_match_n) || (state == `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT);
    else
assign bp_match = state == `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT;
`else
    if (breakpoints > 0)
assign bp_match = |bp_match_n;
    else
assign bp_match = `FALSE;
`endif
endgenerate
 
// Check for watchpoints
generate
    for (i = 0; i < watchpoints; i = i + 1)
    begin : wp_comb
assign wp_match_n[i] = (wp[i] == load_store_address_x) && ((load_x & wpc_c[i][0]) | (store_x & wpc_c[i][1]));
    end
endgenerate
generate
    if (watchpoints > 0)
assign wp_match = |wp_match_n;
    else
assign wp_match = `FALSE;
endgenerate
 
`ifdef CFG_HW_DEBUG_ENABLED
// Multiplex between wcsr instruction writes and debugger writes to the debug CSRs
assign debug_csr_write_enable = (csr_write_enable_x == `TRUE) || (jtag_csr_write_enable == `TRUE);
assign debug_csr_write_data = jtag_csr_write_enable == `TRUE ? jtag_csr_write_data : csr_write_data;
assign debug_csr = jtag_csr_write_enable == `TRUE ? jtag_csr : csr_x;
`else
assign debug_csr_write_enable = csr_write_enable_x;
assign debug_csr_write_data = csr_write_data;
assign debug_csr = csr_x;
`endif
 
/////////////////////////////////////////////////////
// Sequential Logic
/////////////////////////////////////////////////////
 
// Breakpoint address and enable CSRs
generate
    for (i = 0; i < breakpoints; i = i + 1)
    begin : bp_seq
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
    if (rst_i == `TRUE)
    begin
        bp_a[i] <= {`LM32_PC_WIDTH{1'bx}};
        bp_e[i] <= `FALSE;
    end
    else
    begin
        if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_BP0 + i))
        begin
            bp_a[i] <= debug_csr_write_data[`LM32_PC_RNG];
            bp_e[i] <= debug_csr_write_data[0];
        end
    end
end
    end
endgenerate
 
// Watchpoint address and control flags CSRs
generate
    for (i = 0; i < watchpoints; i = i + 1)
    begin : wp_seq
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
    if (rst_i == `TRUE)
    begin
        wp[i] <= {`LM32_WORD_WIDTH{1'bx}};
        wpc_c[i] <= `LM32_WPC_C_DISABLED;
    end
    else
    begin
        if (debug_csr_write_enable == `TRUE)
        begin
            if (debug_csr == `LM32_CSR_DC)
                wpc_c[i] <= debug_csr_write_data[3+i*2:2+i*2];
            if (debug_csr == `LM32_CSR_WP0 + i)
                wp[i] <= debug_csr_write_data;
        end
    end
end
    end
endgenerate
 
// Remap exceptions control bit
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
    if (rst_i == `TRUE)
        dc_re <= `FALSE;
    else
    begin
        if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_DC))
            dc_re <= debug_csr_write_data[1];
    end
end
 
`ifdef LM32_SINGLE_STEP_ENABLED
// Single-step control flag
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
    if (rst_i == `TRUE)
    begin
        state <= `LM32_DEBUG_SS_STATE_IDLE;
        dc_ss <= `FALSE;
    end
    else
    begin
        if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_DC))
        begin
            dc_ss <= debug_csr_write_data[0];
            if (debug_csr_write_data[0] == `FALSE)
                state <= `LM32_DEBUG_SS_STATE_IDLE;
            else
                state <= `LM32_DEBUG_SS_STATE_WAIT_FOR_RET;
        end
        case (state)
        `LM32_DEBUG_SS_STATE_WAIT_FOR_RET:
        begin
            // Wait for eret or bret instruction to be executed
            if (   (   (eret_q_x == `TRUE)
                    || (bret_q_x == `TRUE)
                    )
                && (stall_x == `FALSE)
               )
                state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN;
        end
        `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN:
        begin
            // Wait for an instruction to be executed
            if ((q_x == `TRUE) && (stall_x == `FALSE))
                state <= `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT;
        end
        `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT:
        begin
            // Wait for exception to be raised
`ifdef CFG_DCACHE_ENABLED
            if (dcache_refill_request == `TRUE)
                state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN;
            else
`endif
                 if ((exception_x == `TRUE) && (q_x == `TRUE) && (stall_x == `FALSE))
            begin
                dc_ss <= `FALSE;
                state <= `LM32_DEBUG_SS_STATE_RESTART;
            end
        end
        `LM32_DEBUG_SS_STATE_RESTART:
        begin
            // Watch to see if stepped instruction is restarted due to a cache miss
`ifdef CFG_DCACHE_ENABLED
            if (dcache_refill_request == `TRUE)
                state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN;
            else
`endif
                state <= `LM32_DEBUG_SS_STATE_IDLE;
        end
        endcase
    end
end
`endif
 
endmodule
 
`endif

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Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [new_lm32/] [rtl/] [lm32_debug.v] - Blame information for rev 48

Line No.	Rev	Author	Line
1	48	alirezamon	`// ==================================================================`
2			`// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<`
3			`// ------------------------------------------------------------------`
4			`// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation`
5			`// ALL RIGHTS RESERVED`
6			`// ------------------------------------------------------------------`
7			`//`
8			`// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.`
9			`//`
10			`// Permission:`
11			`//`
12			`// Lattice Semiconductor grants permission to use this code`
13			`// pursuant to the terms of the Lattice Semiconductor Corporation`
14			`// Open Source License Agreement.`
15			`//`
16			`// Disclaimer:`
17			`//`
18			`// Lattice Semiconductor provides no warranty regarding the use or`
19			`// functionality of this code. It is the user's responsibility to`
20			`// verify the user's design for consistency and functionality through`
21			`// the use of formal verification methods.`
22			`//`
23			`// --------------------------------------------------------------------`
24			`//`
25			`// Lattice Semiconductor Corporation`
26			`// 5555 NE Moore Court`
27			`// Hillsboro, OR 97214`
28			`// U.S.A`
29			`//`
30			`// TEL: 1-800-Lattice (USA and Canada)`
31			`// 503-286-8001 (other locations)`
32			`//`
33			`// web: http://www.latticesemi.com/`
34			`// email: techsupport@latticesemi.com`
35			`//`
36			`// --------------------------------------------------------------------`
37			`// FILE DETAILS`
38			`// Project : LatticeMico32`
39			`// File : lm32_debug.v`
40			`// Title : Hardware debug registers and associated logic.`
41			`// Dependencies : lm32_include.v`
42			`// Version : 6.1.17`
43			`// : Initial Release`
44			`// Version : 7.0SP2, 3.0`
45			`// : No Change`
46			`// Version : 3.1`
47			`// : No Change`
48			`// Version : 3.2`
49			`// : Fixed simulation bug which flares up when number of`
50			`// : watchpoints is zero.`
51			`// =============================================================================`
52
53			`include "lm32_include.v"
54
55			`ifdef CFG_DEBUG_ENABLED
56
57			`// States for single-step FSM`
58			`define LM32_DEBUG_SS_STATE_RNG 2:0
59			`define LM32_DEBUG_SS_STATE_IDLE 3'b000
60			`define LM32_DEBUG_SS_STATE_WAIT_FOR_RET 3'b001
61			`define LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN 3'b010
62			`define LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT 3'b011
63			`define LM32_DEBUG_SS_STATE_RESTART 3'b100
64
65			`/////////////////////////////////////////////////////`
66			`// Module interface`
67			`/////////////////////////////////////////////////////`
68
69			`module lm32_debug (`
70			`// ----- Inputs -------`
71			`clk_i,`
72			`rst_i,`
73			`pc_x,`
74			`load_x,`
75			`store_x,`
76			`load_store_address_x,`
77			`csr_write_enable_x,`
78			`csr_write_data,`
79			`csr_x,`
80			`ifdef CFG_HW_DEBUG_ENABLED
81			`jtag_csr_write_enable,`
82			`jtag_csr_write_data,`
83			`jtag_csr,`
84			`endif
85			`ifdef LM32_SINGLE_STEP_ENABLED
86			`eret_q_x,`
87			`bret_q_x,`
88			`stall_x,`
89			`exception_x,`
90			`q_x,`
91			`ifdef CFG_DCACHE_ENABLED
92			`dcache_refill_request,`
93			`endif
94			`endif
95			`// ----- Outputs -------`
96			`ifdef LM32_SINGLE_STEP_ENABLED
97			`dc_ss,`
98			`endif
99			`dc_re,`
100			`bp_match,`
101			`wp_match`
102			`);`
103
104			`/////////////////////////////////////////////////////`
105			`// Parameters`
106			`/////////////////////////////////////////////////////`
107
108			`parameter breakpoints = 0; // Number of breakpoint CSRs`
109			`parameter watchpoints = 0; // Number of watchpoint CSRs`
110
111			`/////////////////////////////////////////////////////`
112			`// Inputs`
113			`/////////////////////////////////////////////////////`
114
115			`input clk_i; // Clock`
116			`input rst_i; // Reset`
117
118			input [`LM32_PC_RNG] pc_x; // X stage PC
119			`input load_x; // Load instruction in X stage`
120			`input store_x; // Store instruction in X stage`
121			input [`LM32_WORD_RNG] load_store_address_x; // Load or store effective address
122			`input csr_write_enable_x; // wcsr instruction in X stage`
123			input [`LM32_WORD_RNG] csr_write_data; // Data to write to CSR
124			input [`LM32_CSR_RNG] csr_x; // Which CSR to write
125			`ifdef CFG_HW_DEBUG_ENABLED
126			`input jtag_csr_write_enable; // JTAG interface CSR write enable`
127			input [`LM32_WORD_RNG] jtag_csr_write_data; // Data to write to CSR
128			input [`LM32_CSR_RNG] jtag_csr; // Which CSR to write
129			`endif
130			`ifdef LM32_SINGLE_STEP_ENABLED
131			`input eret_q_x; // eret instruction in X stage`
132			`input bret_q_x; // bret instruction in X stage`
133			`input stall_x; // Instruction in X stage is stalled`
134			`input exception_x; // An exception has occured in X stage`
135			`input q_x; // Indicates the instruction in the X stage is qualified`
136			`ifdef CFG_DCACHE_ENABLED
137			`input dcache_refill_request; // Indicates data cache wants to be refilled`
138			`endif
139			`endif
140
141			`/////////////////////////////////////////////////////`
142			`// Outputs`
143			`/////////////////////////////////////////////////////`
144
145			`ifdef LM32_SINGLE_STEP_ENABLED
146			`output dc_ss; // Single-step enable`
147			`reg dc_ss;`
148			`endif
149			`output dc_re; // Remap exceptions`
150			`reg dc_re;`
151			`output bp_match; // Indicates a breakpoint has matched`
152			`wire bp_match;`
153			`output wp_match; // Indicates a watchpoint has matched`
154			`wire wp_match;`
155
156			`/////////////////////////////////////////////////////`
157			`// Internal nets and registers`
158			`/////////////////////////////////////////////////////`
159
160			`genvar i; // Loop index for generate statements`
161
162			`// Debug CSRs`
163
164			reg [`LM32_PC_RNG] bp_a[0:breakpoints-1]; // Instruction breakpoint address
165			`reg bp_e[0:breakpoints-1]; // Instruction breakpoint enable`
166			`wire [0:breakpoints-1]bp_match_n; // Indicates if a h/w instruction breakpoint matched`
167
168			reg [`LM32_WPC_C_RNG] wpc_c[0:watchpoints-1]; // Watchpoint enable
169			reg [`LM32_WORD_RNG] wp[0:watchpoints-1]; // Watchpoint address
170			`wire [0:watchpoints-1]wp_match_n; // Indicates if a h/w data watchpoint matched`
171
172			`wire debug_csr_write_enable; // Debug CSR write enable (from either a wcsr instruction of external debugger)`
173			wire [`LM32_WORD_RNG] debug_csr_write_data; // Data to write to debug CSR
174			wire [`LM32_CSR_RNG] debug_csr; // Debug CSR to write to
175
176			`ifdef LM32_SINGLE_STEP_ENABLED
177			`// FIXME: Declaring this as a reg causes ModelSim 6.1.15b to crash, so use integer for now`
178			//reg [`LM32_DEBUG_SS_STATE_RNG] state; // State of single-step FSM
179			`integer state; // State of single-step FSM`
180			`endif
181
182			`/////////////////////////////////////////////////////`
183			`// Functions`
184			`/////////////////////////////////////////////////////`
185
186			`/////////////////////////////////////////////////////`
187			`// Combinational Logic`
188			`/////////////////////////////////////////////////////`
189
190			`// Check for breakpoints`
191			`generate`
192			`for (i = 0; i < breakpoints; i = i + 1)`
193			`begin : bp_comb`
194			assign bp_match_n[i] = ((bp_a[i] == pc_x) && (bp_e[i] == `TRUE));
195			`end`
196			`endgenerate`
197			`generate`
198			`ifdef LM32_SINGLE_STEP_ENABLED
199			`if (breakpoints > 0)`
200			assign bp_match = (\|bp_match_n) \|\| (state == `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT);
201			`else`
202			assign bp_match = state == `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT;
203			`else
204			`if (breakpoints > 0)`
205			`assign bp_match = \|bp_match_n;`
206			`else`
207			assign bp_match = `FALSE;
208			`endif
209			`endgenerate`
210
211			`// Check for watchpoints`
212			`generate`
213			`for (i = 0; i < watchpoints; i = i + 1)`
214			`begin : wp_comb`
215			`assign wp_match_n[i] = (wp[i] == load_store_address_x) && ((load_x & wpc_c[i][0]) \| (store_x & wpc_c[i][1]));`
216			`end`
217			`endgenerate`
218			`generate`
219			`if (watchpoints > 0)`
220			`assign wp_match = \|wp_match_n;`
221			`else`
222			assign wp_match = `FALSE;
223			`endgenerate`
224
225			`ifdef CFG_HW_DEBUG_ENABLED
226			`// Multiplex between wcsr instruction writes and debugger writes to the debug CSRs`
227			assign debug_csr_write_enable = (csr_write_enable_x == `TRUE) \|\| (jtag_csr_write_enable == `TRUE);
228			assign debug_csr_write_data = jtag_csr_write_enable == `TRUE ? jtag_csr_write_data : csr_write_data;
229			assign debug_csr = jtag_csr_write_enable == `TRUE ? jtag_csr : csr_x;
230			`else
231			`assign debug_csr_write_enable = csr_write_enable_x;`
232			`assign debug_csr_write_data = csr_write_data;`
233			`assign debug_csr = csr_x;`
234			`endif
235
236			`/////////////////////////////////////////////////////`
237			`// Sequential Logic`
238			`/////////////////////////////////////////////////////`
239
240			`// Breakpoint address and enable CSRs`
241			`generate`
242			`for (i = 0; i < breakpoints; i = i + 1)`
243			`begin : bp_seq`
244			always @(posedge clk_i `CFG_RESET_SENSITIVITY)
245			`begin`
246			if (rst_i == `TRUE)
247			`begin`
248			bp_a[i] <= {`LM32_PC_WIDTH{1'bx}};
249			bp_e[i] <= `FALSE;
250			`end`
251			`else`
252			`begin`
253			if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_BP0 + i))
254			`begin`
255			bp_a[i] <= debug_csr_write_data[`LM32_PC_RNG];
256			`bp_e[i] <= debug_csr_write_data[0];`
257			`end`
258			`end`
259			`end`
260			`end`
261			`endgenerate`
262
263			`// Watchpoint address and control flags CSRs`
264			`generate`
265			`for (i = 0; i < watchpoints; i = i + 1)`
266			`begin : wp_seq`
267			always @(posedge clk_i `CFG_RESET_SENSITIVITY)
268			`begin`
269			if (rst_i == `TRUE)
270			`begin`
271			wp[i] <= {`LM32_WORD_WIDTH{1'bx}};
272			wpc_c[i] <= `LM32_WPC_C_DISABLED;
273			`end`
274			`else`
275			`begin`
276			if (debug_csr_write_enable == `TRUE)
277			`begin`
278			if (debug_csr == `LM32_CSR_DC)
279			`wpc_c[i] <= debug_csr_write_data[3+i2:2+i2];`
280			if (debug_csr == `LM32_CSR_WP0 + i)
281			`wp[i] <= debug_csr_write_data;`
282			`end`
283			`end`
284			`end`
285			`end`
286			`endgenerate`
287
288			`// Remap exceptions control bit`
289			always @(posedge clk_i `CFG_RESET_SENSITIVITY)
290			`begin`
291			if (rst_i == `TRUE)
292			dc_re <= `FALSE;
293			`else`
294			`begin`
295			if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_DC))
296			`dc_re <= debug_csr_write_data[1];`
297			`end`
298			`end`
299
300			`ifdef LM32_SINGLE_STEP_ENABLED
301			`// Single-step control flag`
302			always @(posedge clk_i `CFG_RESET_SENSITIVITY)
303			`begin`
304			if (rst_i == `TRUE)
305			`begin`
306			state <= `LM32_DEBUG_SS_STATE_IDLE;
307			dc_ss <= `FALSE;
308			`end`
309			`else`
310			`begin`
311			if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_DC))
312			`begin`
313			`dc_ss <= debug_csr_write_data[0];`
314			if (debug_csr_write_data[0] == `FALSE)
315			state <= `LM32_DEBUG_SS_STATE_IDLE;
316			`else`
317			state <= `LM32_DEBUG_SS_STATE_WAIT_FOR_RET;
318			`end`
319			`case (state)`
320			`LM32_DEBUG_SS_STATE_WAIT_FOR_RET:
321			`begin`
322			`// Wait for eret or bret instruction to be executed`
323			if ( ( (eret_q_x == `TRUE)
324			\|\| (bret_q_x == `TRUE)
325			`)`
326			&& (stall_x == `FALSE)
327			`)`
328			state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN;
329			`end`
330			`LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN:
331			`begin`
332			`// Wait for an instruction to be executed`
333			if ((q_x == `TRUE) && (stall_x == `FALSE))
334			state <= `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT;
335			`end`
336			`LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT:
337			`begin`
338			`// Wait for exception to be raised`
339			`ifdef CFG_DCACHE_ENABLED
340			if (dcache_refill_request == `TRUE)
341			state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN;
342			`else`
343			`endif
344			if ((exception_x == `TRUE) && (q_x == `TRUE) && (stall_x == `FALSE))
345			`begin`
346			dc_ss <= `FALSE;
347			state <= `LM32_DEBUG_SS_STATE_RESTART;
348			`end`
349			`end`
350			`LM32_DEBUG_SS_STATE_RESTART:
351			`begin`
352			`// Watch to see if stepped instruction is restarted due to a cache miss`
353			`ifdef CFG_DCACHE_ENABLED
354			if (dcache_refill_request == `TRUE)
355			state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN;
356			`else`
357			`endif
358			state <= `LM32_DEBUG_SS_STATE_IDLE;
359			`end`
360			`endcase`
361			`end`
362			`end`
363			`endif
364
365			`endmodule`
366
367			`endif