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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [new_lm32/] [rtl/] [lm32_dp_ram.v] - Blame information for rev 48

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1 48 alirezamon 
/*
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 * LatticeMico32
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 * True dual-ported RAM
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 *
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 * Copyright (c) 2012 Michael Walle <michael@walle.cc>
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 * 1. Redistributions of source code must retain the above copyright
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 *    notice, this list of conditions and the following disclaimer.
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 * 2. Redistributions in binary form must reproduce the above copyright
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 *    notice, this list of conditions and the following disclaimer in the
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 *    documentation and/or other materials provided with the distribution.
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 * 3. The name of the author may not be used to endorse or promote products
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 *    derived from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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`include "lm32_include.v"
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/////////////////////////////////////////////////////
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// Module interface
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/////////////////////////////////////////////////////
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module lm32_dp_ram (
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    // ----- Inputs -------
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    clk_a,
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    clk_b,
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    ce_a,
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    ce_b,
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    addr_a,
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    addr_b,
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    di_a,
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    di_b,
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    we_a,
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    we_b,
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    // ----- Outputs -------
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    do_a,
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    do_b
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    );
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/////////////////////////////////////////////////////
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// Parameters
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/////////////////////////////////////////////////////
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parameter data_width = 1;               // Width of the data ports
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parameter address_width = 1;            // Width of the address ports
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parameter init_file = "NONE";           // Initialization file
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/////////////////////////////////////////////////////
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// Inputs
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/////////////////////////////////////////////////////
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input clk_a;                            // Clock port A
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input clk_b;                            // Clock port B
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input ce_a;                             // Clock enable port A
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input ce_b;                             // Clock enable port B
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input [address_width-1:0] addr_a;       // Read/write address port A
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input [address_width-1:0] addr_b;       // Read/write address port B
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input [data_width-1:0] di_a;            // Data input port A
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input [data_width-1:0] di_b;            // Data input port B
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input we_a;                             // Write enable port A
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input we_b;                             // Write enable port B
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/////////////////////////////////////////////////////
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// Outputs
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/////////////////////////////////////////////////////
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output [data_width-1:0] do_a;           // Data output port A
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wire   [data_width-1:0] do_a;
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output [data_width-1:0] do_b;           // Data output port B
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wire   [data_width-1:0] do_b;
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/////////////////////////////////////////////////////
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// Internal nets and registers
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/////////////////////////////////////////////////////
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reg [data_width-1:0]    mem[0:(1<<address_width)-1];
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reg [address_width-1:0] ra_a;           // Registered read address port A
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reg [address_width-1:0] ra_b;           // Registered read address port B
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/////////////////////////////////////////////////////
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// Functions
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/////////////////////////////////////////////////////
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////////////////////////////////////////////////////
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// Instantiations
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/////////////////////////////////////////////////////
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/////////////////////////////////////////////////////
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// Combinational logic
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/////////////////////////////////////////////////////
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// Read ports
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assign do_a = mem[ra_a];
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assign do_b = mem[ra_b];
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/////////////////////////////////////////////////////
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// Sequential logic
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/////////////////////////////////////////////////////
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// Write ports
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always @(posedge clk_a)
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    if ((ce_a == `TRUE) && (we_a == `TRUE))
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        mem[addr_a] <= di_a;
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always @(posedge clk_b)
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    if ((ce_b == `TRUE) && (we_b == `TRUE))
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        mem[addr_b] <= di_b;
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// Register read addresses for use on next cycle
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always @(posedge clk_a)
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    if (ce_a == `TRUE)
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        ra_a <= addr_a;
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always @(posedge clk_b)
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    if (ce_b == `TRUE)
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        ra_b <= addr_b;
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/////////////////////////////////////////////////////
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// Initialization
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/////////////////////////////////////////////////////
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generate
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    if (init_file != "NONE")
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    begin
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initial $readmemh(init_file, mem);
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    end
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endgenerate
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endmodule

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