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// ==================================================================
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// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
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// ------------------------------------------------------------------
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// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
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// ALL RIGHTS RESERVED
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// ------------------------------------------------------------------
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//
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// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
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//
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// Permission:
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//
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// Lattice Semiconductor grants permission to use this code
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// pursuant to the terms of the Lattice Semiconductor Corporation
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// Open Source License Agreement.
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//
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// Disclaimer:
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//
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// Lattice Semiconductor provides no warranty regarding the use or
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// functionality of this code. It is the user's responsibility to
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// verify the user's design for consistency and functionality through
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// the use of formal verification methods.
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//
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// --------------------------------------------------------------------
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//
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// Lattice Semiconductor Corporation
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// 5555 NE Moore Court
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// Hillsboro, OR 97214
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// U.S.A
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//
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// TEL: 1-800-Lattice (USA and Canada)
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// 503-286-8001 (other locations)
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//
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// web: http://www.latticesemi.com/
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// email: techsupport@latticesemi.com
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//
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// --------------------------------------------------------------------
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// FILE DETAILS
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// Project : LatticeMico32
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// File : lm32_load_store_unit.v
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// Title : Load and store unit
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// Dependencies : lm32_include.v
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// Version : 6.1.17
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// : Initial Release
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// Version : 7.0SP2, 3.0
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// : No Change
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// Version : 3.1
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// : Instead of disallowing an instruction cache miss on a data cache
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// : miss, both can now occur at the same time. If both occur at same
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// : time, then restart address is the address of instruction that
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// : caused data cache miss.
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// Version : 3.2
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// : EBRs use SYNC resets instead of ASYNC resets.
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// Version : 3.3
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// : Support for new non-cacheable Data Memory that is accessible by
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// : the data port and has a one cycle access latency.
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// Version : 3.4
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// : No change
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// Version : 3.5
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// : Bug fix: Inline memory is correctly generated if it is not a
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// : power-of-two
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// =============================================================================
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`include "lm32_include.v"
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/////////////////////////////////////////////////////
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// Module interface
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/////////////////////////////////////////////////////
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module lm32_load_store_unit (
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// ----- Inputs -------
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clk_i,
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rst_i,
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// From pipeline
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stall_a,
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stall_x,
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stall_m,
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kill_m,
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exception_m,
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store_operand_x,
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load_store_address_x,
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load_store_address_m,
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load_store_address_w,
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`ifdef CFG_MMU_ENABLED
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load_d,
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store_d,
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`endif
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load_x,
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store_x,
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load_q_x,
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store_q_x,
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load_q_m,
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store_q_m,
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sign_extend_x,
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size_x,
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`ifdef CFG_DCACHE_ENABLED
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dflush,
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`endif
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`ifdef CFG_IROM_ENABLED
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irom_data_m,
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`endif
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`ifdef CFG_MMU_ENABLED
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dtlb_enable,
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tlbpaddr,
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tlbvaddr,
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dtlb_update,
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dtlb_flush,
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dtlb_invalidate,
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`endif
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// From Wishbone
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d_dat_i,
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d_ack_i,
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d_err_i,
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d_rty_i,
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// ----- Outputs -------
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// To pipeline
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`ifdef CFG_DCACHE_ENABLED
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dcache_refill_request,
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dcache_restart_request,
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dcache_stall_request,
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dcache_refilling,
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`endif
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`ifdef CFG_IROM_ENABLED
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irom_store_data_m,
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irom_address_xm,
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irom_we_xm,
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irom_stall_request_x,
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`endif
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load_data_w,
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stall_wb_load,
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`ifdef CFG_MMU_ENABLED
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dtlb_stall_request,
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dtlb_miss_vfn,
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dtlb_miss_x,
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dtlb_fault_x,
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`endif
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// To Wishbone
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d_dat_o,
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d_adr_o,
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d_cyc_o,
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d_sel_o,
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d_stb_o,
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d_we_o,
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d_cti_o,
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d_lock_o,
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d_bte_o
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);
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/////////////////////////////////////////////////////
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// Parameters
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/////////////////////////////////////////////////////
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parameter associativity = 1; // Associativity of the cache (Number of ways)
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parameter sets = 512; // Number of sets
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parameter bytes_per_line = 16; // Number of bytes per cache line
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parameter base_address = 0; // Base address of cachable memory
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parameter limit = 0; // Limit (highest address) of cachable memory
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// For bytes_per_line == 4, we set 1 so part-select range isn't reversed, even though not really used
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localparam addr_offset_width = bytes_per_line == 4 ? 1 : `CLOG2(bytes_per_line)-2;
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localparam addr_offset_lsb = 2;
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localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
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/////////////////////////////////////////////////////
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// Inputs
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/////////////////////////////////////////////////////
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input clk_i; // Clock
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input rst_i; // Reset
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input stall_a; // A stage stall
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input stall_x; // X stage stall
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input stall_m; // M stage stall
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input kill_m; // Kill instruction in M stage
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input exception_m; // An exception occured in the M stage
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input [`LM32_WORD_RNG] store_operand_x; // Data read from register to store
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input [`LM32_WORD_RNG] load_store_address_x; // X stage load/store address
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input [`LM32_WORD_RNG] load_store_address_m; // M stage load/store address
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input [1:0] load_store_address_w; // W stage load/store address (only least two significant bits are needed)
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`ifdef CFG_MMU_ENABLED
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input load_d; // Load instruction in D stage
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input store_d; // Store instruction in D stage
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`endif
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input load_x; // Load instruction in X stage
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input store_x; // Store instruction in X stage
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input load_q_x; // Load instruction in X stage
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input store_q_x; // Store instruction in X stage
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input load_q_m; // Load instruction in M stage
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input store_q_m; // Store instruction in M stage
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input sign_extend_x; // Whether load instruction in X stage should sign extend or zero extend
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input [`LM32_SIZE_RNG] size_x; // Size of load or store (byte, hword, word)
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`ifdef CFG_DCACHE_ENABLED
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input dflush; // Flush the data cache
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`endif
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`ifdef CFG_IROM_ENABLED
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input [`LM32_WORD_RNG] irom_data_m; // Data from Instruction-ROM
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`endif
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`ifdef CFG_MMU_ENABLED
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input dtlb_enable; // Data TLB enable
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input [`LM32_WORD_RNG] tlbpaddr; // TLBPADDR CSR
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input [`LM32_WORD_RNG] tlbvaddr; // TLBVADDR CSR
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input dtlb_update; // Data TLB update
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input dtlb_flush; // Data TLB flush
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input dtlb_invalidate; // Data TLB invalidate
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`endif
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input [`LM32_WORD_RNG] d_dat_i; // Data Wishbone interface read data
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input d_ack_i; // Data Wishbone interface acknowledgement
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input d_err_i; // Data Wishbone interface error
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input d_rty_i; // Data Wishbone interface retry
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/////////////////////////////////////////////////////
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// Outputs
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/////////////////////////////////////////////////////
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`ifdef CFG_DCACHE_ENABLED
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output dcache_refill_request; // Request to refill data cache
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wire dcache_refill_request;
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output dcache_restart_request; // Request to restart the instruction that caused a data cache miss
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wire dcache_restart_request;
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output dcache_stall_request; // Data cache stall request
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wire dcache_stall_request;
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output dcache_refilling;
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wire dcache_refilling;
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`endif
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`ifdef CFG_IROM_ENABLED
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output [`LM32_WORD_RNG] irom_store_data_m; // Store data to Instruction ROM
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wire [`LM32_WORD_RNG] irom_store_data_m;
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output [`LM32_WORD_RNG] irom_address_xm; // Load/store address to Instruction ROM
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wire [`LM32_WORD_RNG] irom_address_xm;
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output irom_we_xm; // Write-enable of 2nd port of Instruction ROM
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wire irom_we_xm;
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output irom_stall_request_x; // Stall instruction in D stage
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wire irom_stall_request_x;
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`endif
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output [`LM32_WORD_RNG] load_data_w; // Result of a load instruction
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reg [`LM32_WORD_RNG] load_data_w;
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output stall_wb_load; // Request to stall pipeline due to a load from the Wishbone interface
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reg stall_wb_load;
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`ifdef CFG_MMU_ENABLED
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output dtlb_stall_request; // Data TLB stall request
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wire dtlb_stall_request;
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output [`LM32_WORD_RNG] dtlb_miss_vfn; // Virtual frame number of missed load or store address
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wire [`LM32_WORD_RNG] dtlb_miss_vfn;
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output dtlb_miss_x; // Indicates if a data TLB miss has occured
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wire dtlb_miss_x;
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output dtlb_fault_x; // Indicates if a data TLB fault has occured in X stage
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wire dtlb_fault_x;
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`endif
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output [`LM32_WORD_RNG] d_dat_o; // Data Wishbone interface write data
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reg [`LM32_WORD_RNG] d_dat_o;
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output [`LM32_WORD_RNG] d_adr_o; // Data Wishbone interface address
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reg [`LM32_WORD_RNG] d_adr_o;
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output d_cyc_o; // Data Wishbone interface cycle
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reg d_cyc_o;
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output [`LM32_BYTE_SELECT_RNG] d_sel_o; // Data Wishbone interface byte select
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reg [`LM32_BYTE_SELECT_RNG] d_sel_o;
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output d_stb_o; // Data Wishbone interface strobe
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reg d_stb_o;
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output d_we_o; // Data Wishbone interface write enable
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reg d_we_o;
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output [`LM32_CTYPE_RNG] d_cti_o; // Data Wishbone interface cycle type
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reg [`LM32_CTYPE_RNG] d_cti_o;
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output d_lock_o; // Date Wishbone interface lock bus
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reg d_lock_o;
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output [`LM32_BTYPE_RNG] d_bte_o; // Data Wishbone interface burst type
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wire [`LM32_BTYPE_RNG] d_bte_o;
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/////////////////////////////////////////////////////
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// Internal nets and registers
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/////////////////////////////////////////////////////
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// Microcode pipeline registers - See inputs for description
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reg [`LM32_SIZE_RNG] size_m;
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reg [`LM32_SIZE_RNG] size_w;
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reg sign_extend_m;
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reg sign_extend_w;
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reg [`LM32_WORD_RNG] store_data_x;
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reg [`LM32_WORD_RNG] store_data_m;
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reg [`LM32_BYTE_SELECT_RNG] byte_enable_x;
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reg [`LM32_BYTE_SELECT_RNG] byte_enable_m;
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wire [`LM32_WORD_RNG] data_m;
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reg [`LM32_WORD_RNG] data_w;
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`ifdef CFG_DCACHE_ENABLED
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wire dcache_select_x; // Select data cache to load from / store to
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reg dcache_select_m;
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wire [`LM32_WORD_RNG] dcache_data_m; // Data read from cache
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wire [`LM32_WORD_RNG] dcache_refill_address; // Address to refill data cache from
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reg dcache_refill_ready; // Indicates the next word of refill data is ready
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wire [`LM32_CTYPE_RNG] first_cycle_type; // First Wishbone cycle type
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wire [`LM32_CTYPE_RNG] next_cycle_type; // Next Wishbone cycle type
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wire last_word; // Indicates if this is the last word in the cache line
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wire [`LM32_WORD_RNG] first_address; // First cache refill address
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`endif
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`ifdef CFG_DRAM_ENABLED
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wire dram_select_x; // Select data RAM to load from / store to
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reg dram_select_m;
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reg dram_bypass_en; // RAW in data RAM; read latched (bypass) value rather than value from memory
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reg [`LM32_WORD_RNG] dram_bypass_data; // Latched value of store'd data to data RAM
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wire [`LM32_WORD_RNG] dram_data_out; // Data read from data RAM
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wire [`LM32_WORD_RNG] dram_data_m; // Data read from data RAM: bypass value or value from memory
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wire [`LM32_WORD_RNG] dram_store_data_m; // Data to write to RAM
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`endif
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wire wb_select_x; // Select Wishbone to load from / store to
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`ifdef CFG_IROM_ENABLED
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wire irom_select_x; // Select instruction ROM to load from / store to
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reg irom_select_m;
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`endif
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reg wb_select_m;
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reg [`LM32_WORD_RNG] wb_data_m; // Data read from Wishbone
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reg wb_load_complete; // Indicates when a Wishbone load is complete
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`ifdef CFG_MMU_ENABLED
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wire [`LM32_WORD_RNG] physical_load_store_address_m; // X stage physical load/store address
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wire cache_inhibit_x; // Indicates if data cache should be bypassed
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`endif
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/////////////////////////////////////////////////////
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// Functions
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327 |
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/////////////////////////////////////////////////////
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/////////////////////////////////////////////////////
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// Instantiations
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/////////////////////////////////////////////////////
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`ifdef CFG_DRAM_ENABLED
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|
|
`define LM32_DRAM_WIDTH `CLOG2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)
|
335 |
|
|
`define LM32_DRAM_RNG (`LM32_DRAM_WIDTH-1+2):2
|
336 |
|
|
|
337 |
|
|
// Data RAM
|
338 |
|
|
lm32_ram #(
|
339 |
|
|
.data_width (`LM32_WORD_WIDTH),
|
340 |
|
|
.address_width (`LM32_DRAM_WIDTH),
|
341 |
|
|
.init_file (`CFG_DRAM_INIT_FILE)
|
342 |
|
|
) ram (
|
343 |
|
|
// ----- Inputs -------
|
344 |
|
|
.read_clk (clk_i),
|
345 |
|
|
.write_clk (clk_i),
|
346 |
|
|
.reset (rst_i),
|
347 |
|
|
.enable_read (!stall_x),
|
348 |
|
|
.read_address (load_store_address_x[`LM32_DRAM_RNG]),
|
349 |
|
|
.enable_write (!stall_m),
|
350 |
|
|
.write_address (load_store_address_m[`LM32_DRAM_RNG]),
|
351 |
|
|
.write_data (dram_store_data_m),
|
352 |
|
|
.write_enable (store_q_m & dram_select_m),
|
353 |
|
|
// ----- Outputs -------
|
354 |
|
|
.read_data (dram_data_out)
|
355 |
|
|
);
|
356 |
|
|
|
357 |
|
|
/*----------------------------------------------------------------------
|
358 |
|
|
EBRs cannot perform reads from location 'written to' on the same clock
|
359 |
|
|
edge. Therefore bypass logic is required to latch the store'd value
|
360 |
|
|
and use it for the load (instead of value from memory).
|
361 |
|
|
----------------------------------------------------------------------*/
|
362 |
|
|
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
|
363 |
|
|
if (rst_i == `TRUE)
|
364 |
|
|
begin
|
365 |
|
|
dram_bypass_en <= `FALSE;
|
366 |
|
|
dram_bypass_data <= 0;
|
367 |
|
|
end
|
368 |
|
|
else
|
369 |
|
|
begin
|
370 |
|
|
if (stall_x == `FALSE)
|
371 |
|
|
dram_bypass_data <= dram_store_data_m;
|
372 |
|
|
|
373 |
|
|
if ( (stall_m == `FALSE)
|
374 |
|
|
&& (stall_x == `FALSE)
|
375 |
|
|
&& (store_q_m == `TRUE)
|
376 |
|
|
&& ( (load_x == `TRUE)
|
377 |
|
|
|| (store_x == `TRUE)
|
378 |
|
|
)
|
379 |
|
|
&& (load_store_address_x[(`LM32_WORD_WIDTH-1):2] == load_store_address_m[(`LM32_WORD_WIDTH-1):2])
|
380 |
|
|
)
|
381 |
|
|
dram_bypass_en <= `TRUE;
|
382 |
|
|
else
|
383 |
|
|
if ( (dram_bypass_en == `TRUE)
|
384 |
|
|
&& (stall_x == `FALSE)
|
385 |
|
|
)
|
386 |
|
|
dram_bypass_en <= `FALSE;
|
387 |
|
|
end
|
388 |
|
|
|
389 |
|
|
assign dram_data_m = dram_bypass_en ? dram_bypass_data : dram_data_out;
|
390 |
|
|
`endif
|
391 |
|
|
|
392 |
|
|
`ifdef CFG_DCACHE_ENABLED
|
393 |
|
|
// Data cache
|
394 |
|
|
lm32_dcache #(
|
395 |
|
|
.associativity (associativity),
|
396 |
|
|
.sets (sets),
|
397 |
|
|
.bytes_per_line (bytes_per_line),
|
398 |
|
|
.base_address (base_address),
|
399 |
|
|
.limit (limit)
|
400 |
|
|
) dcache (
|
401 |
|
|
// ----- Inputs -----
|
402 |
|
|
.clk_i (clk_i),
|
403 |
|
|
.rst_i (rst_i),
|
404 |
|
|
.stall_a (stall_a),
|
405 |
|
|
.stall_x (stall_x),
|
406 |
|
|
.stall_m (stall_m),
|
407 |
|
|
.address_x (load_store_address_x),
|
408 |
|
|
`ifdef CFG_MMU_ENABLED
|
409 |
|
|
/* VIPT cache, address_m is (only) used for tag */
|
410 |
|
|
.address_m (physical_load_store_address_m),
|
411 |
|
|
`else
|
412 |
|
|
.address_m (load_store_address_m),
|
413 |
|
|
`endif
|
414 |
|
|
.load_q_m (load_q_m & dcache_select_m),
|
415 |
|
|
.store_q_m (store_q_m & dcache_select_m),
|
416 |
|
|
.store_data (store_data_m),
|
417 |
|
|
.store_byte_select (byte_enable_m & {4{dcache_select_m}}),
|
418 |
|
|
.refill_ready (dcache_refill_ready),
|
419 |
|
|
.refill_data (wb_data_m),
|
420 |
|
|
.dflush (dflush),
|
421 |
|
|
`ifdef CFG_MMU_ENABLED
|
422 |
|
|
.dtlb_miss_x (dtlb_miss_x),
|
423 |
|
|
`endif
|
424 |
|
|
// ----- Outputs -----
|
425 |
|
|
.stall_request (dcache_stall_request),
|
426 |
|
|
.restart_request (dcache_restart_request),
|
427 |
|
|
.refill_request (dcache_refill_request),
|
428 |
|
|
.refill_address (dcache_refill_address),
|
429 |
|
|
.refilling (dcache_refilling),
|
430 |
|
|
.load_data (dcache_data_m)
|
431 |
|
|
);
|
432 |
|
|
`endif
|
433 |
|
|
|
434 |
|
|
`ifdef CFG_MMU_ENABLED
|
435 |
|
|
// Data TLB
|
436 |
|
|
lm32_dtlb dtlb (
|
437 |
|
|
// ----- Inputs -----
|
438 |
|
|
.clk_i (clk_i),
|
439 |
|
|
.rst_i (rst_i),
|
440 |
|
|
.enable (dtlb_enable),
|
441 |
|
|
.stall_x (stall_x),
|
442 |
|
|
.stall_m (stall_m),
|
443 |
|
|
.address_x (load_store_address_x),
|
444 |
|
|
.address_m (load_store_address_m),
|
445 |
|
|
.load_d (load_d),
|
446 |
|
|
.store_d (store_d),
|
447 |
|
|
.load_q_x (load_q_x),
|
448 |
|
|
.store_q_x (store_q_x),
|
449 |
|
|
.tlbpaddr (tlbpaddr),
|
450 |
|
|
.tlbvaddr (tlbvaddr),
|
451 |
|
|
.update (dtlb_update),
|
452 |
|
|
.flush (dtlb_flush),
|
453 |
|
|
.invalidate (dtlb_invalidate),
|
454 |
|
|
// ----- Outputs -----
|
455 |
|
|
.physical_load_store_address_m (physical_load_store_address_m),
|
456 |
|
|
.stall_request (dtlb_stall_request),
|
457 |
|
|
.miss_vfn (dtlb_miss_vfn),
|
458 |
|
|
.miss_x (dtlb_miss_x),
|
459 |
|
|
.fault_x (dtlb_fault_x),
|
460 |
|
|
.cache_inhibit_x (cache_inhibit_x)
|
461 |
|
|
);
|
462 |
|
|
`endif
|
463 |
|
|
|
464 |
|
|
/////////////////////////////////////////////////////
|
465 |
|
|
// Combinational Logic
|
466 |
|
|
/////////////////////////////////////////////////////
|
467 |
|
|
|
468 |
|
|
// Select where data should be loaded from / stored to
|
469 |
|
|
`ifdef CFG_DRAM_ENABLED
|
470 |
|
|
assign dram_select_x = (load_store_address_x >= `CFG_DRAM_BASE_ADDRESS)
|
471 |
|
|
&& (load_store_address_x <= `CFG_DRAM_LIMIT);
|
472 |
|
|
`endif
|
473 |
|
|
|
474 |
|
|
`ifdef CFG_IROM_ENABLED
|
475 |
|
|
assign irom_select_x = (load_store_address_x >= `CFG_IROM_BASE_ADDRESS)
|
476 |
|
|
&& (load_store_address_x <= `CFG_IROM_LIMIT);
|
477 |
|
|
`endif
|
478 |
|
|
|
479 |
|
|
`ifdef CFG_DCACHE_ENABLED
|
480 |
|
|
assign dcache_select_x = (load_store_address_x >= `CFG_DCACHE_BASE_ADDRESS)
|
481 |
|
|
&& (load_store_address_x <= `CFG_DCACHE_LIMIT)
|
482 |
|
|
`ifdef CFG_DRAM_ENABLED
|
483 |
|
|
&& (dram_select_x == `FALSE)
|
484 |
|
|
`endif
|
485 |
|
|
`ifdef CFG_IROM_ENABLED
|
486 |
|
|
&& (irom_select_x == `FALSE)
|
487 |
|
|
`endif
|
488 |
|
|
`ifdef CFG_MMU_ENABLED
|
489 |
|
|
&& (cache_inhibit_x == `FALSE)
|
490 |
|
|
`endif
|
491 |
|
|
;
|
492 |
|
|
`endif
|
493 |
|
|
|
494 |
|
|
assign wb_select_x = `TRUE
|
495 |
|
|
`ifdef CFG_DCACHE_ENABLED
|
496 |
|
|
&& !dcache_select_x
|
497 |
|
|
`endif
|
498 |
|
|
`ifdef CFG_DRAM_ENABLED
|
499 |
|
|
&& !dram_select_x
|
500 |
|
|
`endif
|
501 |
|
|
`ifdef CFG_IROM_ENABLED
|
502 |
|
|
&& !irom_select_x
|
503 |
|
|
`endif
|
504 |
|
|
;
|
505 |
|
|
|
506 |
|
|
// Make sure data to store is in correct byte lane
|
507 |
|
|
always @(*)
|
508 |
|
|
begin
|
509 |
|
|
case (size_x)
|
510 |
|
|
`LM32_SIZE_BYTE: store_data_x = {4{store_operand_x[7:0]}};
|
511 |
|
|
`LM32_SIZE_HWORD: store_data_x = {2{store_operand_x[15:0]}};
|
512 |
|
|
`LM32_SIZE_WORD: store_data_x = store_operand_x;
|
513 |
|
|
default: store_data_x = {`LM32_WORD_WIDTH{1'bx}};
|
514 |
|
|
endcase
|
515 |
|
|
end
|
516 |
|
|
|
517 |
|
|
// Generate byte enable accoring to size of load or store and address being accessed
|
518 |
|
|
always @(*)
|
519 |
|
|
begin
|
520 |
|
|
casez ({size_x, load_store_address_x[1:0]})
|
521 |
|
|
{`LM32_SIZE_BYTE, 2'b11}: byte_enable_x = 4'b0001;
|
522 |
|
|
{`LM32_SIZE_BYTE, 2'b10}: byte_enable_x = 4'b0010;
|
523 |
|
|
{`LM32_SIZE_BYTE, 2'b01}: byte_enable_x = 4'b0100;
|
524 |
|
|
{`LM32_SIZE_BYTE, 2'b00}: byte_enable_x = 4'b1000;
|
525 |
|
|
{`LM32_SIZE_HWORD, 2'b1?}: byte_enable_x = 4'b0011;
|
526 |
|
|
{`LM32_SIZE_HWORD, 2'b0?}: byte_enable_x = 4'b1100;
|
527 |
|
|
{`LM32_SIZE_WORD, 2'b??}: byte_enable_x = 4'b1111;
|
528 |
|
|
default: byte_enable_x = 4'bxxxx;
|
529 |
|
|
endcase
|
530 |
|
|
end
|
531 |
|
|
|
532 |
|
|
`ifdef CFG_DRAM_ENABLED
|
533 |
|
|
// Only replace selected bytes
|
534 |
|
|
assign dram_store_data_m[`LM32_BYTE_0_RNG] = byte_enable_m[0] ? store_data_m[`LM32_BYTE_0_RNG] : dram_data_m[`LM32_BYTE_0_RNG];
|
535 |
|
|
assign dram_store_data_m[`LM32_BYTE_1_RNG] = byte_enable_m[1] ? store_data_m[`LM32_BYTE_1_RNG] : dram_data_m[`LM32_BYTE_1_RNG];
|
536 |
|
|
assign dram_store_data_m[`LM32_BYTE_2_RNG] = byte_enable_m[2] ? store_data_m[`LM32_BYTE_2_RNG] : dram_data_m[`LM32_BYTE_2_RNG];
|
537 |
|
|
assign dram_store_data_m[`LM32_BYTE_3_RNG] = byte_enable_m[3] ? store_data_m[`LM32_BYTE_3_RNG] : dram_data_m[`LM32_BYTE_3_RNG];
|
538 |
|
|
`endif
|
539 |
|
|
|
540 |
|
|
`ifdef CFG_IROM_ENABLED
|
541 |
|
|
// Only replace selected bytes
|
542 |
|
|
assign irom_store_data_m[`LM32_BYTE_0_RNG] = byte_enable_m[0] ? store_data_m[`LM32_BYTE_0_RNG] : irom_data_m[`LM32_BYTE_0_RNG];
|
543 |
|
|
assign irom_store_data_m[`LM32_BYTE_1_RNG] = byte_enable_m[1] ? store_data_m[`LM32_BYTE_1_RNG] : irom_data_m[`LM32_BYTE_1_RNG];
|
544 |
|
|
assign irom_store_data_m[`LM32_BYTE_2_RNG] = byte_enable_m[2] ? store_data_m[`LM32_BYTE_2_RNG] : irom_data_m[`LM32_BYTE_2_RNG];
|
545 |
|
|
assign irom_store_data_m[`LM32_BYTE_3_RNG] = byte_enable_m[3] ? store_data_m[`LM32_BYTE_3_RNG] : irom_data_m[`LM32_BYTE_3_RNG];
|
546 |
|
|
`endif
|
547 |
|
|
|
548 |
|
|
`ifdef CFG_IROM_ENABLED
|
549 |
|
|
// Instead of implementing a byte-addressable instruction ROM (for store byte instruction),
|
550 |
|
|
// a load-and-store architecture is used wherein a 32-bit value is loaded, the requisite
|
551 |
|
|
// byte is replaced, and the whole 32-bit value is written back
|
552 |
|
|
|
553 |
|
|
assign irom_address_xm = ((irom_select_m == `TRUE) && (store_q_m == `TRUE))
|
554 |
|
|
? load_store_address_m
|
555 |
|
|
: load_store_address_x;
|
556 |
|
|
|
557 |
|
|
// All store instructions perform a write operation in the M stage
|
558 |
|
|
assign irom_we_xm = (irom_select_m == `TRUE)
|
559 |
|
|
&& (store_q_m == `TRUE);
|
560 |
|
|
|
561 |
|
|
// A single port in instruction ROM is available to load-store unit for doing loads/stores.
|
562 |
|
|
// Since every store requires a load (in X stage) and then a store (in M stage), we cannot
|
563 |
|
|
// allow load (or store) instructions sequentially after the store instructions to proceed
|
564 |
|
|
// until the store instruction has vacated M stage (i.e., completed the store operation)
|
565 |
|
|
assign irom_stall_request_x = (irom_select_x == `TRUE)
|
566 |
|
|
&& (store_q_x == `TRUE);
|
567 |
|
|
`endif
|
568 |
|
|
|
569 |
|
|
`ifdef CFG_DCACHE_ENABLED
|
570 |
|
|
`ifdef CFG_DRAM_ENABLED
|
571 |
|
|
`ifdef CFG_IROM_ENABLED
|
572 |
|
|
// WB + DC + DRAM + IROM
|
573 |
|
|
assign data_m = wb_select_m == `TRUE
|
574 |
|
|
? wb_data_m
|
575 |
|
|
: dram_select_m == `TRUE
|
576 |
|
|
? dram_data_m
|
577 |
|
|
: irom_select_m == `TRUE
|
578 |
|
|
? irom_data_m
|
579 |
|
|
: dcache_data_m;
|
580 |
|
|
`else
|
581 |
|
|
// WB + DC + DRAM
|
582 |
|
|
assign data_m = wb_select_m == `TRUE
|
583 |
|
|
? wb_data_m
|
584 |
|
|
: dram_select_m == `TRUE
|
585 |
|
|
? dram_data_m
|
586 |
|
|
: dcache_data_m;
|
587 |
|
|
`endif
|
588 |
|
|
`else
|
589 |
|
|
`ifdef CFG_IROM_ENABLED
|
590 |
|
|
// WB + DC + IROM
|
591 |
|
|
assign data_m = wb_select_m == `TRUE
|
592 |
|
|
? wb_data_m
|
593 |
|
|
: irom_select_m == `TRUE
|
594 |
|
|
? irom_data_m
|
595 |
|
|
: dcache_data_m;
|
596 |
|
|
`else
|
597 |
|
|
// WB + DC
|
598 |
|
|
assign data_m = wb_select_m == `TRUE
|
599 |
|
|
? wb_data_m
|
600 |
|
|
: dcache_data_m;
|
601 |
|
|
`endif
|
602 |
|
|
`endif
|
603 |
|
|
`else
|
604 |
|
|
`ifdef CFG_DRAM_ENABLED
|
605 |
|
|
`ifdef CFG_IROM_ENABLED
|
606 |
|
|
// WB + DRAM + IROM
|
607 |
|
|
assign data_m = wb_select_m == `TRUE
|
608 |
|
|
? wb_data_m
|
609 |
|
|
: dram_select_m == `TRUE
|
610 |
|
|
? dram_data_m
|
611 |
|
|
: irom_data_m;
|
612 |
|
|
`else
|
613 |
|
|
// WB + DRAM
|
614 |
|
|
assign data_m = wb_select_m == `TRUE
|
615 |
|
|
? wb_data_m
|
616 |
|
|
: dram_data_m;
|
617 |
|
|
`endif
|
618 |
|
|
`else
|
619 |
|
|
`ifdef CFG_IROM_ENABLED
|
620 |
|
|
// WB + IROM
|
621 |
|
|
assign data_m = wb_select_m == `TRUE
|
622 |
|
|
? wb_data_m
|
623 |
|
|
: irom_data_m;
|
624 |
|
|
`else
|
625 |
|
|
// WB
|
626 |
|
|
assign data_m = wb_data_m;
|
627 |
|
|
`endif
|
628 |
|
|
`endif
|
629 |
|
|
`endif
|
630 |
|
|
|
631 |
|
|
// Sub-word selection and sign/zero-extension for loads
|
632 |
|
|
always @(*)
|
633 |
|
|
begin
|
634 |
|
|
casez ({size_w, load_store_address_w[1:0]})
|
635 |
|
|
{`LM32_SIZE_BYTE, 2'b11}: load_data_w = {{24{sign_extend_w & data_w[7]}}, data_w[7:0]};
|
636 |
|
|
{`LM32_SIZE_BYTE, 2'b10}: load_data_w = {{24{sign_extend_w & data_w[15]}}, data_w[15:8]};
|
637 |
|
|
{`LM32_SIZE_BYTE, 2'b01}: load_data_w = {{24{sign_extend_w & data_w[23]}}, data_w[23:16]};
|
638 |
|
|
{`LM32_SIZE_BYTE, 2'b00}: load_data_w = {{24{sign_extend_w & data_w[31]}}, data_w[31:24]};
|
639 |
|
|
{`LM32_SIZE_HWORD, 2'b1?}: load_data_w = {{16{sign_extend_w & data_w[15]}}, data_w[15:0]};
|
640 |
|
|
{`LM32_SIZE_HWORD, 2'b0?}: load_data_w = {{16{sign_extend_w & data_w[31]}}, data_w[31:16]};
|
641 |
|
|
{`LM32_SIZE_WORD, 2'b??}: load_data_w = data_w;
|
642 |
|
|
default: load_data_w = {`LM32_WORD_WIDTH{1'bx}};
|
643 |
|
|
endcase
|
644 |
|
|
end
|
645 |
|
|
|
646 |
|
|
// Unused/constant Wishbone signals
|
647 |
|
|
assign d_bte_o = `LM32_BTYPE_LINEAR;
|
648 |
|
|
|
649 |
|
|
`ifdef CFG_DCACHE_ENABLED
|
650 |
|
|
// Generate signal to indicate last word in cache line
|
651 |
|
|
generate
|
652 |
|
|
case (bytes_per_line)
|
653 |
|
|
4:
|
654 |
|
|
begin
|
655 |
|
|
assign first_cycle_type = `LM32_CTYPE_END;
|
656 |
|
|
assign next_cycle_type = `LM32_CTYPE_END;
|
657 |
|
|
assign last_word = `TRUE;
|
658 |
|
|
assign first_address = {dcache_refill_address[`LM32_WORD_WIDTH-1:2], 2'b00};
|
659 |
|
|
end
|
660 |
|
|
8:
|
661 |
|
|
begin
|
662 |
|
|
assign first_cycle_type = `LM32_CTYPE_INCREMENTING;
|
663 |
|
|
assign next_cycle_type = `LM32_CTYPE_END;
|
664 |
|
|
assign last_word = (&d_adr_o[addr_offset_msb:addr_offset_lsb]) == 1'b1;
|
665 |
|
|
assign first_address = {dcache_refill_address[`LM32_WORD_WIDTH-1:addr_offset_msb+1], {addr_offset_width{1'b0}}, 2'b00};
|
666 |
|
|
end
|
667 |
|
|
default:
|
668 |
|
|
begin
|
669 |
|
|
assign first_cycle_type = `LM32_CTYPE_INCREMENTING;
|
670 |
|
|
assign next_cycle_type = d_adr_o[addr_offset_msb:addr_offset_lsb+1] == {addr_offset_width-1{1'b1}} ? `LM32_CTYPE_END : `LM32_CTYPE_INCREMENTING;
|
671 |
|
|
assign last_word = (&d_adr_o[addr_offset_msb:addr_offset_lsb]) == 1'b1;
|
672 |
|
|
assign first_address = {dcache_refill_address[`LM32_WORD_WIDTH-1:addr_offset_msb+1], {addr_offset_width{1'b0}}, 2'b00};
|
673 |
|
|
end
|
674 |
|
|
endcase
|
675 |
|
|
endgenerate
|
676 |
|
|
`endif
|
677 |
|
|
|
678 |
|
|
/////////////////////////////////////////////////////
|
679 |
|
|
// Sequential Logic
|
680 |
|
|
/////////////////////////////////////////////////////
|
681 |
|
|
|
682 |
|
|
// Data Wishbone interface
|
683 |
|
|
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
|
684 |
|
|
begin
|
685 |
|
|
if (rst_i == `TRUE)
|
686 |
|
|
begin
|
687 |
|
|
d_cyc_o <= `FALSE;
|
688 |
|
|
d_stb_o <= `FALSE;
|
689 |
|
|
d_dat_o <= {`LM32_WORD_WIDTH{1'b0}};
|
690 |
|
|
d_adr_o <= {`LM32_WORD_WIDTH{1'b0}};
|
691 |
|
|
d_sel_o <= {`LM32_BYTE_SELECT_WIDTH{`FALSE}};
|
692 |
|
|
d_we_o <= `FALSE;
|
693 |
|
|
d_cti_o <= `LM32_CTYPE_END;
|
694 |
|
|
d_lock_o <= `FALSE;
|
695 |
|
|
wb_data_m <= {`LM32_WORD_WIDTH{1'b0}};
|
696 |
|
|
wb_load_complete <= `FALSE;
|
697 |
|
|
stall_wb_load <= `FALSE;
|
698 |
|
|
`ifdef CFG_DCACHE_ENABLED
|
699 |
|
|
dcache_refill_ready <= `FALSE;
|
700 |
|
|
`endif
|
701 |
|
|
end
|
702 |
|
|
else
|
703 |
|
|
begin
|
704 |
|
|
`ifdef CFG_DCACHE_ENABLED
|
705 |
|
|
// Refill ready should only be asserted for a single cycle
|
706 |
|
|
dcache_refill_ready <= `FALSE;
|
707 |
|
|
`endif
|
708 |
|
|
// Is a Wishbone cycle already in progress?
|
709 |
|
|
if (d_cyc_o == `TRUE)
|
710 |
|
|
begin
|
711 |
|
|
// Is the cycle complete?
|
712 |
|
|
if ((d_ack_i == `TRUE) || (d_err_i == `TRUE))
|
713 |
|
|
begin
|
714 |
|
|
`ifdef CFG_DCACHE_ENABLED
|
715 |
|
|
if ((dcache_refilling == `TRUE) && (!last_word))
|
716 |
|
|
begin
|
717 |
|
|
// Fetch next word of cache line
|
718 |
|
|
d_adr_o[addr_offset_msb:addr_offset_lsb] <= d_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1;
|
719 |
|
|
end
|
720 |
|
|
else
|
721 |
|
|
`endif
|
722 |
|
|
begin
|
723 |
|
|
// Refill/access complete
|
724 |
|
|
d_cyc_o <= `FALSE;
|
725 |
|
|
d_stb_o <= `FALSE;
|
726 |
|
|
d_lock_o <= `FALSE;
|
727 |
|
|
end
|
728 |
|
|
`ifdef CFG_DCACHE_ENABLED
|
729 |
|
|
d_cti_o <= next_cycle_type;
|
730 |
|
|
// If we are performing a refill, indicate to cache next word of data is ready
|
731 |
|
|
dcache_refill_ready <= dcache_refilling;
|
732 |
|
|
`endif
|
733 |
|
|
// Register data read from Wishbone interface
|
734 |
|
|
wb_data_m <= d_dat_i;
|
735 |
|
|
// Don't set when stores complete - otherwise we'll deadlock if load in m stage
|
736 |
|
|
wb_load_complete <= !d_we_o;
|
737 |
|
|
end
|
738 |
|
|
// synthesis translate_off
|
739 |
|
|
if (d_err_i == `TRUE)
|
740 |
|
|
$display ("Data bus error. Address: %x", d_adr_o);
|
741 |
|
|
// synthesis translate_on
|
742 |
|
|
end
|
743 |
|
|
else
|
744 |
|
|
begin
|
745 |
|
|
`ifdef CFG_DCACHE_ENABLED
|
746 |
|
|
if (dcache_refill_request == `TRUE)
|
747 |
|
|
begin
|
748 |
|
|
// Start cache refill
|
749 |
|
|
d_adr_o <= first_address;
|
750 |
|
|
d_cyc_o <= `TRUE;
|
751 |
|
|
d_sel_o <= {`LM32_WORD_WIDTH/8{`TRUE}};
|
752 |
|
|
d_stb_o <= `TRUE;
|
753 |
|
|
d_we_o <= `FALSE;
|
754 |
|
|
d_cti_o <= first_cycle_type;
|
755 |
|
|
//d_lock_o <= `TRUE;
|
756 |
|
|
end
|
757 |
|
|
else
|
758 |
|
|
`endif
|
759 |
|
|
if ( (store_q_m == `TRUE)
|
760 |
|
|
&& (stall_m == `FALSE)
|
761 |
|
|
`ifdef CFG_DRAM_ENABLED
|
762 |
|
|
&& (dram_select_m == `FALSE)
|
763 |
|
|
`endif
|
764 |
|
|
`ifdef CFG_IROM_ENABLED
|
765 |
|
|
&& (irom_select_m == `FALSE)
|
766 |
|
|
`endif
|
767 |
|
|
)
|
768 |
|
|
begin
|
769 |
|
|
// Data cache is write through, so all stores go to memory
|
770 |
|
|
d_dat_o <= store_data_m;
|
771 |
|
|
d_adr_o <=
|
772 |
|
|
`ifdef CFG_MMU_ENABLED
|
773 |
|
|
(dtlb_enable) ? physical_load_store_address_m :
|
774 |
|
|
`endif
|
775 |
|
|
load_store_address_m;
|
776 |
|
|
d_cyc_o <= `TRUE;
|
777 |
|
|
d_sel_o <= byte_enable_m;
|
778 |
|
|
d_stb_o <= `TRUE;
|
779 |
|
|
d_we_o <= `TRUE;
|
780 |
|
|
d_cti_o <= `LM32_CTYPE_END;
|
781 |
|
|
end
|
782 |
|
|
else if ( (load_q_m == `TRUE)
|
783 |
|
|
&& (wb_select_m == `TRUE)
|
784 |
|
|
&& (wb_load_complete == `FALSE)
|
785 |
|
|
// stall_m will be TRUE, because stall_wb_load will be TRUE
|
786 |
|
|
)
|
787 |
|
|
begin
|
788 |
|
|
// Read requested address
|
789 |
|
|
stall_wb_load <= `FALSE;
|
790 |
|
|
d_adr_o <=
|
791 |
|
|
`ifdef CFG_MMU_ENABLED
|
792 |
|
|
(dtlb_enable) ? physical_load_store_address_m :
|
793 |
|
|
`endif
|
794 |
|
|
load_store_address_m;
|
795 |
|
|
d_cyc_o <= `TRUE;
|
796 |
|
|
d_sel_o <= byte_enable_m;
|
797 |
|
|
d_stb_o <= `TRUE;
|
798 |
|
|
d_we_o <= `FALSE;
|
799 |
|
|
d_cti_o <= `LM32_CTYPE_END;
|
800 |
|
|
end
|
801 |
|
|
end
|
802 |
|
|
// Clear load/store complete flag when instruction leaves M stage
|
803 |
|
|
if (stall_m == `FALSE)
|
804 |
|
|
wb_load_complete <= `FALSE;
|
805 |
|
|
// When a Wishbone load first enters the M stage, we need to stall it
|
806 |
|
|
if ((load_q_x == `TRUE) && (wb_select_x == `TRUE) && (stall_x == `FALSE))
|
807 |
|
|
stall_wb_load <= `TRUE;
|
808 |
|
|
// Clear stall request if load instruction is killed
|
809 |
|
|
if ((kill_m == `TRUE) || (exception_m == `TRUE))
|
810 |
|
|
stall_wb_load <= `FALSE;
|
811 |
|
|
end
|
812 |
|
|
end
|
813 |
|
|
|
814 |
|
|
// Pipeline registers
|
815 |
|
|
|
816 |
|
|
// X/M stage pipeline registers
|
817 |
|
|
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
|
818 |
|
|
begin
|
819 |
|
|
if (rst_i == `TRUE)
|
820 |
|
|
begin
|
821 |
|
|
sign_extend_m <= `FALSE;
|
822 |
|
|
size_m <= 2'b00;
|
823 |
|
|
byte_enable_m <= `FALSE;
|
824 |
|
|
store_data_m <= {`LM32_WORD_WIDTH{1'b0}};
|
825 |
|
|
`ifdef CFG_DCACHE_ENABLED
|
826 |
|
|
dcache_select_m <= `FALSE;
|
827 |
|
|
`endif
|
828 |
|
|
`ifdef CFG_DRAM_ENABLED
|
829 |
|
|
dram_select_m <= `FALSE;
|
830 |
|
|
`endif
|
831 |
|
|
`ifdef CFG_IROM_ENABLED
|
832 |
|
|
irom_select_m <= `FALSE;
|
833 |
|
|
`endif
|
834 |
|
|
wb_select_m <= `FALSE;
|
835 |
|
|
end
|
836 |
|
|
else
|
837 |
|
|
begin
|
838 |
|
|
if (stall_m == `FALSE)
|
839 |
|
|
begin
|
840 |
|
|
sign_extend_m <= sign_extend_x;
|
841 |
|
|
size_m <= size_x;
|
842 |
|
|
byte_enable_m <= byte_enable_x;
|
843 |
|
|
store_data_m <= store_data_x;
|
844 |
|
|
`ifdef CFG_DCACHE_ENABLED
|
845 |
|
|
dcache_select_m <= dcache_select_x;
|
846 |
|
|
`endif
|
847 |
|
|
`ifdef CFG_DRAM_ENABLED
|
848 |
|
|
dram_select_m <= dram_select_x;
|
849 |
|
|
`endif
|
850 |
|
|
`ifdef CFG_IROM_ENABLED
|
851 |
|
|
irom_select_m <= irom_select_x;
|
852 |
|
|
`endif
|
853 |
|
|
wb_select_m <= wb_select_x;
|
854 |
|
|
end
|
855 |
|
|
end
|
856 |
|
|
end
|
857 |
|
|
|
858 |
|
|
// M/W stage pipeline registers
|
859 |
|
|
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
|
860 |
|
|
begin
|
861 |
|
|
if (rst_i == `TRUE)
|
862 |
|
|
begin
|
863 |
|
|
size_w <= 2'b00;
|
864 |
|
|
data_w <= {`LM32_WORD_WIDTH{1'b0}};
|
865 |
|
|
sign_extend_w <= `FALSE;
|
866 |
|
|
end
|
867 |
|
|
else
|
868 |
|
|
begin
|
869 |
|
|
size_w <= size_m;
|
870 |
|
|
data_w <= data_m;
|
871 |
|
|
sign_extend_w <= sign_extend_m;
|
872 |
|
|
end
|
873 |
|
|
end
|
874 |
|
|
|
875 |
|
|
/////////////////////////////////////////////////////
|
876 |
|
|
// Behavioural Logic
|
877 |
|
|
/////////////////////////////////////////////////////
|
878 |
|
|
|
879 |
|
|
// synthesis translate_off
|
880 |
|
|
|
881 |
|
|
// Check for non-aligned loads or stores
|
882 |
|
|
always @(posedge clk_i)
|
883 |
|
|
begin
|
884 |
|
|
if (((load_q_m == `TRUE) || (store_q_m == `TRUE)) && (stall_m == `FALSE))
|
885 |
|
|
begin
|
886 |
|
|
if ((size_m === `LM32_SIZE_HWORD) && (load_store_address_m[0] !== 1'b0))
|
887 |
|
|
$display ("Warning: Non-aligned halfword access. Address: 0x%0x Time: %0t.", load_store_address_m, $time);
|
888 |
|
|
if ((size_m === `LM32_SIZE_WORD) && (load_store_address_m[1:0] !== 2'b00))
|
889 |
|
|
$display ("Warning: Non-aligned word access. Address: 0x%0x Time: %0t.", load_store_address_m, $time);
|
890 |
|
|
end
|
891 |
|
|
end
|
892 |
|
|
|
893 |
|
|
// synthesis translate_on
|
894 |
|
|
|
895 |
|
|
endmodule
|