URL https://opencores.org/ocsvn/ao486/ao486/trunk

Subversion Repositories ao486

[/] [ao486/] [trunk/] [bochs486/] [cpu/] [bit16.cc] - Blame information for rev 2

Details | Compare with Previous | View Log


/////////////////////////////////////////////////////////////////////////
// $Id: bit16.cc 11437 2012-09-21 14:56:56Z sshwarts $
/////////////////////////////////////////////////////////////////////////
//
//  Copyright (C) 2001-2012  The Bochs Project
//
//  This library is free software; you can redistribute it and/or
//  modify it under the terms of the GNU Lesser General Public
//  License as published by the Free Software Foundation; either
//  version 2 of the License, or (at your option) any later version.
//
//  This library is distributed in the hope that it will be useful,
//  but WITHOUT ANY WARRANTY; without even the implied warranty of
//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
//  Lesser General Public License for more details.
//
//  You should have received a copy of the GNU Lesser General Public
//  License along with this library; if not, write to the Free Software
//  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
/////////////////////////////////////////////////////////////////////////
 
#define NEED_CPU_REG_SHORTCUTS 1
#include "bochs.h"
#include "cpu.h"
#define LOG_THIS BX_CPU_THIS_PTR
 
#if BX_CPU_LEVEL >= 3
 
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BSF_GwEwR(bxInstruction_c *i)
{
  Bit16u op2_16 = BX_READ_16BIT_REG(i->src());
 
  if (op2_16 == 0) {
    assert_ZF(); /* op1_16 undefined */
  }
  else {
    Bit16u op1_16 = 0;
    while ((op2_16 & 0x01) == 0) {
      op1_16++;
      op2_16 >>= 1;
    }
 
    SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
    clear_ZF();
 
    BX_WRITE_16BIT_REG(i->dst(), op1_16);
  }
 
  BX_NEXT_INSTR(i);
}
 
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BSR_GwEwR(bxInstruction_c *i)
{
  Bit16u op2_16 = BX_READ_16BIT_REG(i->src());
 
  if (op2_16 == 0) {
    assert_ZF(); /* op1_16 undefined */
  }
  else {
    Bit16u op1_16 = 15;
    while ((op2_16 & 0x8000) == 0) {
      op1_16--;
      op2_16 <<= 1;
    }
 
    SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
    clear_ZF();
 
    BX_WRITE_16BIT_REG(i->dst(), op1_16);
  }
 
  BX_NEXT_INSTR(i);
}
 
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BT_EwGwM(bxInstruction_c *i)
{
  bx_address op1_addr;
  Bit16u op1_16, op2_16, index;
  Bit32s displacement32;
 
  bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
 
  op2_16 = BX_READ_16BIT_REG(i->src());
  index = op2_16 & 0xf;
  displacement32 = ((Bit16s) (op2_16&0xfff0)) / 16;
  op1_addr = eaddr + 2 * displacement32;
 
  /* pointer, segment address pair */
  op1_16 = read_virtual_word(i->seg(), op1_addr & i->asize_mask());
 
  set_CF((op1_16 >> index) & 0x01);
 
  BX_NEXT_INSTR(i);
}
 
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BT_EwGwR(bxInstruction_c *i)
{
  Bit16u op1_16, op2_16;
 
  op1_16 = BX_READ_16BIT_REG(i->dst());
  op2_16 = BX_READ_16BIT_REG(i->src());
  op2_16 &= 0xf;
  set_CF((op1_16 >> op2_16) & 0x01);
 
  BX_NEXT_INSTR(i);
}
 
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BTS_EwGwM(bxInstruction_c *i)
{
  bx_address op1_addr;
  Bit16u op1_16, op2_16, index;
  Bit32s displacement32;
  bx_bool bit_i;
 
  bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
 
  op2_16 = BX_READ_16BIT_REG(i->src());
  index = op2_16 & 0xf;
  displacement32 = ((Bit16s) (op2_16 & 0xfff0)) / 16;
  op1_addr = eaddr + 2 * displacement32;
 
  /* pointer, segment address pair */
  op1_16 = read_RMW_virtual_word(i->seg(), op1_addr & i->asize_mask());
  bit_i = (op1_16 >> index) & 0x01;
  op1_16 |= (1 << index);
  write_RMW_virtual_word(op1_16);
 
  set_CF(bit_i);
 
  BX_NEXT_INSTR(i);
}
 
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BTS_EwGwR(bxInstruction_c *i)
{
  Bit16u op1_16, op2_16;
 
  op1_16 = BX_READ_16BIT_REG(i->dst());
  op2_16 = BX_READ_16BIT_REG(i->src());
  op2_16 &= 0xf;
  set_CF((op1_16 >> op2_16) & 0x01);
  op1_16 |= (1 << op2_16);
 
  /* now write result back to the destination */
  BX_WRITE_16BIT_REG(i->dst(), op1_16);
 
  BX_NEXT_INSTR(i);
}
 
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BTR_EwGwM(bxInstruction_c *i)
{
  bx_address op1_addr;
  Bit16u op1_16, op2_16, index;
  Bit32s displacement32;
 
  bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
 
  op2_16 = BX_READ_16BIT_REG(i->src());
  index = op2_16 & 0xf;
  displacement32 = ((Bit16s) (op2_16&0xfff0)) / 16;
  op1_addr = eaddr + 2 * displacement32;
 
  /* pointer, segment address pair */
  op1_16 = read_RMW_virtual_word(i->seg(), op1_addr & i->asize_mask());
  bx_bool temp_cf = (op1_16 >> index) & 0x01;
  op1_16 &= ~(1 << index);
 
  /* now write back to destination */
  write_RMW_virtual_word(op1_16);
 
  set_CF(temp_cf);
 
  BX_NEXT_INSTR(i);
}
 
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BTR_EwGwR(bxInstruction_c *i)
{
  Bit16u op1_16, op2_16;
 
  op1_16 = BX_READ_16BIT_REG(i->dst());
  op2_16 = BX_READ_16BIT_REG(i->src());
  op2_16 &= 0xf;
  set_CF((op1_16 >> op2_16) & 0x01);
  op1_16 &= ~(1 << op2_16);
 
  /* now write result back to the destination */
  BX_WRITE_16BIT_REG(i->dst(), op1_16);
 
  BX_NEXT_INSTR(i);
}
 
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BTC_EwGwM(bxInstruction_c *i)
{
  bx_address op1_addr;
  Bit16u op1_16, op2_16, index_16;
  Bit16s displacement16;
 
  bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
 
  op2_16 = BX_READ_16BIT_REG(i->src());
  index_16 = op2_16 & 0xf;
  displacement16 = ((Bit16s) (op2_16 & 0xfff0)) / 16;
  op1_addr = eaddr + 2 * displacement16;
 
  op1_16 = read_RMW_virtual_word(i->seg(), op1_addr & i->asize_mask());
  bx_bool temp_CF = (op1_16 >> index_16) & 0x01;
  op1_16 ^= (1 << index_16);  /* toggle bit */
  write_RMW_virtual_word(op1_16);
 
  set_CF(temp_CF);
 
  BX_NEXT_INSTR(i);
}
 
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BTC_EwGwR(bxInstruction_c *i)
{
  Bit16u op1_16, op2_16;
 
  op1_16 = BX_READ_16BIT_REG(i->dst());
  op2_16 = BX_READ_16BIT_REG(i->src());
  op2_16 &= 0xf;
 
  bx_bool temp_CF = (op1_16 >> op2_16) & 0x01;
  op1_16 ^= (1 << op2_16);  /* toggle bit */
  BX_WRITE_16BIT_REG(i->dst(), op1_16);
 
  set_CF(temp_CF);
 
  BX_NEXT_INSTR(i);
}
 
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BT_EwIbM(bxInstruction_c *i)
{
  bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
 
  Bit16u op1_16 = read_virtual_word(i->seg(), eaddr);
  Bit8u  op2_8  = i->Ib() & 0xf;
 
  set_CF((op1_16 >> op2_8) & 0x01);
 
  BX_NEXT_INSTR(i);
}
 
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BT_EwIbR(bxInstruction_c *i)
{
  Bit16u op1_16 = BX_READ_16BIT_REG(i->dst());
  Bit8u  op2_8  = i->Ib() & 0xf;
 
  set_CF((op1_16 >> op2_8) & 0x01);
 
  BX_NEXT_INSTR(i);
}
 
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BTS_EwIbM(bxInstruction_c *i)
{
  Bit8u op2_8 = i->Ib() & 0xf;
 
  bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
 
  Bit16u op1_16 = read_RMW_virtual_word(i->seg(), eaddr);
  bx_bool temp_CF = (op1_16 >> op2_8) & 0x01;
  op1_16 |= (1 << op2_8);
  write_RMW_virtual_word(op1_16);
 
  set_CF(temp_CF);
 
  BX_NEXT_INSTR(i);
}
 
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BTS_EwIbR(bxInstruction_c *i)
{
  Bit8u op2_8 = i->Ib() & 0xf;
 
  Bit16u op1_16 = BX_READ_16BIT_REG(i->dst());
  bx_bool temp_CF = (op1_16 >> op2_8) & 0x01;
  op1_16 |= (1 << op2_8);
  BX_WRITE_16BIT_REG(i->dst(), op1_16);
 
  set_CF(temp_CF);
 
  BX_NEXT_INSTR(i);
}
 
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BTC_EwIbM(bxInstruction_c *i)
{
  Bit8u op2_8 = i->Ib() & 0xf;
 
  bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
 
  Bit16u op1_16 = read_RMW_virtual_word(i->seg(), eaddr);
  bx_bool temp_CF = (op1_16 >> op2_8) & 0x01;
  op1_16 ^= (1 << op2_8);  /* toggle bit */
  write_RMW_virtual_word(op1_16);
 
  set_CF(temp_CF);
 
  BX_NEXT_INSTR(i);
}
 
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BTC_EwIbR(bxInstruction_c *i)
{
  Bit8u op2_8 = i->Ib() & 0xf;
 
  Bit16u op1_16 = BX_READ_16BIT_REG(i->dst());
  bx_bool temp_CF = (op1_16 >> op2_8) & 0x01;
  op1_16 ^= (1 << op2_8);  /* toggle bit */
  BX_WRITE_16BIT_REG(i->dst(), op1_16);
 
  set_CF(temp_CF);
 
  BX_NEXT_INSTR(i);
}
 
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BTR_EwIbM(bxInstruction_c *i)
{
  Bit8u op2_8 = i->Ib() & 0xf;
 
  bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
 
  Bit16u op1_16 = read_RMW_virtual_word(i->seg(), eaddr);
  bx_bool temp_CF = (op1_16 >> op2_8) & 0x01;
  op1_16 &= ~(1 << op2_8);
  write_RMW_virtual_word(op1_16);
 
  set_CF(temp_CF);
 
  BX_NEXT_INSTR(i);
}
 
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BTR_EwIbR(bxInstruction_c *i)
{
  Bit8u op2_8 = i->Ib() & 0xf;
 
  Bit16u op1_16 = BX_READ_16BIT_REG(i->dst());
  bx_bool temp_CF = (op1_16 >> op2_8) & 0x01;
  op1_16 &= ~(1 << op2_8);
  BX_WRITE_16BIT_REG(i->dst(), op1_16);
 
  set_CF(temp_CF);
 
  BX_NEXT_INSTR(i);
}
 
/* F3 0F B8 */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::POPCNT_GwEwR(bxInstruction_c *i)
{
  Bit16u op2_16 = BX_READ_16BIT_REG(i->src());
 
  Bit16u op1_16 = 0;
  while (op2_16 != 0) {
    op2_16 &= (op2_16-1);
    op1_16++;
  }
 
  Bit32u flags = op1_16 ? 0 : EFlagsZFMask;
  setEFlagsOSZAPC(flags);
 
  BX_WRITE_16BIT_REG(i->dst(), op1_16);
 
  BX_NEXT_INSTR(i);
}
 
/* F3 0F BC */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::TZCNT_GwEwR(bxInstruction_c *i)
{
  Bit16u op1_16 = BX_READ_16BIT_REG(i->src());
  Bit16u mask = 0x1, result_16 = 0;
 
  while ((op1_16 & mask) == 0 && mask) {
    mask <<= 1;
    result_16++;
  }
 
  set_CF(! op1_16);
  set_ZF(! result_16);
 
  BX_WRITE_16BIT_REG(i->dst(), result_16);
 
  BX_NEXT_INSTR(i);
}
 
/* F3 0F BD */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LZCNT_GwEwR(bxInstruction_c *i)
{
  Bit16u op1_16 = BX_READ_16BIT_REG(i->src());
  Bit16u mask = 0x8000, result_16 = 0;
 
  while ((op1_16 & mask) == 0 && mask) {
    mask >>= 1;
    result_16++;
  }
 
  set_CF(! op1_16);
  set_ZF(! result_16);
 
  BX_WRITE_16BIT_REG(i->dst(), result_16);
 
  BX_NEXT_INSTR(i);
}
 
#endif // (BX_CPU_LEVEL >= 3)

Browse

Tools

Subversion Repositories ao486

[/] [ao486/] [trunk/] [bochs486/] [cpu/] [bit16.cc] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	alfik	`/////////////////////////////////////////////////////////////////////////`
2			`// $Id: bit16.cc 11437 2012-09-21 14:56:56Z sshwarts $`
3			`/////////////////////////////////////////////////////////////////////////`
4			`//`
5			`// Copyright (C) 2001-2012 The Bochs Project`
6			`//`
7			`// This library is free software; you can redistribute it and/or`
8			`// modify it under the terms of the GNU Lesser General Public`
9			`// License as published by the Free Software Foundation; either`
10			`// version 2 of the License, or (at your option) any later version.`
11			`//`
12			`// This library is distributed in the hope that it will be useful,`
13			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
14			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU`
15			`// Lesser General Public License for more details.`
16			`//`
17			`// You should have received a copy of the GNU Lesser General Public`
18			`// License along with this library; if not, write to the Free Software`
19			`// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA`
20			`/////////////////////////////////////////////////////////////////////////`
21
22			`#define NEED_CPU_REG_SHORTCUTS 1`
23			`#include "bochs.h"`
24			`#include "cpu.h"`
25			`#define LOG_THIS BX_CPU_THIS_PTR`
26
27			`#if BX_CPU_LEVEL >= 3`
28
29			`BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BSF_GwEwR(bxInstruction_c *i)`
30			`{`
31			`Bit16u op2_16 = BX_READ_16BIT_REG(i->src());`
32
33			`if (op2_16 == 0) {`
34			`assert_ZF(); /* op1_16 undefined */`
35			`}`
36			`else {`
37			`Bit16u op1_16 = 0;`
38			`while ((op2_16 & 0x01) == 0) {`
39			`op1_16++;`
40			`op2_16 >>= 1;`
41			`}`
42
43			`SET_FLAGS_OSZAPC_LOGIC_16(op1_16);`
44			`clear_ZF();`
45
46			`BX_WRITE_16BIT_REG(i->dst(), op1_16);`
47			`}`
48
49			`BX_NEXT_INSTR(i);`
50			`}`
51
52			`BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BSR_GwEwR(bxInstruction_c *i)`
53			`{`
54			`Bit16u op2_16 = BX_READ_16BIT_REG(i->src());`
55
56			`if (op2_16 == 0) {`
57			`assert_ZF(); /* op1_16 undefined */`
58			`}`
59			`else {`
60			`Bit16u op1_16 = 15;`
61			`while ((op2_16 & 0x8000) == 0) {`
62			`op1_16--;`
63			`op2_16 <<= 1;`
64			`}`
65
66			`SET_FLAGS_OSZAPC_LOGIC_16(op1_16);`
67			`clear_ZF();`
68
69			`BX_WRITE_16BIT_REG(i->dst(), op1_16);`
70			`}`
71
72			`BX_NEXT_INSTR(i);`
73			`}`
74
75			`BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BT_EwGwM(bxInstruction_c *i)`
76			`{`
77			`bx_address op1_addr;`
78			`Bit16u op1_16, op2_16, index;`
79			`Bit32s displacement32;`
80
81			`bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));`
82
83			`op2_16 = BX_READ_16BIT_REG(i->src());`
84			`index = op2_16 & 0xf;`
85			`displacement32 = ((Bit16s) (op2_16&0xfff0)) / 16;`
86			`op1_addr = eaddr + 2 * displacement32;`
87
88			`/* pointer, segment address pair */`
89			`op1_16 = read_virtual_word(i->seg(), op1_addr & i->asize_mask());`
90
91			`set_CF((op1_16 >> index) & 0x01);`
92
93			`BX_NEXT_INSTR(i);`
94			`}`
95
96			`BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BT_EwGwR(bxInstruction_c *i)`
97			`{`
98			`Bit16u op1_16, op2_16;`
99
100			`op1_16 = BX_READ_16BIT_REG(i->dst());`
101			`op2_16 = BX_READ_16BIT_REG(i->src());`
102			`op2_16 &= 0xf;`
103			`set_CF((op1_16 >> op2_16) & 0x01);`
104
105			`BX_NEXT_INSTR(i);`
106			`}`
107
108			`BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BTS_EwGwM(bxInstruction_c *i)`
109			`{`
110			`bx_address op1_addr;`
111			`Bit16u op1_16, op2_16, index;`
112			`Bit32s displacement32;`
113			`bx_bool bit_i;`
114
115			`bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));`
116
117			`op2_16 = BX_READ_16BIT_REG(i->src());`
118			`index = op2_16 & 0xf;`
119			`displacement32 = ((Bit16s) (op2_16 & 0xfff0)) / 16;`
120			`op1_addr = eaddr + 2 * displacement32;`
121
122			`/* pointer, segment address pair */`
123			`op1_16 = read_RMW_virtual_word(i->seg(), op1_addr & i->asize_mask());`
124			`bit_i = (op1_16 >> index) & 0x01;`
125			`op1_16 \|= (1 << index);`
126			`write_RMW_virtual_word(op1_16);`
127
128			`set_CF(bit_i);`
129
130			`BX_NEXT_INSTR(i);`
131			`}`
132
133			`BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BTS_EwGwR(bxInstruction_c *i)`
134			`{`
135			`Bit16u op1_16, op2_16;`
136
137			`op1_16 = BX_READ_16BIT_REG(i->dst());`
138			`op2_16 = BX_READ_16BIT_REG(i->src());`
139			`op2_16 &= 0xf;`
140			`set_CF((op1_16 >> op2_16) & 0x01);`
141			`op1_16 \|= (1 << op2_16);`
142
143			`/* now write result back to the destination */`
144			`BX_WRITE_16BIT_REG(i->dst(), op1_16);`
145
146			`BX_NEXT_INSTR(i);`
147			`}`
148
149			`BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BTR_EwGwM(bxInstruction_c *i)`
150			`{`
151			`bx_address op1_addr;`
152			`Bit16u op1_16, op2_16, index;`
153			`Bit32s displacement32;`
154
155			`bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));`
156
157			`op2_16 = BX_READ_16BIT_REG(i->src());`
158			`index = op2_16 & 0xf;`
159			`displacement32 = ((Bit16s) (op2_16&0xfff0)) / 16;`
160			`op1_addr = eaddr + 2 * displacement32;`
161
162			`/* pointer, segment address pair */`
163			`op1_16 = read_RMW_virtual_word(i->seg(), op1_addr & i->asize_mask());`
164			`bx_bool temp_cf = (op1_16 >> index) & 0x01;`
165			`op1_16 &= ~(1 << index);`
166
167			`/* now write back to destination */`
168			`write_RMW_virtual_word(op1_16);`
169
170			`set_CF(temp_cf);`
171
172			`BX_NEXT_INSTR(i);`
173			`}`
174
175			`BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BTR_EwGwR(bxInstruction_c *i)`
176			`{`
177			`Bit16u op1_16, op2_16;`
178
179			`op1_16 = BX_READ_16BIT_REG(i->dst());`
180			`op2_16 = BX_READ_16BIT_REG(i->src());`
181			`op2_16 &= 0xf;`
182			`set_CF((op1_16 >> op2_16) & 0x01);`
183			`op1_16 &= ~(1 << op2_16);`
184
185			`/* now write result back to the destination */`
186			`BX_WRITE_16BIT_REG(i->dst(), op1_16);`
187
188			`BX_NEXT_INSTR(i);`
189			`}`
190
191			`BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BTC_EwGwM(bxInstruction_c *i)`
192			`{`
193			`bx_address op1_addr;`
194			`Bit16u op1_16, op2_16, index_16;`
195			`Bit16s displacement16;`
196
197			`bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));`
198
199			`op2_16 = BX_READ_16BIT_REG(i->src());`
200			`index_16 = op2_16 & 0xf;`
201			`displacement16 = ((Bit16s) (op2_16 & 0xfff0)) / 16;`
202			`op1_addr = eaddr + 2 * displacement16;`
203
204			`op1_16 = read_RMW_virtual_word(i->seg(), op1_addr & i->asize_mask());`
205			`bx_bool temp_CF = (op1_16 >> index_16) & 0x01;`
206			`op1_16 ^= (1 << index_16); /* toggle bit */`
207			`write_RMW_virtual_word(op1_16);`
208
209			`set_CF(temp_CF);`
210
211			`BX_NEXT_INSTR(i);`
212			`}`
213
214			`BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BTC_EwGwR(bxInstruction_c *i)`
215			`{`
216			`Bit16u op1_16, op2_16;`
217
218			`op1_16 = BX_READ_16BIT_REG(i->dst());`
219			`op2_16 = BX_READ_16BIT_REG(i->src());`
220			`op2_16 &= 0xf;`
221
222			`bx_bool temp_CF = (op1_16 >> op2_16) & 0x01;`
223			`op1_16 ^= (1 << op2_16); /* toggle bit */`
224			`BX_WRITE_16BIT_REG(i->dst(), op1_16);`
225
226			`set_CF(temp_CF);`
227
228			`BX_NEXT_INSTR(i);`
229			`}`
230
231			`BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BT_EwIbM(bxInstruction_c *i)`
232			`{`
233			`bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));`
234
235			`Bit16u op1_16 = read_virtual_word(i->seg(), eaddr);`
236			`Bit8u op2_8 = i->Ib() & 0xf;`
237
238			`set_CF((op1_16 >> op2_8) & 0x01);`
239
240			`BX_NEXT_INSTR(i);`
241			`}`
242
243			`BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BT_EwIbR(bxInstruction_c *i)`
244			`{`
245			`Bit16u op1_16 = BX_READ_16BIT_REG(i->dst());`
246			`Bit8u op2_8 = i->Ib() & 0xf;`
247
248			`set_CF((op1_16 >> op2_8) & 0x01);`
249
250			`BX_NEXT_INSTR(i);`
251			`}`
252
253			`BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BTS_EwIbM(bxInstruction_c *i)`
254			`{`
255			`Bit8u op2_8 = i->Ib() & 0xf;`
256
257			`bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));`
258
259			`Bit16u op1_16 = read_RMW_virtual_word(i->seg(), eaddr);`
260			`bx_bool temp_CF = (op1_16 >> op2_8) & 0x01;`
261			`op1_16 \|= (1 << op2_8);`
262			`write_RMW_virtual_word(op1_16);`
263
264			`set_CF(temp_CF);`
265
266			`BX_NEXT_INSTR(i);`
267			`}`
268
269			`BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BTS_EwIbR(bxInstruction_c *i)`
270			`{`
271			`Bit8u op2_8 = i->Ib() & 0xf;`
272
273			`Bit16u op1_16 = BX_READ_16BIT_REG(i->dst());`
274			`bx_bool temp_CF = (op1_16 >> op2_8) & 0x01;`
275			`op1_16 \|= (1 << op2_8);`
276			`BX_WRITE_16BIT_REG(i->dst(), op1_16);`
277
278			`set_CF(temp_CF);`
279
280			`BX_NEXT_INSTR(i);`
281			`}`
282
283			`BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BTC_EwIbM(bxInstruction_c *i)`
284			`{`
285			`Bit8u op2_8 = i->Ib() & 0xf;`
286
287			`bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));`
288
289			`Bit16u op1_16 = read_RMW_virtual_word(i->seg(), eaddr);`
290			`bx_bool temp_CF = (op1_16 >> op2_8) & 0x01;`
291			`op1_16 ^= (1 << op2_8); /* toggle bit */`
292			`write_RMW_virtual_word(op1_16);`
293
294			`set_CF(temp_CF);`
295
296			`BX_NEXT_INSTR(i);`
297			`}`
298
299			`BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BTC_EwIbR(bxInstruction_c *i)`
300			`{`
301			`Bit8u op2_8 = i->Ib() & 0xf;`
302
303			`Bit16u op1_16 = BX_READ_16BIT_REG(i->dst());`
304			`bx_bool temp_CF = (op1_16 >> op2_8) & 0x01;`
305			`op1_16 ^= (1 << op2_8); /* toggle bit */`
306			`BX_WRITE_16BIT_REG(i->dst(), op1_16);`
307
308			`set_CF(temp_CF);`
309
310			`BX_NEXT_INSTR(i);`
311			`}`
312
313			`BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BTR_EwIbM(bxInstruction_c *i)`
314			`{`
315			`Bit8u op2_8 = i->Ib() & 0xf;`
316
317			`bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));`
318
319			`Bit16u op1_16 = read_RMW_virtual_word(i->seg(), eaddr);`
320			`bx_bool temp_CF = (op1_16 >> op2_8) & 0x01;`
321			`op1_16 &= ~(1 << op2_8);`
322			`write_RMW_virtual_word(op1_16);`
323
324			`set_CF(temp_CF);`
325
326			`BX_NEXT_INSTR(i);`
327			`}`
328
329			`BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::BTR_EwIbR(bxInstruction_c *i)`
330			`{`
331			`Bit8u op2_8 = i->Ib() & 0xf;`
332
333			`Bit16u op1_16 = BX_READ_16BIT_REG(i->dst());`
334			`bx_bool temp_CF = (op1_16 >> op2_8) & 0x01;`
335			`op1_16 &= ~(1 << op2_8);`
336			`BX_WRITE_16BIT_REG(i->dst(), op1_16);`
337
338			`set_CF(temp_CF);`
339
340			`BX_NEXT_INSTR(i);`
341			`}`
342
343			`/* F3 0F B8 */`
344			`BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::POPCNT_GwEwR(bxInstruction_c *i)`
345			`{`
346			`Bit16u op2_16 = BX_READ_16BIT_REG(i->src());`
347
348			`Bit16u op1_16 = 0;`
349			`while (op2_16 != 0) {`
350			`op2_16 &= (op2_16-1);`
351			`op1_16++;`
352			`}`
353
354			`Bit32u flags = op1_16 ? 0 : EFlagsZFMask;`
355			`setEFlagsOSZAPC(flags);`
356
357			`BX_WRITE_16BIT_REG(i->dst(), op1_16);`
358
359			`BX_NEXT_INSTR(i);`
360			`}`
361
362			`/* F3 0F BC */`
363			`BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::TZCNT_GwEwR(bxInstruction_c *i)`
364			`{`
365			`Bit16u op1_16 = BX_READ_16BIT_REG(i->src());`
366			`Bit16u mask = 0x1, result_16 = 0;`
367
368			`while ((op1_16 & mask) == 0 && mask) {`
369			`mask <<= 1;`
370			`result_16++;`
371			`}`
372
373			`set_CF(! op1_16);`
374			`set_ZF(! result_16);`
375
376			`BX_WRITE_16BIT_REG(i->dst(), result_16);`
377
378			`BX_NEXT_INSTR(i);`
379			`}`
380
381			`/* F3 0F BD */`
382			`BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LZCNT_GwEwR(bxInstruction_c *i)`
383			`{`
384			`Bit16u op1_16 = BX_READ_16BIT_REG(i->src());`
385			`Bit16u mask = 0x8000, result_16 = 0;`
386
387			`while ((op1_16 & mask) == 0 && mask) {`
388			`mask >>= 1;`
389			`result_16++;`
390			`}`
391
392			`set_CF(! op1_16);`
393			`set_ZF(! result_16);`
394
395			`BX_WRITE_16BIT_REG(i->dst(), result_16);`
396
397			`BX_NEXT_INSTR(i);`
398			`}`
399
400			`#endif // (BX_CPU_LEVEL >= 3)`