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/////////////////////////////////////////////////////////////////////////

// $Id: cpu.h 11680 2013-04-17 19:59:56Z sshwarts $

/////////////////////////////////////////////////////////////////////////

//

//  Copyright (C) 2001-2013  The Bochs Project

//

//  This library is free software; you can redistribute it and/or

//  modify it under the terms of the GNU Lesser General Public

//  License as published by the Free Software Foundation; either

//  version 2 of the License, or (at your option) any later version.

//

//  This library is distributed in the hope that it will be useful,

//  but WITHOUT ANY WARRANTY; without even the implied warranty of

//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

//  Lesser General Public License for more details.

//

//  You should have received a copy of the GNU Lesser General Public

//  License along with this library; if not, write to the Free Software

//  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA

/////////////////////////////////////////////////////////////////////////

#ifndef BX_CPU_H

#  define BX_CPU_H 1

#include <setjmp.h>

// <TAG-DEFINES-DECODE-START>

// segment register encoding

#define BX_SEG_REG_ES    0

#define BX_SEG_REG_CS    1

#define BX_SEG_REG_SS    2

#define BX_SEG_REG_DS    3

#define BX_SEG_REG_FS    4

#define BX_SEG_REG_GS    5

// NULL now has to fit in 3 bits.

#define BX_SEG_REG_NULL  7

#define BX_NULL_SEG_REG(seg) ((seg) == BX_SEG_REG_NULL)

// <TAG-DEFINES-DECODE-END>

#define BX_16BIT_REG_AX 0

#define BX_16BIT_REG_CX 1

#define BX_16BIT_REG_DX 2

#define BX_16BIT_REG_BX 3

#define BX_16BIT_REG_SP 4

#define BX_16BIT_REG_BP 5

#define BX_16BIT_REG_SI 6

#define BX_16BIT_REG_DI 7

#define BX_32BIT_REG_EAX 0

#define BX_32BIT_REG_ECX 1

#define BX_32BIT_REG_EDX 2

#define BX_32BIT_REG_EBX 3

#define BX_32BIT_REG_ESP 4

#define BX_32BIT_REG_EBP 5

#define BX_32BIT_REG_ESI 6

#define BX_32BIT_REG_EDI 7

#define BX_64BIT_REG_RAX 0

#define BX_64BIT_REG_RCX 1

#define BX_64BIT_REG_RDX 2

#define BX_64BIT_REG_RBX 3

#define BX_64BIT_REG_RSP 4

#define BX_64BIT_REG_RBP 5

#define BX_64BIT_REG_RSI 6

#define BX_64BIT_REG_RDI 7

#define BX_64BIT_REG_R8  8

#define BX_64BIT_REG_R9  9

#define BX_64BIT_REG_R10 10

#define BX_64BIT_REG_R11 11

#define BX_64BIT_REG_R12 12

#define BX_64BIT_REG_R13 13

#define BX_64BIT_REG_R14 14

#define BX_64BIT_REG_R15 15

#if BX_SUPPORT_X86_64

# define BX_GENERAL_REGISTERS 16

#else

# define BX_GENERAL_REGISTERS 8

#endif

#define BX_TMP_REGISTER (BX_GENERAL_REGISTERS)

#define BX_16BIT_REG_IP  (BX_GENERAL_REGISTERS+1)

#define BX_32BIT_REG_EIP (BX_GENERAL_REGISTERS+1)

#define BX_64BIT_REG_RIP (BX_GENERAL_REGISTERS+1)

#define BX_NIL_REGISTER  (BX_GENERAL_REGISTERS+2)

#if defined(NEED_CPU_REG_SHORTCUTS)

/* WARNING:

   Only BX_CPU_C member functions can use these shortcuts safely!

   Functions that use the shortcuts outside of BX_CPU_C might work

   when BX_USE_CPU_SMF=1 but will fail when BX_USE_CPU_SMF=0

   (for example in SMP mode).

*/

// access to 8 bit general registers

#define AL (BX_CPU_THIS_PTR gen_reg[0].word.byte.rl)

#define CL (BX_CPU_THIS_PTR gen_reg[1].word.byte.rl)

#define DL (BX_CPU_THIS_PTR gen_reg[2].word.byte.rl)

#define BL (BX_CPU_THIS_PTR gen_reg[3].word.byte.rl)

#define AH (BX_CPU_THIS_PTR gen_reg[0].word.byte.rh)

#define CH (BX_CPU_THIS_PTR gen_reg[1].word.byte.rh)

#define DH (BX_CPU_THIS_PTR gen_reg[2].word.byte.rh)

#define BH (BX_CPU_THIS_PTR gen_reg[3].word.byte.rh)

#define TMP8L (BX_CPU_THIS_PTR gen_reg[BX_TMP_REGISTER].word.byte.rl)

// access to 16 bit general registers

#define AX (BX_CPU_THIS_PTR gen_reg[0].word.rx)

#define CX (BX_CPU_THIS_PTR gen_reg[1].word.rx)

#define DX (BX_CPU_THIS_PTR gen_reg[2].word.rx)

#define BX (BX_CPU_THIS_PTR gen_reg[3].word.rx)

#define SP (BX_CPU_THIS_PTR gen_reg[4].word.rx)

#define BP (BX_CPU_THIS_PTR gen_reg[5].word.rx)

#define SI (BX_CPU_THIS_PTR gen_reg[6].word.rx)

#define DI (BX_CPU_THIS_PTR gen_reg[7].word.rx)

// access to 16 bit instruction pointer

#define IP (BX_CPU_THIS_PTR gen_reg[BX_16BIT_REG_IP].word.rx)

#define TMP16 (BX_CPU_THIS_PTR gen_reg[BX_TMP_REGISTER].word.rx)

// accesss to 32 bit general registers

#define EAX (BX_CPU_THIS_PTR gen_reg[0].dword.erx)

#define ECX (BX_CPU_THIS_PTR gen_reg[1].dword.erx)

#define EDX (BX_CPU_THIS_PTR gen_reg[2].dword.erx)

#define EBX (BX_CPU_THIS_PTR gen_reg[3].dword.erx)

#define ESP (BX_CPU_THIS_PTR gen_reg[4].dword.erx)

#define EBP (BX_CPU_THIS_PTR gen_reg[5].dword.erx)

#define ESI (BX_CPU_THIS_PTR gen_reg[6].dword.erx)

#define EDI (BX_CPU_THIS_PTR gen_reg[7].dword.erx)

// access to 32 bit instruction pointer

#define EIP (BX_CPU_THIS_PTR gen_reg[BX_32BIT_REG_EIP].dword.erx)

#define TMP32 (BX_CPU_THIS_PTR gen_reg[BX_TMP_REGISTER].dword.erx)

#if BX_SUPPORT_X86_64

// accesss to 64 bit general registers

#define RAX (BX_CPU_THIS_PTR gen_reg[0].rrx)

#define RCX (BX_CPU_THIS_PTR gen_reg[1].rrx)

#define RDX (BX_CPU_THIS_PTR gen_reg[2].rrx)

#define RBX (BX_CPU_THIS_PTR gen_reg[3].rrx)

#define RSP (BX_CPU_THIS_PTR gen_reg[4].rrx)

#define RBP (BX_CPU_THIS_PTR gen_reg[5].rrx)

#define RSI (BX_CPU_THIS_PTR gen_reg[6].rrx)

#define RDI (BX_CPU_THIS_PTR gen_reg[7].rrx)

#define R8  (BX_CPU_THIS_PTR gen_reg[8].rrx)

#define R9  (BX_CPU_THIS_PTR gen_reg[9].rrx)

#define R10 (BX_CPU_THIS_PTR gen_reg[10].rrx)

#define R11 (BX_CPU_THIS_PTR gen_reg[11].rrx)

#define R12 (BX_CPU_THIS_PTR gen_reg[12].rrx)

#define R13 (BX_CPU_THIS_PTR gen_reg[13].rrx)

#define R14 (BX_CPU_THIS_PTR gen_reg[14].rrx)

#define R15 (BX_CPU_THIS_PTR gen_reg[15].rrx)

// access to 64 bit instruction pointer

#define RIP (BX_CPU_THIS_PTR gen_reg[BX_64BIT_REG_RIP].rrx)

#define TMP64 (BX_CPU_THIS_PTR gen_reg[BX_TMP_REGISTER].rrx)

// access to 64 bit MSR registers

#define MSR_FSBASE  (BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS].cache.u.segment.base)

#define MSR_GSBASE  (BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.u.segment.base)

#define MSR_LSTAR   (BX_CPU_THIS_PTR msr.lstar)

#define MSR_CSTAR   (BX_CPU_THIS_PTR msr.cstar)

#define MSR_FMASK   (BX_CPU_THIS_PTR msr.fmask)

#define MSR_KERNELGSBASE   (BX_CPU_THIS_PTR msr.kernelgsbase)

#define MSR_TSC_AUX (BX_CPU_THIS_PTR msr.tsc_aux)

#else // simplify merge between 32-bit and 64-bit mode

#define RAX EAX

#define RCX ECX

#define RDX EDX

#define RBX EBX

#define RSP ESP

#define RBP EBP

#define RSI ESI

#define RDI EDI

#define RIP EIP

#endif // BX_SUPPORT_X86_64 == 0

#define PREV_RIP (BX_CPU_THIS_PTR prev_rip)

#if BX_SUPPORT_X86_64

#define BX_READ_8BIT_REGx(index,extended)  ((((index) & 4) == 0 || (extended)) ? \

  (BX_CPU_THIS_PTR gen_reg[index].word.byte.rl) : \

  (BX_CPU_THIS_PTR gen_reg[(index)-4].word.byte.rh))

#define BX_READ_64BIT_REG(index) (BX_CPU_THIS_PTR gen_reg[index].rrx)

#define BX_READ_64BIT_REG_HIGH(index) (BX_CPU_THIS_PTR gen_reg[index].dword.hrx)

#else

#define BX_READ_8BIT_REG(index)  (((index) & 4) ? \

  (BX_CPU_THIS_PTR gen_reg[(index)-4].word.byte.rh) : \

  (BX_CPU_THIS_PTR gen_reg[index].word.byte.rl))

#define BX_READ_8BIT_REGx(index,ext) BX_READ_8BIT_REG(index)

#endif

#define BX_READ_8BIT_REGH(index) (BX_CPU_THIS_PTR gen_reg[index].word.byte.rh)

#define BX_READ_16BIT_REG(index) (BX_CPU_THIS_PTR gen_reg[index].word.rx)

#define BX_READ_32BIT_REG(index) (BX_CPU_THIS_PTR gen_reg[index].dword.erx)

#define BX_WRITE_8BIT_REGH(index, val) {\

  BX_CPU_THIS_PTR gen_reg[index].word.byte.rh = val; \

}

#define BX_WRITE_16BIT_REG(index, val) {\

  BX_CPU_THIS_PTR gen_reg[index].word.rx = val; \

}

/*

#define BX_WRITE_32BIT_REG(index, val) {\

  BX_CPU_THIS_PTR gen_reg[index].dword.erx = val; \

}

*/

#if BX_SUPPORT_X86_64

#define BX_WRITE_8BIT_REGx(index, extended, val) {\

  if (((index) & 4) == 0 || (extended)) \

    BX_CPU_THIS_PTR gen_reg[index].word.byte.rl = val; \

  else \

    BX_CPU_THIS_PTR gen_reg[(index)-4].word.byte.rh = val; \

}

#define BX_WRITE_32BIT_REGZ(index, val) {\

  BX_CPU_THIS_PTR gen_reg[index].rrx = (Bit32u) val; \

}

#define BX_WRITE_64BIT_REG(index, val) {\

  BX_CPU_THIS_PTR gen_reg[index].rrx = val; \

}

#define BX_CLEAR_64BIT_HIGH(index) {\

  BX_CPU_THIS_PTR gen_reg[index].dword.hrx = 0; \

}

#else

#define BX_WRITE_8BIT_REG(index, val) {\

  if ((index) & 4) \

    BX_CPU_THIS_PTR gen_reg[(index)-4].word.byte.rh = val; \

  else \

    BX_CPU_THIS_PTR gen_reg[index].word.byte.rl = val; \

}

#define BX_WRITE_8BIT_REGx(index, ext, val) BX_WRITE_8BIT_REG(index, val)

// For x86-32, I just pretend this one is like the macro above,

// so common code can be used.

#define BX_WRITE_32BIT_REGZ(index, val) {\

  BX_CPU_THIS_PTR gen_reg[index].dword.erx = (Bit32u) val; \

}

#define BX_CLEAR_64BIT_HIGH(index)

#endif

#define CPL       (BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.rpl)

#define USER_PL   (BX_CPU_THIS_PTR user_pl) /* CPL == 3 */

#if BX_SUPPORT_SMP

#define BX_CPU_ID (BX_CPU_THIS_PTR bx_cpuid)

#else

#define BX_CPU_ID (0)

#endif

#endif  // defined(NEED_CPU_REG_SHORTCUTS)

// <TAG-INSTRUMENTATION_COMMON-BEGIN>

// possible types passed to BX_INSTR_TLB_CNTRL()

#define BX_INSTR_MOV_CR0        10

#define BX_INSTR_MOV_CR3        11

#define BX_INSTR_MOV_CR4        12

#define BX_INSTR_TASK_SWITCH    13

#define BX_INSTR_CONTEXT_SWITCH 14

#define BX_INSTR_INVLPG         15

#define BX_INSTR_INVEPT         16

#define BX_INSTR_INVVPID        17

#define BX_INSTR_INVPCID        18

// possible types passed to BX_INSTR_CACHE_CNTRL()

#define BX_INSTR_INVD           10

#define BX_INSTR_WBINVD         11

// possible types passed to BX_INSTR_FAR_BRANCH() and BX_INSTR_UCNEAR_BRANCH()

#define BX_INSTR_IS_JMP            10

#define BX_INSTR_IS_JMP_INDIRECT   11

#define BX_INSTR_IS_CALL           12

#define BX_INSTR_IS_CALL_INDIRECT  13

#define BX_INSTR_IS_RET            14

#define BX_INSTR_IS_IRET           15

#define BX_INSTR_IS_INT            16

#define BX_INSTR_IS_SYSCALL        17

#define BX_INSTR_IS_SYSRET         18

#define BX_INSTR_IS_SYSENTER       19

#define BX_INSTR_IS_SYSEXIT        20

// possible types passed to BX_INSTR_PREFETCH_HINT()

#define BX_INSTR_PREFETCH_NTA   0

#define BX_INSTR_PREFETCH_T0    1

#define BX_INSTR_PREFETCH_T1    2

#define BX_INSTR_PREFETCH_T2    3

// <TAG-INSTRUMENTATION_COMMON-END>

// passed to internal debugger together with BX_READ/BX_WRITE/BX_EXECUTE/BX_RW

enum {

  BX_PDPTR0_ACCESS = 1,

  BX_PDPTR1_ACCESS,

  BX_PDPTR2_ACCESS,

  BX_PDPTR3_ACCESS,

  BX_PTE_ACCESS,

  BX_PDE_ACCESS,

  BX_PDTE_ACCESS,

  BX_PML4E_ACCESS,

  BX_EPT_PTE_ACCESS,

  BX_EPT_PDE_ACCESS,

  BX_EPT_PDTE_ACCESS,

  BX_EPT_PML4E_ACCESS,

  BX_VMCS_ACCESS,

  BX_SHADOW_VMCS_ACCESS,

  BX_MSR_BITMAP_ACCESS,

  BX_IO_BITMAP_ACCESS,

  BX_VMREAD_BITMAP_ACCESS,

  BX_VMWRITE_BITMAP_ACCESS,

  BX_VMX_LOAD_MSR_ACCESS,

  BX_VMX_STORE_MSR_ACCESS,

  BX_VMX_VAPIC_ACCESS,

  BX_SMRAM_ACCESS

};

struct BxExceptionInfo {

  unsigned exception_type;

  unsigned exception_class;

  bx_bool push_error;

};

#define BX_DE_EXCEPTION   0 // Divide Error (fault)

#define BX_DB_EXCEPTION   1 // Debug (fault/trap)

#define BX_BP_EXCEPTION   3 // Breakpoint (trap)

#define BX_OF_EXCEPTION   4 // Overflow (trap)

#define BX_BR_EXCEPTION   5 // BOUND (fault)

#define BX_UD_EXCEPTION   6

#define BX_NM_EXCEPTION   7

#define BX_DF_EXCEPTION   8

#define BX_TS_EXCEPTION  10

#define BX_NP_EXCEPTION  11

#define BX_SS_EXCEPTION  12

#define BX_GP_EXCEPTION  13

#define BX_PF_EXCEPTION  14

#define BX_MF_EXCEPTION  16

#define BX_AC_EXCEPTION  17

#define BX_MC_EXCEPTION  18

#define BX_XM_EXCEPTION  19

#define BX_VE_EXCEPTION  20

#define BX_CPU_HANDLED_EXCEPTIONS  32

/* MSR registers */

#define BX_MSR_TSC                 0x010

#define BX_MSR_APICBASE            0x01b

#if BX_CPU_LEVEL >= 6

  #define BX_MSR_SYSENTER_CS       0x174

  #define BX_MSR_SYSENTER_ESP      0x175

  #define BX_MSR_SYSENTER_EIP      0x176

#endif

#define BX_MSR_DEBUGCTLMSR         0x1d9

#define BX_MSR_LASTBRANCHFROMIP    0x1db

#define BX_MSR_LASTBRANCHTOIP      0x1dc

#define BX_MSR_LASTINTOIP          0x1dd

#if BX_CPU_LEVEL >= 6

  #define BX_MSR_MTRRCAP           0x0fe

  #define BX_MSR_MTRRPHYSBASE0     0x200

  #define BX_MSR_MTRRPHYSMASK0     0x201

  #define BX_MSR_MTRRPHYSBASE1     0x202

  #define BX_MSR_MTRRPHYSMASK1     0x203

  #define BX_MSR_MTRRPHYSBASE2     0x204

  #define BX_MSR_MTRRPHYSMASK2     0x205

  #define BX_MSR_MTRRPHYSBASE3     0x206

  #define BX_MSR_MTRRPHYSMASK3     0x207

  #define BX_MSR_MTRRPHYSBASE4     0x208

  #define BX_MSR_MTRRPHYSMASK4     0x209

  #define BX_MSR_MTRRPHYSBASE5     0x20a

  #define BX_MSR_MTRRPHYSMASK5     0x20b

  #define BX_MSR_MTRRPHYSBASE6     0x20c

  #define BX_MSR_MTRRPHYSMASK6     0x20d

  #define BX_MSR_MTRRPHYSBASE7     0x20e

  #define BX_MSR_MTRRPHYSMASK7     0x20f

  #define BX_MSR_MTRRFIX64K_00000  0x250

  #define BX_MSR_MTRRFIX16K_80000  0x258

  #define BX_MSR_MTRRFIX16K_A0000  0x259

  #define BX_MSR_MTRRFIX4K_C0000   0x268

  #define BX_MSR_MTRRFIX4K_C8000   0x269

  #define BX_MSR_MTRRFIX4K_D0000   0x26a

  #define BX_MSR_MTRRFIX4K_D8000   0x26b

  #define BX_MSR_MTRRFIX4K_E0000   0x26c

  #define BX_MSR_MTRRFIX4K_E8000   0x26d

  #define BX_MSR_MTRRFIX4K_F0000   0x26e

  #define BX_MSR_MTRRFIX4K_F8000   0x26f

  #define BX_MSR_PAT               0x277

  #define BX_MSR_MTRR_DEFTYPE      0x2ff

#endif

#define BX_MSR_TSC_DEADLINE        0x6E0

#define BX_MSR_MAX_INDEX          0x1000

enum {

  BX_MEMTYPE_UC = 0,

  BX_MEMTYPE_WC,

  BX_MEMTYPE_RESERVED2,

  BX_MEMTYPE_RESERVED3,

  BX_MEMTYPE_WT,

  BX_MEMTYPE_WP,

  BX_MEMTYPE_WB

};

#if BX_SUPPORT_VMX

  #define BX_MSR_VMX_BASIC                0x480

  #define BX_MSR_VMX_PINBASED_CTRLS       0x481

  #define BX_MSR_VMX_PROCBASED_CTRLS      0x482

  #define BX_MSR_VMX_VMEXIT_CTRLS         0x483

  #define BX_MSR_VMX_VMENTRY_CTRLS        0x484

  #define BX_MSR_VMX_MISC                 0x485

  #define BX_MSR_VMX_CR0_FIXED0           0x486

  #define BX_MSR_VMX_CR0_FIXED1           0x487

  #define BX_MSR_VMX_CR4_FIXED0           0x488

  #define BX_MSR_VMX_CR4_FIXED1           0x489

  #define BX_MSR_VMX_VMCS_ENUM            0x48a

  #define BX_MSR_VMX_PROCBASED_CTRLS2     0x48b

  #define BX_MSR_VMX_EPT_VPID_CAP         0x48c

  #define BX_MSR_VMX_TRUE_PINBASED_CTRLS  0x48d

  #define BX_MSR_VMX_TRUE_PROCBASED_CTRLS 0x48e

  #define BX_MSR_VMX_TRUE_VMEXIT_CTRLS    0x48f

  #define BX_MSR_VMX_TRUE_VMENTRY_CTRLS   0x490

  #define BX_MSR_VMX_VMFUNC               0x491

  #define BX_MSR_IA32_FEATURE_CONTROL     0x03A

  #define BX_MSR_IA32_SMM_MONITOR_CTL     0x09B

#endif

#define BX_MSR_EFER             0xc0000080

#define BX_MSR_STAR             0xc0000081

#define BX_MSR_LSTAR            0xc0000082

#define BX_MSR_CSTAR            0xc0000083

#define BX_MSR_FMASK            0xc0000084

#define BX_MSR_FSBASE           0xc0000100

#define BX_MSR_GSBASE           0xc0000101

#define BX_MSR_KERNELGSBASE     0xc0000102

#define BX_MSR_TSC_AUX          0xc0000103

#define BX_SVM_VM_CR_MSR        0xc0010114

#define BX_SVM_IGNNE_MSR        0xc0010115

#define BX_SVM_SMM_CTL_MSR      0xc0010116

#define BX_SVM_HSAVE_PA_MSR     0xc0010117

#define BX_MODE_IA32_REAL       0x0   // CR0.PE=0                |

#define BX_MODE_IA32_V8086      0x1   // CR0.PE=1, EFLAGS.VM=1   | EFER.LMA=0

#define BX_MODE_IA32_PROTECTED  0x2   // CR0.PE=1, EFLAGS.VM=0   |

#define BX_MODE_LONG_COMPAT     0x3   // EFER.LMA = 1, CR0.PE=1, CS.L=0

#define BX_MODE_LONG_64         0x4   // EFER.LMA = 1, CR0.PE=1, CS.L=1

extern const char* cpu_mode_string(unsigned cpu_mode);

#if BX_SUPPORT_X86_64

#define IsCanonical(offset) ((Bit64u)((((Bit64s)(offset)) >> (BX_LIN_ADDRESS_WIDTH-1)) + 1) < 2)

#endif

#define IsValidPhyAddr(addr) (((addr) & BX_PHY_ADDRESS_RESERVED_BITS) == 0)

#define IsValidPageAlignedPhyAddr(addr) (((addr) & (BX_PHY_ADDRESS_RESERVED_BITS | 0xfff)) == 0)

#define CACHE_LINE_SIZE 64

class BX_CPU_C;

class BX_MEM_C;

#if BX_USE_CPU_SMF == 0

// normal member functions.  This can ONLY be used within BX_CPU_C classes.

// Anyone on the outside should use the BX_CPU macro (defined in bochs.h)

// instead.

#  define BX_CPU_THIS_PTR  this->

#  define BX_CPU_THIS      this

#  define BX_SMF

// with normal member functions, calling a member fn pointer looks like

// object->*(fnptr)(arg, ...);

// Since this is different from when SMF=1, encapsulate it in a macro.

#  define BX_CPU_CALL_METHOD(func, args) \

            (this->*((BxExecutePtr_tR) (func))) args

#  define BX_CPU_CALL_METHODR(func, args) \

            (this->*((BxResolvePtr_tR) (func))) args

#  define BX_CPU_CALL_REP_ITERATION(func, args) \

            (this->*((BxRepIterationPtr_tR) (func))) args

#else

// static member functions.  With SMF, there is only one CPU by definition.

#  define BX_CPU_THIS_PTR  BX_CPU(0)->

#  define BX_CPU_THIS      BX_CPU(0)

#  define BX_SMF           static

#  define BX_CPU_CALL_METHOD(func, args) \

            ((BxExecutePtr_tR) (func)) args

#  define BX_CPU_CALL_METHODR(func, args) \

            ((BxResolvePtr_tR) (func)) args

#  define BX_CPU_CALL_REP_ITERATION(func, args) \

            ((BxRepIterationPtr_tR) (func)) args

#endif

#if BX_SUPPORT_SMP

// multiprocessor simulation, we need an array of cpus and memories

BOCHSAPI extern BX_CPU_C **bx_cpu_array;

#else

// single processor simulation, so there's one of everything

BOCHSAPI extern BX_CPU_C   bx_cpu;

#endif

// notify internal debugger/instrumentation about memory access

#define BX_NOTIFY_LIN_MEMORY_ACCESS(laddr, paddr, size, pl, rw, dataptr) {              \

  BX_INSTR_LIN_ACCESS(BX_CPU_ID, (laddr), (paddr), (size), (rw));                       \

  BX_DBG_LIN_MEMORY_ACCESS(BX_CPU_ID, (laddr), (paddr), (size), (pl), (rw), (dataptr)); \

}

#define BX_NOTIFY_PHY_MEMORY_ACCESS(paddr, size, rw, why, dataptr) {            \

  BX_INSTR_PHY_ACCESS(BX_CPU_ID, (paddr), (size), (rw));                        \

  BX_DBG_PHY_MEMORY_ACCESS(BX_CPU_ID, (paddr), (size), (rw), (why), (dataptr)); \

}

// accessors for all eflags in bx_flags_reg_t

// The macro is used once for each flag bit

// Do not use for arithmetic flags !

#define DECLARE_EFLAG_ACCESSOR(name,bitnum)                     \

  BX_SMF BX_CPP_INLINE Bit32u  get_##name ();                   \

  BX_SMF BX_CPP_INLINE bx_bool getB_##name ();                  \

  BX_SMF BX_CPP_INLINE void assert_##name ();                   \

  BX_SMF BX_CPP_INLINE void clear_##name ();                    \

  BX_SMF BX_CPP_INLINE void set_##name (bx_bool val);

#define IMPLEMENT_EFLAG_ACCESSOR(name,bitnum)                   \

  BX_CPP_INLINE bx_bool BX_CPU_C::getB_##name () {              \

    return 1 & (BX_CPU_THIS_PTR eflags >> bitnum);              \

  }                                                             \

  BX_CPP_INLINE Bit32u  BX_CPU_C::get_##name () {               \

    return BX_CPU_THIS_PTR eflags & (1 << bitnum);              \

  }

#define IMPLEMENT_EFLAG_SET_ACCESSOR(name,bitnum)               \

  BX_CPP_INLINE void BX_CPU_C::assert_##name () {               \

    BX_CPU_THIS_PTR eflags |= (1<<bitnum);                      \

  }                                                             \

  BX_CPP_INLINE void BX_CPU_C::clear_##name () {                \

    BX_CPU_THIS_PTR eflags &= ~(1<<bitnum);                     \

  }                                                             \

  BX_CPP_INLINE void BX_CPU_C::set_##name (bx_bool val) {       \

    BX_CPU_THIS_PTR eflags =                                    \

      (BX_CPU_THIS_PTR eflags&~(1<<bitnum))|((val)<<bitnum);    \

  }

#if BX_CPU_LEVEL >= 4

#define IMPLEMENT_EFLAG_SET_ACCESSOR_AC(bitnum)                 \

  BX_CPP_INLINE void BX_CPU_C::assert_AC() {                    \

    BX_CPU_THIS_PTR eflags |= (1<<bitnum);                      \

    handleAlignmentCheck();                                     \

  }                                                             \

  BX_CPP_INLINE void BX_CPU_C::clear_AC() {                     \

    BX_CPU_THIS_PTR eflags &= ~(1<<bitnum);                     \

    handleAlignmentCheck();                                     \

  }                                                             \

  BX_CPP_INLINE void BX_CPU_C::set_AC(bx_bool val) {            \

    BX_CPU_THIS_PTR eflags =                                    \

      (BX_CPU_THIS_PTR eflags&~(1<<bitnum))|((val)<<bitnum);    \

    handleAlignmentCheck();                                     \

  }

#endif

#define IMPLEMENT_EFLAG_SET_ACCESSOR_VM(bitnum)                 \

  BX_CPP_INLINE void BX_CPU_C::assert_VM() {                    \

    set_VM(1);                                                  \

  }                                                             \

  BX_CPP_INLINE void BX_CPU_C::clear_VM() {                     \

    set_VM(0);                                                  \

  }                                                             \

  BX_CPP_INLINE void BX_CPU_C::set_VM(bx_bool val) {            \

    if (!long_mode()) {                                         \

      BX_CPU_THIS_PTR eflags =                                  \

        (BX_CPU_THIS_PTR eflags&~(1<<bitnum))|((val)<<bitnum);  \

      handleCpuModeChange();                                    \

    }                                                           \

  }

// need special handling when IF is set

#define IMPLEMENT_EFLAG_SET_ACCESSOR_IF(bitnum)                 \

  BX_CPP_INLINE void BX_CPU_C::assert_IF() {                    \

    BX_CPU_THIS_PTR eflags |= (1<<bitnum);                      \

    handleInterruptMaskChange();                                \

  }                                                             \

  BX_CPP_INLINE void BX_CPU_C::clear_IF() {                     \

    BX_CPU_THIS_PTR eflags &= ~(1<<bitnum);                     \

    handleInterruptMaskChange();                                \

  }                                                             \

  BX_CPP_INLINE void BX_CPU_C::set_IF(bx_bool val) {            \

    if (val) assert_IF();                                       \

    else clear_IF();                                            \

  }

// assert async_event when TF is set

#define IMPLEMENT_EFLAG_SET_ACCESSOR_TF(bitnum)                 \

  BX_CPP_INLINE void BX_CPU_C::assert_TF() {                    \

    BX_CPU_THIS_PTR async_event = 1;                            \

    BX_CPU_THIS_PTR eflags |= (1<<bitnum);                      \

  }                                                             \

  BX_CPP_INLINE void BX_CPU_C::clear_TF() {                     \

    BX_CPU_THIS_PTR eflags &= ~(1<<bitnum);                     \

  }                                                             \

  BX_CPP_INLINE void BX_CPU_C::set_TF(bx_bool val) {            \

    if (val) BX_CPU_THIS_PTR async_event = 1;                   \

    BX_CPU_THIS_PTR eflags =                                    \

      (BX_CPU_THIS_PTR eflags&~(1<<bitnum))|((val)<<bitnum);    \

  }

// invalidate prefetch queue and call prefetch() when RF is set

#define IMPLEMENT_EFLAG_SET_ACCESSOR_RF(bitnum)                 \

  BX_CPP_INLINE void BX_CPU_C::assert_RF() {                    \

    invalidate_prefetch_q();                                    \

    BX_CPU_THIS_PTR eflags |= (1<<bitnum);                      \

  }                                                             \

  BX_CPP_INLINE void BX_CPU_C::clear_RF() {                     \

    BX_CPU_THIS_PTR eflags &= ~(1<<bitnum);                     \

  }                                                             \

  BX_CPP_INLINE void BX_CPU_C::set_RF(bx_bool val) {            \

    if (val) invalidate_prefetch_q();                           \

    BX_CPU_THIS_PTR eflags =                                    \

      (BX_CPU_THIS_PTR eflags&~(1<<bitnum))|((val)<<bitnum);    \

  }

#define DECLARE_EFLAG_ACCESSOR_IOPL(bitnum)                     \

  BX_SMF BX_CPP_INLINE void set_IOPL(Bit32u val);               \

  BX_SMF BX_CPP_INLINE Bit32u  get_IOPL(void);

#define IMPLEMENT_EFLAG_ACCESSOR_IOPL(bitnum)                   \

  BX_CPP_INLINE void BX_CPU_C::set_IOPL(Bit32u val) {           \

    BX_CPU_THIS_PTR eflags &= ~(3<<12);                         \

    BX_CPU_THIS_PTR eflags |= ((3&val) << 12);                  \

  }                                                             \

  BX_CPP_INLINE Bit32u BX_CPU_C::get_IOPL() {                   \

    return 3 & (BX_CPU_THIS_PTR eflags >> 12);                  \

  }

#define EFlagsCFMask   (1 <<  0)

#define EFlagsPFMask   (1 <<  2)

#define EFlagsAFMask   (1 <<  4)

#define EFlagsZFMask   (1 <<  6)

#define EFlagsSFMask   (1 <<  7)

#define EFlagsTFMask   (1 <<  8)

#define EFlagsIFMask   (1 <<  9)

#define EFlagsDFMask   (1 << 10)

#define EFlagsOFMask   (1 << 11)

#define EFlagsIOPLMask (3 << 12)

#define EFlagsNTMask   (1 << 14)

#define EFlagsRFMask   (1 << 16)

#define EFlagsVMMask   (1 << 17)

#define EFlagsACMask   (1 << 18)

#define EFlagsVIFMask  (1 << 19)

#define EFlagsVIPMask  (1 << 20)

#define EFlagsIDMask   (1 << 21)

#define EFlagsOSZAPCMask \

    (EFlagsCFMask | EFlagsPFMask | EFlagsAFMask | EFlagsZFMask | EFlagsSFMask | EFlagsOFMask)

#define EFlagsOSZAPMask  \

    (EFlagsPFMask | EFlagsAFMask | EFlagsZFMask | EFlagsSFMask | EFlagsOFMask)

#define EFlagsValidMask  0x003f7fd5     // only supported bits for EFLAGS

#if BX_CPU_LEVEL >= 5

typedef struct

{

#if BX_SUPPORT_APIC

  bx_phy_address apicbase;

#endif

#define MSR_STAR   (BX_CPU_THIS_PTR msr.star)

  // SYSCALL/SYSRET instruction msr's

  Bit64u star;

#if BX_SUPPORT_X86_64

  Bit64u lstar;

  Bit64u cstar;

  Bit32u fmask;

  Bit64u kernelgsbase;

  Bit32u tsc_aux;

#endif

#if BX_CPU_LEVEL >= 6

  // SYSENTER/SYSEXIT instruction msr's

  Bit32u sysenter_cs_msr;

  bx_address sysenter_esp_msr;

  bx_address sysenter_eip_msr;

  Bit64u mtrrphys[16];

  Bit64u mtrrfix64k_00000;

  Bit64u mtrrfix16k[2];

  Bit64u mtrrfix4k[8];

  Bit16u mtrr_deftype;

  Bit64u pat;

#endif

#if BX_SUPPORT_VMX

  Bit32u ia32_feature_ctrl;

#endif

#if BX_SUPPORT_SVM

  Bit64u svm_hsave_pa;

#endif

  /* TODO finish of the others */

} bx_regs_msr_t;

#endif

#include "cpuid.h"

#include "crregs.h"

#include "descriptor.h"

#include "instr.h"

#include "lazy_flags.h"

// BX_TLB_SIZE: Number of entries in TLB

// BX_TLB_INDEX_OF(lpf): This macro is passed the linear page frame

//   (top 20 bits of the linear address.  It must map these bits to

//   one of the TLB cache slots, given the size of BX_TLB_SIZE.

//   There will be a many-to-one mapping to each TLB cache slot.

//   When there are collisions, the old entry is overwritten with

//   one for the newest access.

#define BX_TLB_SIZE 1024

#define BX_TLB_MASK ((BX_TLB_SIZE-1) << 12)

#define BX_TLB_INDEX_OF(lpf, len) ((((unsigned)(lpf) + (len)) & BX_TLB_MASK) >> 12)

typedef bx_ptr_equiv_t bx_hostpageaddr_t;

typedef struct {

  bx_address lpf;       // linear page frame

  bx_phy_address ppf;   // physical page frame

  bx_hostpageaddr_t hostPageAddr;

  Bit32u accessBits;

  Bit32u lpf_mask;      // linear address mask of the page size

} bx_TLB_entry;

#if BX_SUPPORT_X86_64

  #define LPF_MASK BX_CONST64(0xfffffffffffff000)

#else

  #define LPF_MASK (0xfffff000)

#endif

#if BX_PHY_ADDRESS_LONG

  #define PPF_MASK BX_CONST64(0xfffffffffffff000)

#else

  #define PPF_MASK (0xfffff000)