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[/] [ao486/] [trunk/] [bochs486/] [cpu/] [cpuid.h] - Blame information for rev 3

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1 2 alfik
/////////////////////////////////////////////////////////////////////////
2
// $Id: cpuid.h 11686 2013-05-17 19:41:57Z sshwarts $
3
/////////////////////////////////////////////////////////////////////////
4
//
5
//   Copyright (c) 2010-2013 Stanislav Shwartsman
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//          Written by Stanislav Shwartsman [sshwarts at sourceforge net]
7
//
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//  This library is free software; you can redistribute it and/or
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//  modify it under the terms of the GNU Lesser General Public
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//  License as published by the Free Software Foundation; either
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//  version 2 of the License, or (at your option) any later version.
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//
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//  This library is distributed in the hope that it will be useful,
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//  but WITHOUT ANY WARRANTY; without even the implied warranty of
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//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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//  Lesser General Public License for more details.
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//
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//  You should have received a copy of the GNU Lesser General Public
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//  License along with this library; if not, write to the Free Software
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//  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
21
//
22
/////////////////////////////////////////////////////////////////////////
23
 
24
#ifndef BX_CPU_MODEL_SPECIFIC
25
#define BX_CPU_MODEL_SPECIFIC
26
 
27
struct cpuid_function_t {
28
  Bit32u eax;
29
  Bit32u ebx;
30
  Bit32u ecx;
31
  Bit32u edx;
32
};
33
 
34
class bx_cpuid_t {
35
public:
36
  bx_cpuid_t(BX_CPU_C *_cpu);
37
  virtual ~bx_cpuid_t() {}
38
 
39
  // return CPU name
40
  virtual const char *get_name(void) const { return NULL; }
41
 
42
  virtual Bit64u get_isa_extensions_bitmask(void) const = 0;
43
  virtual Bit32u get_cpu_extensions_bitmask(void) const = 0;
44
#if BX_SUPPORT_VMX
45
  virtual Bit32u get_vmx_extensions_bitmask(void) const { return 0; }
46
#endif
47
#if BX_SUPPORT_SVM
48
  virtual Bit32u get_svm_extensions_bitmask(void) const { return 0; }
49
#endif
50
 
51
  virtual void get_cpuid_leaf(Bit32u function, Bit32u subfunction, cpuid_function_t *leaf) const = 0;
52
 
53
  virtual void dump_cpuid(void) const = 0;
54
 
55
#if BX_CPU_LEVEL >= 5
56
  virtual int rdmsr(Bit32u index, Bit64u *msr) { return -1; }
57
  virtual int wrmsr(Bit32u index, Bit64u  msr) { return -1; }
58
#endif
59
 
60
protected:
61
  BX_CPU_C *cpu;
62
 
63
  unsigned nprocessors;
64
  unsigned ncores;
65
  unsigned nthreads;
66
 
67
  void get_reserved_leaf(cpuid_function_t *leaf) const
68
  {
69
     leaf->eax = 0;
70
     leaf->ebx = 0;
71
     leaf->ecx = 0;
72
     leaf->edx = 0;
73
  }
74
};
75
 
76
typedef bx_cpuid_t* (*bx_create_cpuid_method)(BX_CPU_C *cpu);
77
 
78
// cpuid ISA (duplicated in disasm.h)
79
#define BX_ISA_X87                   (BX_CONST64(1) << 0)   /* FPU (X87) instruction */
80
#define BX_ISA_486                   (BX_CONST64(1) << 1)   /* 486 new instruction */
81
#define BX_ISA_PENTIUM               (BX_CONST64(1) << 2)   /* Pentium new instruction */
82
#define BX_ISA_P6                    (BX_CONST64(1) << 3)   /* P6 new instruction */
83
#define BX_ISA_MMX                   (BX_CONST64(1) << 4)   /* MMX instruction */
84
#define BX_ISA_3DNOW                 (BX_CONST64(1) << 5)   /* 3DNow! instruction (AMD) */
85
#define BX_ISA_SYSCALL_SYSRET_LEGACY (BX_CONST64(1) << 6)   /* SYSCALL/SYSRET in legacy mode (AMD) */
86
#define BX_ISA_SYSENTER_SYSEXIT      (BX_CONST64(1) << 7)   /* SYSENTER/SYSEXIT instruction */
87
#define BX_ISA_CLFLUSH               (BX_CONST64(1) << 8)   /* CLFLUSH instruction */
88
#define BX_ISA_SSE                   (BX_CONST64(1) << 9)   /* SSE  instruction */
89
#define BX_ISA_SSE2                  (BX_CONST64(1) << 10)  /* SSE2 instruction */
90
#define BX_ISA_SSE3                  (BX_CONST64(1) << 11)  /* SSE3 instruction */
91
#define BX_ISA_SSSE3                 (BX_CONST64(1) << 12)  /* SSSE3 instruction */
92
#define BX_ISA_SSE4_1                (BX_CONST64(1) << 13)  /* SSE4_1 instruction */
93
#define BX_ISA_SSE4_2                (BX_CONST64(1) << 14)  /* SSE4_2 instruction */
94
#define BX_ISA_POPCNT                (BX_CONST64(1) << 15)  /* POPCNT instruction */
95
#define BX_ISA_MONITOR_MWAIT         (BX_CONST64(1) << 16)  /* MONITOR/MWAIT instruction */
96
#define BX_ISA_VMX                   (BX_CONST64(1) << 17)  /* VMX instruction */
97
#define BX_ISA_SMX                   (BX_CONST64(1) << 18)  /* SMX instruction */
98
#define BX_ISA_LM_LAHF_SAHF          (BX_CONST64(1) << 19)  /* Long Mode LAHF/SAHF instruction */
99
#define BX_ISA_CMPXCHG16B            (BX_CONST64(1) << 20)  /* CMPXCHG16B instruction */
100
#define BX_ISA_RDTSCP                (BX_CONST64(1) << 21)  /* RDTSCP instruction */
101
#define BX_ISA_XSAVE                 (BX_CONST64(1) << 22)  /* XSAVE/XRSTOR extensions instruction */
102
#define BX_ISA_XSAVEOPT              (BX_CONST64(1) << 23)  /* XSAVEOPT instruction */
103
#define BX_ISA_AES_PCLMULQDQ         (BX_CONST64(1) << 24)  /* AES+PCLMULQDQ instruction */
104
#define BX_ISA_MOVBE                 (BX_CONST64(1) << 25)  /* MOVBE Intel Atom(R) instruction */
105
#define BX_ISA_FSGSBASE              (BX_CONST64(1) << 26)  /* FS/GS BASE access instruction */
106
#define BX_ISA_INVPCID               (BX_CONST64(1) << 27)  /* INVPCID instruction */
107
#define BX_ISA_AVX                   (BX_CONST64(1) << 28)  /* AVX instruction */
108
#define BX_ISA_AVX2                  (BX_CONST64(1) << 29)  /* AVX2 instruction */
109
#define BX_ISA_AVX_F16C              (BX_CONST64(1) << 30)  /* AVX F16 convert instruction */
110
#define BX_ISA_AVX_FMA               (BX_CONST64(1) << 31)  /* AVX FMA instruction */
111
#define BX_ISA_SSE4A                 (BX_CONST64(1) << 32)  /* SSE4A instruction (AMD) */
112
#define BX_ISA_LZCNT                 (BX_CONST64(1) << 33)  /* LZCNT instruction */
113
#define BX_ISA_BMI1                  (BX_CONST64(1) << 34)  /* BMI1 instruction */
114
#define BX_ISA_BMI2                  (BX_CONST64(1) << 35)  /* BMI2 instruction */
115
#define BX_ISA_FMA4                  (BX_CONST64(1) << 36)  /* FMA4 instruction (AMD) */
116
#define BX_ISA_XOP                   (BX_CONST64(1) << 37)  /* XOP instruction (AMD) */
117
#define BX_ISA_TBM                   (BX_CONST64(1) << 38)  /* TBM instruction (AMD) */
118
#define BX_ISA_SVM                   (BX_CONST64(1) << 39)  /* SVM instruction (AMD) */
119
#define BX_ISA_RDRAND                (BX_CONST64(1) << 40)  /* RDRAND instruction */
120
#define BX_ISA_ADX                   (BX_CONST64(1) << 41)  /* ADCX/ADOX instruction */
121
#define BX_ISA_SMAP                  (BX_CONST64(1) << 42)  /* SMAP support */
122
#define BX_ISA_RDSEED                (BX_CONST64(1) << 43)  /* RDSEED instruction */
123
 
124
// cpuid non-ISA features
125
#define BX_CPU_DEBUG_EXTENSIONS      (1 <<  0)              /* Debug Extensions support */
126
#define BX_CPU_VME                   (1 <<  1)              /* VME support */
127
#define BX_CPU_PSE                   (1 <<  2)              /* PSE support */
128
#define BX_CPU_PAE                   (1 <<  3)              /* PAE support */
129
#define BX_CPU_PGE                   (1 <<  4)              /* Global Pages support */
130
#define BX_CPU_PSE36                 (1 <<  5)              /* PSE-36 support */
131
#define BX_CPU_MTRR                  (1 <<  6)              /* MTRR support */
132
#define BX_CPU_PAT                   (1 <<  7)              /* PAT support */
133
#define BX_CPU_XAPIC                 (1 <<  8)              /* XAPIC support */
134
#define BX_CPU_X2APIC                (1 <<  9)              /* X2APIC support */
135
#define BX_CPU_XAPIC_EXT             (1 << 10)              /* XAPIC Extensions support */
136
#define BX_CPU_NX                    (1 << 11)              /* No-Execute support */
137
#define BX_CPU_LONG_MODE             (1 << 12)              /* Long Mode (x86-64) support */
138
#define BX_CPU_1G_PAGES              (1 << 13)              /* 1Gb pages support */
139
#define BX_CPU_PCID                  (1 << 14)              /* PCID pages support */
140
#define BX_CPU_SMEP                  (1 << 15)              /* SMEP support */
141
#define BX_CPU_FFXSR                 (1 << 16)              /* EFER.FFXSR support */
142
#define BX_CPU_ALT_MOV_CR8           (1 << 17)              /* LOCK CR0 access CR8 */
143
#define BX_CPU_TSC_DEADLINE          (1 << 18)              /* TSC-Deadline */
144
#define BX_CPU_MISALIGNED_SSE        (1 << 19)              /* Misaligned SSE */
145
 
146
// cpuid VMX features
147
#define BX_VMX_TPR_SHADOW            (1 <<  0)              /* TPR shadow */
148
#define BX_VMX_VIRTUAL_NMI           (1 <<  1)              /* Virtual NMI */
149
#define BX_VMX_APIC_VIRTUALIZATION   (1 <<  2)              /* APIC Access Virtualization */
150
#define BX_VMX_WBINVD_VMEXIT         (1 <<  3)              /* WBINVD VMEXIT */
151
#define BX_VMX_PERF_GLOBAL_CTRL      (1 <<  4)              /* Save/Restore MSR_PERF_GLOBAL_CTRL */
152
#define BX_VMX_MONITOR_TRAP_FLAG     (1 <<  5)              /* Monitor trap Flag (MTF) */
153
#define BX_VMX_X2APIC_VIRTUALIZATION (1 <<  6)              /* Virtualize X2APIC */
154
#define BX_VMX_EPT                   (1 <<  7)              /* Extended Page Tables (EPT) */
155
#define BX_VMX_VPID                  (1 <<  8)              /* VPID */
156
#define BX_VMX_UNRESTRICTED_GUEST    (1 <<  9)              /* Unrestricted Guest */
157
#define BX_VMX_PREEMPTION_TIMER      (1 << 10)              /* VMX preemption timer */
158
#define BX_VMX_SAVE_DEBUGCTL_DISABLE (1 << 11)              /* Disable Save/Restore of MSR_DEBUGCTL */
159
#define BX_VMX_PAT                   (1 << 12)              /* Save/Restore MSR_PAT */
160
#define BX_VMX_EFER                  (1 << 13)              /* Save/Restore MSR_EFER */
161
#define BX_VMX_DESCRIPTOR_TABLE_EXIT (1 << 14)              /* Descriptor Table VMEXIT */
162
#define BX_VMX_PAUSE_LOOP_EXITING    (1 << 15)              /* Pause Loop Exiting */
163
#define BX_VMX_EPTP_SWITCHING        (1 << 16)              /* EPTP switching (VM Function 0) */
164
#define BX_VMX_EPT_ACCESS_DIRTY      (1 << 17)              /* Extended Page Tables (EPT) A/D Bits */
165
#define BX_VMX_VINTR_DELIVERY        (1 << 18)              /* Virtual Interrupt Delivery */
166
#define BX_VMX_POSTED_INSTERRUPTS    (1 << 19)              /* Posted Interrupts support - not implemented yet */
167
#define BX_VMX_VMCS_SHADOWING        (1 << 20)              /* VMCS Shadowing */
168
#define BX_VMX_EPT_EXCEPTION         (1 << 21)              /* EPT Violation (#VE) exception */
169
 
170
// CPUID defines - STD features CPUID[0x00000001].EDX
171
// ----------------------------
172
 
173
// [0:0]   FPU on chip
174
// [1:1]   VME: Virtual-8086 Mode enhancements
175
// [2:2]   DE: Debug Extensions (I/O breakpoints)
176
// [3:3]   PSE: Page Size Extensions
177
// [4:4]   TSC: Time Stamp Counter
178
// [5:5]   MSR: RDMSR and WRMSR support
179
// [6:6]   PAE: Physical Address Extensions
180
// [7:7]   MCE: Machine Check Exception
181
// [8:8]   CXS: CMPXCHG8B instruction
182
// [9:9]   APIC: APIC on Chip
183
// [10:10] Reserved
184
// [11:11] SYSENTER/SYSEXIT support
185
// [12:12] MTRR: Memory Type Range Reg
186
// [13:13] PGE/PTE Global Bit
187
// [14:14] MCA: Machine Check Architecture
188
// [15:15] CMOV: Cond Mov/Cmp Instructions
189
// [16:16] PAT: Page Attribute Table
190
// [17:17] PSE-36: Physical Address Extensions
191
// [18:18] PSN: Processor Serial Number
192
// [19:19] CLFLUSH: CLFLUSH Instruction support
193
// [20:20] Reserved
194
// [21:21] DS: Debug Store
195
// [22:22] ACPI: Thermal Monitor and Software Controlled Clock Facilities
196
// [23:23] MMX Technology
197
// [24:24] FXSR: FXSAVE/FXRSTOR (also indicates CR4.OSFXSR is available)
198
// [25:25] SSE: SSE Extensions
199
// [26:26] SSE2: SSE2 Extensions
200
// [27:27] Self Snoop
201
// [28:28] Hyper Threading Technology
202
// [29:29] TM: Thermal Monitor
203
// [30:30] Reserved
204
// [31:31] PBE: Pending Break Enable
205
 
206
#define BX_CPUID_STD_X87                     (1 <<  0)
207
#define BX_CPUID_STD_VME                     (1 <<  1)
208
#define BX_CPUID_STD_DEBUG_EXTENSIONS        (1 <<  2)
209
#define BX_CPUID_STD_PSE                     (1 <<  3)
210
#define BX_CPUID_STD_TSC                     (1 <<  4)
211
#define BX_CPUID_STD_MSR                     (1 <<  5)
212
#define BX_CPUID_STD_PAE                     (1 <<  6)
213
#define BX_CPUID_STD_MCE                     (1 <<  7)
214
#define BX_CPUID_STD_CMPXCHG8B               (1 <<  8)
215
#define BX_CPUID_STD_APIC                    (1 <<  9)
216
#define BX_CPUID_STD_RESERVED10              (1 << 10)
217
#define BX_CPUID_STD_SYSENTER_SYSEXIT        (1 << 11)
218
#define BX_CPUID_STD_MTRR                    (1 << 12)
219
#define BX_CPUID_STD_GLOBAL_PAGES            (1 << 13)
220
#define BX_CPUID_STD_MCA                     (1 << 14)
221
#define BX_CPUID_STD_CMOV                    (1 << 15)
222
#define BX_CPUID_STD_PAT                     (1 << 16)
223
#define BX_CPUID_STD_PSE36                   (1 << 17)
224
#define BX_CPUID_STD_PROCESSOR_SERIAL_NUMBER (1 << 18)
225
#define BX_CPUID_STD_CLFLUSH                 (1 << 19)
226
#define BX_CPUID_STD_RESERVED20              (1 << 20)
227
#define BX_CPUID_STD_DEBUG_STORE             (1 << 21)
228
#define BX_CPUID_STD_ACPI                    (1 << 22)
229
#define BX_CPUID_STD_MMX                     (1 << 23)
230
#define BX_CPUID_STD_FXSAVE_FXRSTOR          (1 << 24)
231
#define BX_CPUID_STD_SSE                     (1 << 25)
232
#define BX_CPUID_STD_SSE2                    (1 << 26)
233
#define BX_CPUID_STD_SELF_SNOOP              (1 << 27)
234
#define BX_CPUID_STD_HT                      (1 << 28)
235
#define BX_CPUID_STD_THERMAL_MONITOR         (1 << 29)
236
#define BX_CPUID_STD_RESERVED30              (1 << 30)
237
#define BX_CPUID_STD_PBE                     (1 << 31)
238
 
239
// CPUID defines - EXT features CPUID[0x00000001].ECX
240
// ----------------------------
241
 
242
// [0:0]   SSE3: SSE3 Instructions
243
// [1:1]   PCLMULQDQ Instruction support
244
// [2:2]   DTES64: 64-bit DS area
245
// [3:3]   MONITOR/MWAIT support
246
// [4:4]   DS-CPL: CPL qualified debug store
247
// [5:5]   VMX: Virtual Machine Technology
248
// [6:6]   SMX: Secure Virtual Machine Technology
249
// [7:7]   EST: Enhanced Intel SpeedStep Technology
250
// [8:8]   TM2: Thermal Monitor 2
251
// [9:9]   SSSE3: SSSE3 Instructions
252
// [10:10] CNXT-ID: L1 context ID
253
// [11:11] reserved
254
// [12:12] FMA Instructions support
255
// [13:13] CMPXCHG16B: CMPXCHG16B instruction support
256
// [14:14] xTPR update control
257
// [15:15] PDCM - Perfon and Debug Capability MSR
258
// [16:16] reserved
259
// [17:17] PCID: Process Context Identifiers
260
// [18:18] DCA - Direct Cache Access
261
// [19:19] SSE4.1 Instructions
262
// [20:20] SSE4.2 Instructions
263
// [21:21] X2APIC
264
// [22:22] MOVBE instruction
265
// [23:23] POPCNT instruction
266
// [24:24] TSC Deadline
267
// [25:25] AES Instructions
268
// [26:26] XSAVE extensions support
269
// [27:27] OSXSAVE support
270
// [28:28] AVX extensions support
271
// [29:29] AVX F16C - Float16 conversion support
272
// [30:30] RDRAND instruction
273
// [31:31] reserved
274
 
275
#define BX_CPUID_EXT_SSE3                    (1 <<  0)
276
#define BX_CPUID_EXT_PCLMULQDQ               (1 <<  1)
277
#define BX_CPUID_EXT_DTES64                  (1 <<  2)
278
#define BX_CPUID_EXT_MONITOR_MWAIT           (1 <<  3)
279
#define BX_CPUID_EXT_DS_CPL                  (1 <<  4)
280
#define BX_CPUID_EXT_VMX                     (1 <<  5)
281
#define BX_CPUID_EXT_SMX                     (1 <<  6)
282
#define BX_CPUID_EXT_EST                     (1 <<  7)
283
#define BX_CPUID_EXT_THERMAL_MONITOR2        (1 <<  8)
284
#define BX_CPUID_EXT_SSSE3                   (1 <<  9)
285
#define BX_CPUID_EXT_CNXT_ID                 (1 << 10)
286
#define BX_CPUID_EXT_RESERVED11              (1 << 11)
287
#define BX_CPUID_EXT_FMA                     (1 << 12)
288
#define BX_CPUID_EXT_CMPXCHG16B              (1 << 13)
289
#define BX_CPUID_EXT_xTPR                    (1 << 14)
290
#define BX_CPUID_EXT_PDCM                    (1 << 15)
291
#define BX_CPUID_EXT_RESERVED16              (1 << 16)
292
#define BX_CPUID_EXT_PCID                    (1 << 17)
293
#define BX_CPUID_EXT_DCA                     (1 << 18)
294
#define BX_CPUID_EXT_SSE4_1                  (1 << 19)
295
#define BX_CPUID_EXT_SSE4_2                  (1 << 20)
296
#define BX_CPUID_EXT_X2APIC                  (1 << 21)
297
#define BX_CPUID_EXT_MOVBE                   (1 << 22)
298
#define BX_CPUID_EXT_POPCNT                  (1 << 23)
299
#define BX_CPUID_EXT_TSC_DEADLINE            (1 << 24)
300
#define BX_CPUID_EXT_AES                     (1 << 25)
301
#define BX_CPUID_EXT_XSAVE                   (1 << 26)
302
#define BX_CPUID_EXT_OSXSAVE                 (1 << 27)
303
#define BX_CPUID_EXT_AVX                     (1 << 28)
304
#define BX_CPUID_EXT_AVX_F16C                (1 << 29)
305
#define BX_CPUID_EXT_RDRAND                  (1 << 30)
306
#define BX_CPUID_EXT_RESERVED31              (1 << 31)
307
 
308
// CPUID defines - EXT3 features CPUID[0x00000007].EBX
309
// -----------------------------
310
 
311
//   [0:0]    FS/GS BASE access instructions
312
//   [2:1]    reserved
313
//   [3:3]    BMI1: Advanced Bit Manipulation Extensions
314
//   [4:4]    HLE: Hardware Lock Elision
315
//   [5:5]    AVX2
316
//   [6:6]    reserved
317
//   [7:7]    SMEP: Supervisor Mode Execution Protection
318
//   [8:8]    BMI2: Advanced Bit Manipulation Extensions
319
//   [9:9]    Support for Enhanced REP MOVSB/STOSB
320
//   [10:10]  Support for INVPCID instruction
321
//   [11:11]  RTM: Restricted Transactional Memory
322
//   [12:12]  Supports Quality of Service (QoS) capability
323
//   [13:13]  Deprecates FPU CS and FPU DS values
324
//   [17:14]  reserved
325
//   [18:18]  RDSEED instruction support
326
//   [19:19]  ADCX/ADOX instructions support
327
//   [20:20]  SMAP: Supervisor Mode Access Prevention
328
//   [31:21]  reserved
329
 
330
#define BX_CPUID_EXT3_FSGSBASE               (1 <<  0)
331
#define BX_CPUID_EXT3_RESERVED1              (1 <<  1)
332
#define BX_CPUID_EXT3_RESERVED2              (1 <<  2)
333
#define BX_CPUID_EXT3_BMI1                   (1 <<  3)
334
#define BX_CPUID_EXT3_HLE                    (1 <<  4)
335
#define BX_CPUID_EXT3_AVX2                   (1 <<  5)
336
#define BX_CPUID_EXT3_RESERVED6              (1 <<  6)
337
#define BX_CPUID_EXT3_SMEP                   (1 <<  7)
338
#define BX_CPUID_EXT3_BMI2                   (1 <<  8)
339
#define BX_CPUID_EXT3_ENCHANCED_REP_STRINGS  (1 <<  9)
340
#define BX_CPUID_EXT3_INVPCID                (1 << 10)
341
#define BX_CPUID_EXT3_RTM                    (1 << 11)
342
#define BX_CPUID_EXT3_QOS                    (1 << 12)
343
#define BX_CPUID_EXT3_DEPRECATE_FCS_FDS      (1 << 13)
344
#define BX_CPUID_EXT3_RESERVED14             (1 << 14)
345
#define BX_CPUID_EXT3_RESERVED15             (1 << 15)
346
#define BX_CPUID_EXT3_RESERVED16             (1 << 16)
347
#define BX_CPUID_EXT3_RESERVED17             (1 << 17)
348
#define BX_CPUID_EXT3_RDSEED                 (1 << 18)
349
#define BX_CPUID_EXT3_ADX                    (1 << 19)
350
#define BX_CPUID_EXT3_SMAP                   (1 << 20)
351
// ...
352
 
353
 
354
// CPUID defines - STD2 features CPUID[0x80000001].EDX
355
// -----------------------------
356
 
357
// ...
358
#define BX_CPUID_STD2_SYSCALL_SYSRET         (1 << 11)
359
// ...
360
#define BX_CPUID_STD2_NX                     (1 << 20)
361
#define BX_CPUID_STD2_RESERVED21             (1 << 21)
362
#define BX_CPUID_STD2_AMD_MMX_EXT            (1 << 22)
363
#define BX_CPUID_STD2_RESERVED23             (1 << 23)
364
#define BX_CPUID_STD2_RESERVED24             (1 << 24)
365
#define BX_CPUID_STD2_FFXSR                  (1 << 25)
366
#define BX_CPUID_STD2_1G_PAGES               (1 << 26)
367
#define BX_CPUID_STD2_RDTSCP                 (1 << 27)
368
#define BX_CPUID_STD2_RESERVED28             (1 << 28)
369
#define BX_CPUID_STD2_LONG_MODE              (1 << 29)
370
#define BX_CPUID_STD2_3DNOW_EXT              (1 << 30)
371
#define BX_CPUID_STD2_3DNOW                  (1 << 31)
372
 
373
// CPUID defines - EXT2 features CPUID[0x80000001].ECX
374
// -----------------------------
375
 
376
// [0:0]   LAHF/SAHF instructions support in 64-bit mode
377
// [1:1]   CMP_Legacy: Core multi-processing legacy mode (AMD)
378
// [2:2]   SVM: Secure Virtual Machine (AMD)
379
// [3:3]   Extended APIC Space
380
// [4:4]   AltMovCR8: LOCK MOV CR0 means MOV CR8
381
// [5:5]   LZCNT: LZCNT instruction support
382
// [6:6]   SSE4A: SSE4A Instructions support
383
// [7:7]   Misaligned SSE support
384
// [8:8]   PREFETCHW: PREFETCHW instruction support
385
// [9:9]   OSVW: OS visible workarounds (AMD)
386
// [10:10] IBS: Instruction based sampling
387
// [11:11] XOP: Extended Operations Support and XOP Prefix
388
// [12:12] SKINIT support
389
// [13:13] WDT: Watchdog timer support
390
// [14:14] reserved
391
// [15:15] LWP: Light weight profiling
392
// [16:16] FMA4: Four-operand FMA instructions support
393
// [18:17] reserved
394
// [19:19] NodeId: Indicates support for NodeId MSR (0xc001100c)
395
// [20:20] reserved
396
// [21:21] TBM: trailing bit manipulation instruction support
397
// [22:22] Topology extensions support
398
// [23:23] PerfCtrExtCore: core performance counter extensions support
399
// [24:24] PerfCtrExtNB: NB performance counter extensions support
400
// [25:25] Streaming performance monitor architecture.
401
// [26:26] Data breakpoint extension. Indicates support for MSR 0xC0011027 and MSRs 0xC001101[B:9].
402
// [27:27] Performance time-stamp counter. Indicates support for MSR 0xC0010280.
403
// [31:28] reserved
404
 
405
#define BX_CPUID_EXT2_LAHF_SAHF              (1 <<  0)
406
#define BX_CPUID_EXT2_CMP_LEGACY             (1 <<  1)
407
#define BX_CPUID_EXT2_SVM                    (1 <<  2)
408
#define BX_CPUID_EXT2_EXT_APIC_SPACE         (1 <<  3)
409
#define BX_CPUID_EXT2_ALT_MOV_CR8            (1 <<  4)
410
#define BX_CPUID_EXT2_LZCNT                  (1 <<  5)
411
#define BX_CPUID_EXT2_SSE4A                  (1 <<  6)
412
#define BX_CPUID_EXT2_MISALIGNED_SSE         (1 <<  7)
413
#define BX_CPUID_EXT2_PREFETCHW              (1 <<  8)
414
#define BX_CPUID_EXT2_OSVW                   (1 <<  9)
415
#define BX_CPUID_EXT2_IBS                    (1 << 10)
416
#define BX_CPUID_EXT2_XOP                    (1 << 11)
417
#define BX_CPUID_EXT2_SKINIT                 (1 << 12)
418
#define BX_CPUID_EXT2_WDT                    (1 << 13)
419
#define BX_CPUID_EXT2_RESERVED14             (1 << 14)
420
#define BX_CPUID_EXT2_LWP                    (1 << 15)
421
#define BX_CPUID_EXT2_FMA4                   (1 << 16)
422
#define BX_CPUID_EXT2_RESERVED17             (1 << 17)
423
#define BX_CPUID_EXT2_RESERVED18             (1 << 18)
424
#define BX_CPUID_EXT2_NODEID                 (1 << 19)
425
#define BX_CPUID_EXT2_RESERVED20             (1 << 20)
426
#define BX_CPUID_EXT2_TBM                    (1 << 21)
427
#define BX_CPUID_EXT2_TOPOLOGY_EXTENSIONS    (1 << 22)
428
#define BX_CPUID_EXT2_PERFCTR_EXT_CORE       (1 << 23)
429
#define BX_CPUID_EXT2_PERFCTR_EXT_NB         (1 << 24)
430
#define BX_CPUID_EXT2_STREAMING_PERFMON      (1 << 25)
431
#define BX_CPUID_EXT2_DATA_BREAKPOINT_EXT    (1 << 26)
432
#define BX_CPUID_EXT2_PERF_TSC               (1 << 27)
433
 
434
// CPUID defines - SVM features CPUID[0x8000000A].EDX
435
// ----------------------------
436
 
437
// [0:0]   NP - Nested paging support
438
// [1:1]   LBR virtualization
439
// [2:2]   SVM Lock
440
// [3:3]   NRIPS - Next RIP save on VMEXIT
441
// [4:4]   TscRate - MSR based TSC ratio control
442
// [5:5]   VMCB Clean bits support
443
// [6:6]   Flush by ASID support
444
// [7:7]   Decode assists support
445
// [8:8]   Reserved
446
// [9:9]   Reserved
447
// [10:10] Pause filter support
448
// [11:11] Reserved
449
// [12:12] Pause filter threshold support
450
// [13:13] Advanced Virtual Interrupt Controller
451
 
452
#define BX_CPUID_SVM_NESTED_PAGING           (1 <<  0)
453
#define BX_CPUID_SVM_LBR_VIRTUALIZATION      (1 <<  1)
454
#define BX_CPUID_SVM_SVM_LOCK                (1 <<  2)
455
#define BX_CPUID_SVM_NRIP_SAVE               (1 <<  3)
456
#define BX_CPUID_SVM_TSCRATE                 (1 <<  4)
457
#define BX_CPUID_SVM_VMCB_CLEAN_BITS         (1 <<  5)
458
#define BX_CPUID_SVM_FLUSH_BY_ASID           (1 <<  6)
459
#define BX_CPUID_SVM_DECODE_ASSIST           (1 <<  7)
460
#define BX_CPUID_SVM_RESERVED8               (1 <<  8)
461
#define BX_CPUID_SVM_RESERVED9               (1 <<  9)
462
#define BX_CPUID_SVM_PAUSE_FILTER            (1 << 10)
463
#define BX_CPUID_SVM_RESERVED11              (1 << 11)
464
#define BX_CPUID_SVM_PAUSE_FILTER_THRESHOLD  (1 << 12)
465
#define BX_CPUID_SVM_AVIC                    (1 << 13)
466
 
467
#endif

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