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[/] [ao486/] [trunk/] [bochs486/] [cpu/] [crregs.h] - Blame information for rev 7

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1 2 alfik
/////////////////////////////////////////////////////////////////////////
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// $Id: crregs.h 11572 2013-01-14 17:02:51Z sshwarts $
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/////////////////////////////////////////////////////////////////////////
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//
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//   Copyright (c) 2007-2011 Stanislav Shwartsman
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//          Written by Stanislav Shwartsman [sshwarts at sourceforge net]
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//
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//  This library is free software; you can redistribute it and/or
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//  modify it under the terms of the GNU Lesser General Public
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//  License as published by the Free Software Foundation; either
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//  version 2 of the License, or (at your option) any later version.
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//
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//  This library is distributed in the hope that it will be useful,
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//  but WITHOUT ANY WARRANTY; without even the implied warranty of
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//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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//  Lesser General Public License for more details.
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//
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//  You should have received a copy of the GNU Lesser General Public
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//  License along with this library; if not, write to the Free Software
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//  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
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//
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/////////////////////////////////////////////////////////////////////////
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#ifndef BX_CRREGS
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#define BX_CRREGS
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#define BX_CR0_PE_MASK         (1 <<  0)
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#define BX_CR0_MP_MASK         (1 <<  1)
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#define BX_CR0_EM_MASK         (1 <<  2)
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#define BX_CR0_TS_MASK         (1 <<  3)
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#define BX_CR0_ET_MASK         (1 <<  4)
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#define BX_CR0_NE_MASK         (1 <<  5)
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#define BX_CR0_WP_MASK         (1 << 16)
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#define BX_CR0_AM_MASK         (1 << 18)
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#define BX_CR0_NW_MASK         (1 << 29)
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#define BX_CR0_CD_MASK         (1 << 30)
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#define BX_CR0_PG_MASK         (1 << 31)
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struct bx_cr0_t {
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  Bit32u  val32; // 32bit value of register
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  // Accessors for all cr0 bitfields.
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#define IMPLEMENT_CRREG_ACCESSORS(name, bitnum)            \
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  BX_CPP_INLINE bx_bool get_##name() const {               \
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    return 1 & (val32 >> bitnum);                          \
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  }                                                        \
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  BX_CPP_INLINE void set_##name(Bit8u val) {               \
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    val32 = (val32 & ~(1<<bitnum)) | ((!!val) << bitnum);  \
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  }
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// CR0 notes:
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//   Each x86 level has its own quirks regarding how it handles
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//   reserved bits.  I used DOS DEBUG.EXE in real mode on the
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//   following processors, tried to clear bits 1..30, then tried
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//   to set bits 1..30, to see how these bits are handled.
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//   I found the following:
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//
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//   Processor    try to clear bits 1..30    try to set bits 1..30
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//   386          7FFFFFF0                   7FFFFFFE
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//   486DX2       00000010                   6005003E
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//   Pentium      00000010                   7FFFFFFE
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//   Pentium-II   00000010                   6005003E
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//
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// My assumptions:
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//   All processors: bit 4 is hardwired to 1 (not true on all clones)
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//   386: bits 5..30 of CR0 are also hardwired to 1
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//   Pentium: reserved bits retain value set using mov cr0, reg32
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//   486DX2/Pentium-II: reserved bits are hardwired to 0
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  IMPLEMENT_CRREG_ACCESSORS(PE, 0);
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  IMPLEMENT_CRREG_ACCESSORS(MP, 1);
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  IMPLEMENT_CRREG_ACCESSORS(EM, 2);
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  IMPLEMENT_CRREG_ACCESSORS(TS, 3);
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#if BX_CPU_LEVEL >= 4
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  IMPLEMENT_CRREG_ACCESSORS(ET, 4);
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  IMPLEMENT_CRREG_ACCESSORS(NE, 5);
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  IMPLEMENT_CRREG_ACCESSORS(WP, 16);
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  IMPLEMENT_CRREG_ACCESSORS(AM, 18);
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  IMPLEMENT_CRREG_ACCESSORS(NW, 29);
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  IMPLEMENT_CRREG_ACCESSORS(CD, 30);
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#endif
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  IMPLEMENT_CRREG_ACCESSORS(PG, 31);
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84
  BX_CPP_INLINE Bit32u get32() const { return val32; }
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  // ET is hardwired bit in CR0
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  BX_CPP_INLINE void set32(Bit32u val) { val32 = val | 0x10; }
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};
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#if BX_CPU_LEVEL >= 5
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#define BX_CR4_VME_MASK        (1 << 0)
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#define BX_CR4_PVI_MASK        (1 << 1)
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#define BX_CR4_TSD_MASK        (1 << 2)
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#define BX_CR4_DE_MASK         (1 << 3)
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#define BX_CR4_PSE_MASK        (1 << 4)
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#define BX_CR4_PAE_MASK        (1 << 5)
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#define BX_CR4_MCE_MASK        (1 << 6)
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#define BX_CR4_PGE_MASK        (1 << 7)
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#define BX_CR4_PCE_MASK        (1 << 8)
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#define BX_CR4_OSFXSR_MASK     (1 << 9)
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#define BX_CR4_OSXMMEXCPT_MASK (1 << 10)
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#define BX_CR4_VMXE_MASK       (1 << 13)
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#define BX_CR4_SMXE_MASK       (1 << 14)
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#define BX_CR4_FSGSBASE_MASK   (1 << 16)
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#define BX_CR4_PCIDE_MASK      (1 << 17)
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#define BX_CR4_OSXSAVE_MASK    (1 << 18)
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#define BX_CR4_SMEP_MASK       (1 << 20)
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#define BX_CR4_SMAP_MASK       (1 << 21)
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110
struct bx_cr4_t {
111
  Bit32u  val32; // 32bit value of register
112
 
113
  IMPLEMENT_CRREG_ACCESSORS(VME, 0);
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  IMPLEMENT_CRREG_ACCESSORS(PVI, 1);
115
  IMPLEMENT_CRREG_ACCESSORS(TSD, 2);
116
  IMPLEMENT_CRREG_ACCESSORS(DE,  3);
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  IMPLEMENT_CRREG_ACCESSORS(PSE, 4);
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  IMPLEMENT_CRREG_ACCESSORS(PAE, 5);
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  IMPLEMENT_CRREG_ACCESSORS(MCE, 6);
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  IMPLEMENT_CRREG_ACCESSORS(PGE, 7);
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  IMPLEMENT_CRREG_ACCESSORS(PCE, 8);
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  IMPLEMENT_CRREG_ACCESSORS(OSFXSR, 9);
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  IMPLEMENT_CRREG_ACCESSORS(OSXMMEXCPT, 10);
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#if BX_SUPPORT_VMX
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  IMPLEMENT_CRREG_ACCESSORS(VMXE, 13);
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#endif
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  IMPLEMENT_CRREG_ACCESSORS(SMXE, 14);
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#if BX_SUPPORT_X86_64
129
  IMPLEMENT_CRREG_ACCESSORS(FSGSBASE, 16);
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#endif
131
  IMPLEMENT_CRREG_ACCESSORS(PCIDE, 17);
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  IMPLEMENT_CRREG_ACCESSORS(OSXSAVE, 18);
133
  IMPLEMENT_CRREG_ACCESSORS(SMEP, 20);
134
  IMPLEMENT_CRREG_ACCESSORS(SMAP, 21);
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136
  BX_CPP_INLINE Bit32u get32() const { return val32; }
137
  BX_CPP_INLINE void set32(Bit32u val) { val32 = val; }
138
};
139
 
140
#define BX_CR4_FLUSH_TLB_MASK \
141
   (BX_CR4_PSE_MASK | BX_CR4_PAE_MASK | BX_CR4_PGE_MASK | BX_CR4_PCIDE_MASK | BX_CR4_SMEP_MASK | BX_CR4_SMAP_MASK)
142
 
143
#endif  // #if BX_CPU_LEVEL >= 5
144
 
145
struct bx_dr6_t {
146
  Bit32u val32; // 32bit value of register
147
 
148
  IMPLEMENT_CRREG_ACCESSORS(B0, 0);
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  IMPLEMENT_CRREG_ACCESSORS(B1, 1);
150
  IMPLEMENT_CRREG_ACCESSORS(B2, 2);
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  IMPLEMENT_CRREG_ACCESSORS(B3, 3);
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153
#define BX_DEBUG_TRAP_HIT             (1 << 12)
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#define BX_DEBUG_DR_ACCESS_BIT        (1 << 13)
155
#define BX_DEBUG_SINGLE_STEP_BIT      (1 << 14)
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#define BX_DEBUG_TRAP_TASK_SWITCH_BIT (1 << 15)
157
 
158
  IMPLEMENT_CRREG_ACCESSORS(BD, 13);
159
  IMPLEMENT_CRREG_ACCESSORS(BS, 14);
160
  IMPLEMENT_CRREG_ACCESSORS(BT, 15);
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162
  BX_CPP_INLINE Bit32u get32() const { return val32; }
163
  BX_CPP_INLINE void set32(Bit32u val) { val32 = val; }
164
};
165
 
166
struct bx_dr7_t {
167
  Bit32u val32; // 32bit value of register
168
 
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  IMPLEMENT_CRREG_ACCESSORS(L0, 0);
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  IMPLEMENT_CRREG_ACCESSORS(G0, 1);
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  IMPLEMENT_CRREG_ACCESSORS(L1, 2);
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  IMPLEMENT_CRREG_ACCESSORS(G1, 3);
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  IMPLEMENT_CRREG_ACCESSORS(L2, 4);
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  IMPLEMENT_CRREG_ACCESSORS(G2, 5);
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  IMPLEMENT_CRREG_ACCESSORS(L3, 6);
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  IMPLEMENT_CRREG_ACCESSORS(G3, 7);
177
  IMPLEMENT_CRREG_ACCESSORS(LE, 8);
178
  IMPLEMENT_CRREG_ACCESSORS(GE, 9);
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  IMPLEMENT_CRREG_ACCESSORS(GD, 13);
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181
#define IMPLEMENT_DRREG_ACCESSORS(name, bitmask, bitnum)      \
182
  int get_##name() const {                                    \
183
    return (val32 & (bitmask)) >> (bitnum);                   \
184
  }
185
 
186
  IMPLEMENT_DRREG_ACCESSORS(R_W0, 0x00030000, 16);
187
  IMPLEMENT_DRREG_ACCESSORS(LEN0, 0x000C0000, 18);
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  IMPLEMENT_DRREG_ACCESSORS(R_W1, 0x00300000, 20);
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  IMPLEMENT_DRREG_ACCESSORS(LEN1, 0x00C00000, 22);
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  IMPLEMENT_DRREG_ACCESSORS(R_W2, 0x03000000, 24);
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  IMPLEMENT_DRREG_ACCESSORS(LEN2, 0x0C000000, 26);
192
  IMPLEMENT_DRREG_ACCESSORS(R_W3, 0x30000000, 28);
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  IMPLEMENT_DRREG_ACCESSORS(LEN3, 0xC0000000, 30);
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195
  IMPLEMENT_DRREG_ACCESSORS(bp_enabled, 0xFF, 0);
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197
  BX_CPP_INLINE Bit32u get32() const { return val32; }
198
  BX_CPP_INLINE void set32(Bit32u val) { val32 = val; }
199
};
200
 
201
#if BX_CPU_LEVEL >= 5
202
 
203
#define BX_EFER_SCE_MASK       (1 <<  0)
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#define BX_EFER_LME_MASK       (1 <<  8)
205
#define BX_EFER_LMA_MASK       (1 << 10)
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#define BX_EFER_NXE_MASK       (1 << 11)
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#define BX_EFER_SVME_MASK      (1 << 12)
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#define BX_EFER_LMSLE_MASK     (1 << 13)
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#define BX_EFER_FFXSR_MASK     (1 << 14)
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211
struct bx_efer_t {
212
  Bit32u val32; // 32bit value of register
213
 
214
  IMPLEMENT_CRREG_ACCESSORS(SCE,    0);
215
#if BX_SUPPORT_X86_64
216
  IMPLEMENT_CRREG_ACCESSORS(LME,    8);
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  IMPLEMENT_CRREG_ACCESSORS(LMA,   10);
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#endif
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  IMPLEMENT_CRREG_ACCESSORS(NXE,   11);
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#if BX_SUPPORT_X86_64
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  IMPLEMENT_CRREG_ACCESSORS(SVME,  12); /* AMD Secure Virtual Machine */
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  IMPLEMENT_CRREG_ACCESSORS(LMSLE, 13); /* AMD Long Mode Segment Limit */
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  IMPLEMENT_CRREG_ACCESSORS(FFXSR, 14);
224
#endif
225
 
226
  BX_CPP_INLINE Bit32u get32() const { return val32; }
227
  BX_CPP_INLINE void set32(Bit32u val) { val32 = val; }
228
};
229
 
230
#endif
231
 
232
#if BX_CPU_LEVEL >= 6
233
 
234
struct xcr0_t {
235
  Bit32u  val32; // 32bit value of register
236
 
237
#define BX_XCR0_FPU_BIT   0
238
#define BX_XCR0_FPU_MASK (1<<BX_XCR0_FPU_BIT)
239
#define BX_XCR0_SSE_BIT   1
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#define BX_XCR0_SSE_MASK (1<<BX_XCR0_SSE_BIT)
241
#define BX_XCR0_AVX_BIT   2
242
#define BX_XCR0_AVX_MASK (1<<BX_XCR0_AVX_BIT)
243
 
244
  IMPLEMENT_CRREG_ACCESSORS(FPU, BX_XCR0_FPU_BIT);
245
  IMPLEMENT_CRREG_ACCESSORS(SSE, BX_XCR0_SSE_BIT);
246
  IMPLEMENT_CRREG_ACCESSORS(AVX, BX_XCR0_AVX_BIT);
247
 
248
  BX_CPP_INLINE Bit32u get32() const { return val32; }
249
  BX_CPP_INLINE void set32(Bit32u val) { val32 = val; }
250
};
251
#endif
252
 
253
#undef IMPLEMENT_CRREG_ACCESSORS
254
#undef IMPLEMENT_DRREG_ACCESSORS
255
 
256
#if BX_CPU_LEVEL >= 5
257
 
258
typedef struct msr {
259
  unsigned index;          // MSR index
260
  unsigned type;           // MSR type: 1 - lin address, 2 - phy address
261
#define BX_LIN_ADDRESS_MSR 1
262
#define BX_PHY_ADDRESS_MSR 2
263
  Bit64u val64;            // current MSR value
264
  Bit64u reset_value;      // reset value
265
  Bit64u reserved;         // r/o bits - fault on write
266
  Bit64u ignored;          // hardwired bits - ignored on write
267
 
268
  msr(unsigned idx, unsigned msr_type = 0, Bit64u reset_val = 0, Bit64u rsrv = 0, Bit64u ign = 0):
269
     index(idx), type(msr_type), val64(reset_val), reset_value(reset_val),
270
     reserved(rsrv), ignored(ign) {}
271
 
272
  msr(unsigned idx, Bit64u reset_val = 0, Bit64u rsrv = 0, Bit64u ign = 0):
273
     index(idx), type(0), val64(reset_val), reset_value(reset_val),
274
     reserved(rsrv), ignored(ign) {}
275
 
276
  BX_CPP_INLINE void reset() { val64 = reset_value; }
277
  BX_CPP_INLINE Bit64u get64() const { return val64; }
278
 
279
  BX_CPP_INLINE bx_bool set64(Bit64u new_val) {
280
     new_val = (new_val & ~ignored) | (val64 & ignored);
281
     switch(type) {
282
#if BX_SUPPORT_X86_64
283
       case BX_LIN_ADDRESS_MSR:
284
         if (! IsCanonical(new_val)) return 0;
285
         break;
286
#endif
287
       case BX_PHY_ADDRESS_MSR:
288
         if (! IsValidPhyAddr(new_val)) return 0;
289
         break;
290
       default:
291
         if ((val64 ^ new_val) & reserved) return 0;
292
         break;
293
     }
294
     val64 = new_val;
295
     return 1;
296
  }
297
} MSR;
298
 
299
#endif // BX_CPU_LEVEL >= 5
300
 
301
#endif

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