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[/] [ao486/] [trunk/] [bochs486/] [cpu/] [paging.cc] - Blame information for rev 2

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1 2 alfik
/////////////////////////////////////////////////////////////////////////
2
// $Id: paging.cc 11648 2013-03-06 21:11:23Z sshwarts $
3
/////////////////////////////////////////////////////////////////////////
4
//
5
//  Copyright (C) 2001-2013  The Bochs Project
6
//
7
//  This library is free software; you can redistribute it and/or
8
//  modify it under the terms of the GNU Lesser General Public
9
//  License as published by the Free Software Foundation; either
10
//  version 2 of the License, or (at your option) any later version.
11
//
12
//  This library is distributed in the hope that it will be useful,
13
//  but WITHOUT ANY WARRANTY; without even the implied warranty of
14
//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15
//  Lesser General Public License for more details.
16
//
17
//  You should have received a copy of the GNU Lesser General Public
18
//  License along with this library; if not, write to the Free Software
19
//  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
20
/////////////////////////////////////////////////////////////////////////
21
 
22
#define NEED_CPU_REG_SHORTCUTS 1
23
#include "bochs.h"
24
#include "cpu.h"
25
#define LOG_THIS BX_CPU_THIS_PTR
26
 
27
// X86 Registers Which Affect Paging:
28
// ==================================
29
//
30
// CR0:
31
//   bit 31: PG, Paging (386+)
32
//   bit 16: WP, Write Protect (486+)
33
//     0: allow   supervisor level writes into user level RO pages
34
//     1: inhibit supervisor level writes into user level RO pages
35
//
36
// CR3:
37
//   bit 31..12: PDBR, Page Directory Base Register (386+)
38
//   bit      4: PCD, Page level Cache Disable (486+)
39
//     Controls caching of current page directory.  Affects only the processor's
40
//     internal caches (L1 and L2).
41
//     This flag ignored if paging disabled (PG=0) or cache disabled (CD=1).
42
//     Values:
43
//       0: Page Directory can be cached
44
//       1: Page Directory not cached
45
//   bit      3: PWT, Page level Writes Transparent (486+)
46
//     Controls write-through or write-back caching policy of current page
47
//     directory.  Affects only the processor's internal caches (L1 and L2).
48
//     This flag ignored if paging disabled (PG=0) or cache disabled (CD=1).
49
//     Values:
50
//       0: write-back caching enabled
51
//       1: write-through caching enabled
52
//
53
// CR4:
54
//   bit 4: PSE, Page Size Extension (Pentium+)
55
//     0: 4KByte pages (typical)
56
//     1: 4MByte or 2MByte pages
57
//   bit 5: PAE, Physical Address Extension (Pentium Pro+)
58
//     0: 32bit physical addresses
59
//     1: 36bit physical addresses
60
//   bit 7: PGE, Page Global Enable (Pentium Pro+)
61
//     The global page feature allows frequently used or shared pages
62
//     to be marked as global (PDE or PTE bit 8).  Global pages are
63
//     not flushed from TLB on a task switch or write to CR3.
64
//     Values:
65
//       0: disables global page feature
66
//       1: enables global page feature
67
//
68
//    page size extention and physical address size extention matrix (legacy mode)
69
//   ==============================================================================
70
//   CR0.PG  CR4.PAE  CR4.PSE  PDPE.PS  PDE.PS | page size   physical address size
71
//   ==============================================================================
72
//      0       X        X       R         X   |   --          paging disabled
73
//      1       0        0       R         X   |   4K              32bits
74
//      1       0        1       R         0   |   4K              32bits
75
//      1       0        1       R         1   |   4M              32bits
76
//      1       1        X       R         0   |   4K              36bits
77
//      1       1        X       R         1   |   2M              36bits
78
 
79
//     page size extention and physical address size extention matrix (long mode)
80
//   ==============================================================================
81
//   CR0.PG  CR4.PAE  CR4.PSE  PDPE.PS  PDE.PS | page size   physical address size
82
//   ==============================================================================
83
//      1       1        X       0         0   |   4K              52bits
84
//      1       1        X       0         1   |   2M              52bits
85
//      1       1        X       1         -   |   1G              52bits
86
 
87
 
88
// Page Directory/Table Entry Fields Defined:
89
// ==========================================
90
// NX: No Execute
91
//   This bit controls the ability to execute code from all physical
92
//   pages mapped by the table entry.
93
//     0: Code can be executed from the mapped physical pages
94
//     1: Code cannot be executed
95
//   The NX bit can only be set when the no-execute page-protection
96
//   feature is enabled by setting EFER.NXE=1, If EFER.NXE=0, the
97
//   NX bit is treated as reserved. In this case, #PF occurs if the
98
//   NX bit is not cleared to zero.
99
//
100
// G: Global flag
101
//   Indiciates a global page when set.  When a page is marked
102
//   global and the PGE flag in CR4 is set, the page table or
103
//   directory entry for the page is not invalidated in the TLB
104
//   when CR3 is loaded or a task switch occurs.  Only software
105
//   clears and sets this flag.  For page directory entries that
106
//   point to page tables, this flag is ignored and the global
107
//   characteristics of a page are set in the page table entries.
108
//
109
// PS: Page Size flag
110
//   Only used in page directory entries.  When PS=0, the page
111
//   size is 4KBytes and the page directory entry points to a
112
//   page table.  When PS=1, the page size is 4MBytes for
113
//   normal 32-bit addressing and 2MBytes if extended physical
114
//   addressing.
115
//
116
// PAT: Page-Attribute Table
117
//   This bit is only present in the lowest level of the page
118
//   translation hierarchy. The PAT bit is the high-order bit
119
//   of a 3-bit index into the PAT register. The other two
120
//   bits involved in forming the index are the PCD and PWT
121
//   bits.
122
//
123
// D: Dirty bit:
124
//   Processor sets the Dirty bit in the 2nd-level page table before a
125
//   write operation to an address mapped by that page table entry.
126
//   Dirty bit in directory entries is undefined.
127
//
128
// A: Accessed bit:
129
//   Processor sets the Accessed bits in both levels of page tables before
130
//   a read/write operation to a page.
131
//
132
// PCD: Page level Cache Disable
133
//   Controls caching of individual pages or page tables.
134
//   This allows a per-page based mechanism to disable caching, for
135
//   those pages which contained memory mapped IO, or otherwise
136
//   should not be cached.  Processor ignores this flag if paging
137
//   is not used (CR0.PG=0) or the cache disable bit is set (CR0.CD=1).
138
//   Values:
139
//     0: page or page table can be cached
140
//     1: page or page table is not cached (prevented)
141
//
142
// PWT: Page level Write Through
143
//   Controls the write-through or write-back caching policy of individual
144
//   pages or page tables.  Processor ignores this flag if paging
145
//   is not used (CR0.PG=0) or the cache disable bit is set (CR0.CD=1).
146
//   Values:
147
//     0: write-back caching
148
//     1: write-through caching
149
//
150
// U/S: User/Supervisor level
151
//   0: Supervisor level - for the OS, drivers, etc.
152
//   1: User level - application code and data
153
//
154
// R/W: Read/Write access
155
//   0: read-only access
156
//   1: read/write access
157
//
158
// P: Present
159
//   0: Not present
160
//   1: Present
161
// ==========================================
162
 
163
// Combined page directory/page table protection:
164
// ==============================================
165
// There is one column for the combined effect on a 386
166
// and one column for the combined effect on a 486+ CPU.
167
// The 386 CPU behavior is not supported by Bochs.
168
//
169
// +----------------+-----------------+----------------+----------------+
170
// |  Page Directory|     Page Table  |   Combined 386 |  Combined 486+ |
171
// |Privilege  Type | Privilege  Type | Privilege  Type| Privilege  Type|
172
// |----------------+-----------------+----------------+----------------|
173
// |User       R    | User       R    | User       R   | User       R   |
174
// |User       R    | User       RW   | User       R   | User       R   |
175
// |User       RW   | User       R    | User       R   | User       R   |
176
// |User       RW   | User       RW   | User       RW  | User       RW  |
177
// |User       R    | Supervisor R    | User       R   | Supervisor RW  |
178
// |User       R    | Supervisor RW   | User       R   | Supervisor RW  |
179
// |User       RW   | Supervisor R    | User       R   | Supervisor RW  |
180
// |User       RW   | Supervisor RW   | User       RW  | Supervisor RW  |
181
// |Supervisor R    | User       R    | User       R   | Supervisor RW  |
182
// |Supervisor R    | User       RW   | User       R   | Supervisor RW  |
183
// |Supervisor RW   | User       R    | User       R   | Supervisor RW  |
184
// |Supervisor RW   | User       RW   | User       RW  | Supervisor RW  |
185
// |Supervisor R    | Supervisor R    | Supervisor RW  | Supervisor RW  |
186
// |Supervisor R    | Supervisor RW   | Supervisor RW  | Supervisor RW  |
187
// |Supervisor RW   | Supervisor R    | Supervisor RW  | Supervisor RW  |
188
// |Supervisor RW   | Supervisor RW   | Supervisor RW  | Supervisor RW  |
189
// +----------------+-----------------+----------------+----------------+
190
 
191
// Page Fault Error Code Format:
192
// =============================
193
//
194
// bits 31..4: Reserved
195
// bit  3: RSVD (Pentium Pro+)
196
//   0: fault caused by reserved bits set to 1 in a page directory
197
//      when the PSE or PAE flags in CR4 are set to 1
198
//   1: fault was not caused by reserved bit violation
199
// bit  2: U/S (386+)
200
//   0: fault originated when in supervior mode
201
//   1: fault originated when in user mode
202
// bit  1: R/W (386+)
203
//   0: access causing the fault was a read
204
//   1: access causing the fault was a write
205
// bit  0: P (386+)
206
//   0: fault caused by a nonpresent page
207
//   1: fault caused by a page level protection violation
208
 
209
// Some paging related notes:
210
// ==========================
211
//
212
// - When the processor is running in supervisor level, all pages are both
213
//   readable and writable (write-protect ignored).  When running at user
214
//   level, only pages which belong to the user level are accessible;
215
//   read/write & read-only are readable, read/write are writable.
216
//
217
// - If the Present bit is 0 in either level of page table, an
218
//   access which uses these entries will generate a page fault.
219
//
220
// - (A)ccess bit is used to report read or write access to a page
221
//   or 2nd level page table.
222
//
223
// - (D)irty bit is used to report write access to a page.
224
//
225
// - Processor running at CPL=0,1,2 maps to U/S=0
226
//   Processor running at CPL=3     maps to U/S=1
227
 
228
#if BX_SUPPORT_X86_64
229
  #define BX_INVALID_TLB_ENTRY BX_CONST64(0xffffffffffffffff)
230
#else
231
  #define BX_INVALID_TLB_ENTRY 0xffffffff
232
#endif
233
 
234
// bit [11] of the TLB lpf used for TLB_NoHostPtr valid indication
235
#define TLB_LPFOf(laddr) AlignedAccessLPFOf(laddr, 0x7ff)
236
 
237
#if BX_CPU_LEVEL >= 4
238
#  define BX_PRIV_CHECK_SIZE 32
239
#else
240
#  define BX_PRIV_CHECK_SIZE 16
241
#endif
242
 
243
// The 'priv_check' array is used to decide if the current access
244
// has the proper paging permissions.  An index is formed, based
245
// on parameters such as the access type and level, the write protect
246
// flag and values cached in the TLB.  The format of the index into this
247
// array is:
248
//
249
//   |4 |3 |2 |1 |0 |
250
//   |wp|us|us|rw|rw|
251
//    |  |  |  |  |
252
//    |  |  |  |  +---> r/w of current access
253
//    |  |  +--+------> u/s,r/w combined of page dir & table (cached)
254
//    |  +------------> u/s of current access
255
//    +---------------> Current CR0.WP value
256
 
257
/* 0xff0bbb0b */
258
static const Bit8u priv_check[BX_PRIV_CHECK_SIZE] =
259
{
260
  1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 0, 1, 1,
261
#if BX_CPU_LEVEL >= 4
262
  1, 0, 1, 1, 1, 0, 1, 1, 0, 0, 0, 0, 1, 0, 1, 1
263
#endif
264
};
265
 
266
#define BX_PAGING_PHY_ADDRESS_RESERVED_BITS \
267
    (BX_PHY_ADDRESS_RESERVED_BITS & BX_CONST64(0xfffffffffffff))
268
 
269
#define PAGE_DIRECTORY_NX_BIT (BX_CONST64(0x8000000000000000))
270
 
271
#define BX_CR3_PAGING_MASK    (BX_CONST64(0x000ffffffffff000))
272
 
273
// Each entry in the TLB cache has 3 entries:
274
//
275
//   lpf:         Linear Page Frame (page aligned linear address of page)
276
//     bits 32..12  Linear page frame
277
//     bit  11      0: TLB HostPtr access allowed, 1: not allowed
278
//     bit  10...0  Invalidate index
279
//
280
//   ppf:         Physical Page Frame (page aligned phy address of page)
281
//
282
//   hostPageAddr:
283
//                Host Page Frame address used for direct access to
284
//                the mem.vector[] space allocated for the guest physical
285
//                memory.  If this is zero, it means that a pointer
286
//                to the host space could not be generated, likely because
287
//                that page of memory is not standard memory (it might
288
//                be memory mapped IO, ROM, etc).
289
//
290
//   accessBits:
291
//
292
//     bit  31:     Page is a global page.
293
//
294
//       The following bits are used for a very efficient permissions
295
//       check.  The goal is to be able, using only the current privilege
296
//       level and access type, to determine if the page tables allow the
297
//       access to occur or at least should rewalk the page tables.  On
298
//       the first read access, permissions are set to only read, so a
299
//       rewalk is necessary when a subsequent write fails the tests.
300
//       This allows for the dirty bit to be set properly, but for the
301
//       test to be efficient.  Note that the CR0.WP flag is not present.
302
//       The values in the following flags is based on the current CR0.WP
303
//       value, necessitating a TLB flush when CR0.WP changes.
304
//
305
//       The test bit:
306
//         OK = 1 << ((E<<2) | (W<<1) | U)
307
//
308
//       where E:1=Execute, 0=Data;
309
//             W:1=Write, 0=Read;
310
//             U:1=CPL3, 0=CPL0-2
311
//       
312
//       Thus for reads, it is:
313
//         OK = 0x01 << (          U )
314
//       for writes:
315
//         OK = 0x04 << (          U )
316
//       for code fetches:
317
//         OK = 0x10 << (          U )
318
//
319
//     bit 5: Execute from User   privilege is OK
320
//     bit 4: Execute from System privilege is OK
321
//     bit 3: Write   from User   privilege is OK
322
//     bit 2: Write   from System privilege is OK
323
//     bit 1: Read    from User   privilege is OK
324
//     bit 0: Read    from System privilege is OK
325
//
326
//       Note, that the TLB should have TLB_NoHostPtr bit set in the lpf when
327
//       direct access through host pointer is NOT allowed for the page.
328
//       A memory operation asking for a direct access through host pointer
329
//       will not set TLB_NoHostPtr bit in its lpf and thus get TLB miss 
330
//       result when the direct access is not allowed.
331
//
332
 
333
#define TLB_NoHostPtr   (0x800) /* set this bit when direct access is NOT allowed */
334
#define TLB_GlobalPage  (0x80000000)
335
 
336
#define TLB_SysReadOK     (0x01)
337
#define TLB_UserReadOK    (0x02)
338
#define TLB_SysWriteOK    (0x04)
339
#define TLB_UserWriteOK   (0x08)
340
#define TLB_SysExecuteOK  (0x10)
341
#define TLB_UserExecuteOK (0x20)
342
 
343
// === TLB Instrumentation section ==============================
344
 
345
// Note: this is an approximation of what Peter Tattam had.
346
 
347
#define InstrumentTLB 0
348
 
349
#if InstrumentTLB
350
static unsigned tlbLookups=0;
351
static unsigned tlbMisses=0;
352
static unsigned tlbGlobalFlushes=0;
353
static unsigned tlbNonGlobalFlushes=0;
354
 
355
#define InstrTLB_StatsMask 0xfffff
356
 
357
#define InstrTLB_Stats() {\
358
  if ((tlbLookups & InstrTLB_StatsMask) == 0) { \
359
    BX_INFO(("TLB lookup:%8d miss:%8d %6.2f%% flush:%8d %6.2f%%", \
360
          tlbLookups, \
361
          tlbMisses, \
362
          tlbMisses * 100.0 / tlbLookups, \
363
          (tlbGlobalFlushes+tlbNonGlobalFlushes), \
364
          (tlbGlobalFlushes+tlbNonGlobalFlushes) * 100.0 / tlbLookups \
365
          )); \
366
    tlbLookups = tlbMisses = tlbGlobalFlushes = tlbNonGlobalFlushes = 0; \
367
    } \
368
  }
369
#define InstrTLB_Increment(v) (v)++
370
 
371
#else
372
#define InstrTLB_Stats()
373
#define InstrTLB_Increment(v)
374
#endif
375
 
376
// ==============================================================
377
 
378
void BX_CPU_C::TLB_flush(void)
379
{
380
#if InstrumentTLB
381
  InstrTLB_Increment(tlbGlobalFlushes);
382
#endif
383
 
384
  invalidate_prefetch_q();
385
 
386
  invalidate_stack_cache();
387
 
388
  for (unsigned n=0; n<BX_TLB_SIZE; n++) {
389
    BX_CPU_THIS_PTR TLB.entry[n].lpf = BX_INVALID_TLB_ENTRY;
390
    BX_CPU_THIS_PTR TLB.entry[n].accessBits = 0;
391
  }
392
 
393
#if BX_CPU_LEVEL >= 5
394
  BX_CPU_THIS_PTR TLB.split_large = 0;  // flush whole TLB
395
#endif
396
 
397
#if BX_SUPPORT_MONITOR_MWAIT
398
  // invalidating of the TLB might change translation for monitored page
399
  // and cause subsequent MWAIT instruction to wait forever
400
  BX_CPU_THIS_PTR monitor.reset_monitor();
401
#endif
402
}
403
 
404
#if BX_CPU_LEVEL >= 6
405
void BX_CPU_C::TLB_flushNonGlobal(void)
406
{
407
#if InstrumentTLB
408
  InstrTLB_Increment(tlbNonGlobalFlushes);
409
#endif
410
 
411
  invalidate_prefetch_q();
412
 
413
  invalidate_stack_cache();
414
 
415
  BX_CPU_THIS_PTR TLB.split_large = 0;
416
  Bit32u lpf_mask = 0;
417
 
418
  for (unsigned n=0; n<BX_TLB_SIZE; n++) {
419
    bx_TLB_entry *tlbEntry = &BX_CPU_THIS_PTR TLB.entry[n];
420
    if (!(tlbEntry->accessBits & TLB_GlobalPage)) {
421
      tlbEntry->lpf = BX_INVALID_TLB_ENTRY;
422
      tlbEntry->accessBits = 0;
423
    }
424
    else {
425
      lpf_mask |= tlbEntry->lpf_mask;
426
    }
427
  }
428
 
429
  if (lpf_mask > 0xfff)
430
    BX_CPU_THIS_PTR TLB.split_large = 1;
431
 
432
#if BX_SUPPORT_MONITOR_MWAIT
433
  // invalidating of the TLB might change translation for monitored page
434
  // and cause subsequent MWAIT instruction to wait forever
435
  BX_CPU_THIS_PTR monitor.reset_monitor();
436
#endif
437
}
438
#endif
439
 
440
void BX_CPU_C::TLB_invlpg(bx_address laddr)
441
{
442
  invalidate_prefetch_q();
443
 
444
  invalidate_stack_cache();
445
 
446
  BX_DEBUG(("TLB_invlpg(0x"FMT_ADDRX"): invalidate TLB entry", laddr));
447
 
448
#if BX_CPU_LEVEL >= 5
449
  if (BX_CPU_THIS_PTR TLB.split_large)
450
  {
451
    Bit32u lpf_mask = 0;
452
    BX_CPU_THIS_PTR TLB.split_large = 0;
453
 
454
    // make sure INVLPG handles correctly large pages
455
    for (unsigned n=0; n<BX_TLB_SIZE; n++) {
456
      bx_TLB_entry *tlbEntry = &BX_CPU_THIS_PTR TLB.entry[n];
457
      bx_address entry_lpf_mask = tlbEntry->lpf_mask;
458
      if ((laddr & ~entry_lpf_mask) == (tlbEntry->lpf & ~entry_lpf_mask)) {
459
        tlbEntry->lpf = BX_INVALID_TLB_ENTRY;
460
        tlbEntry->accessBits = 0;
461
      }
462
      else {
463
        lpf_mask |= entry_lpf_mask;
464
      }
465
    }
466
 
467
    if (lpf_mask > 0xfff)
468
      BX_CPU_THIS_PTR TLB.split_large = 1;
469
  }
470
  else
471
#endif
472
  {
473
    unsigned TLB_index = BX_TLB_INDEX_OF(laddr, 0);
474
    bx_address lpf = LPFOf(laddr);
475
    bx_TLB_entry *tlbEntry = &BX_CPU_THIS_PTR TLB.entry[TLB_index];
476
    if (TLB_LPFOf(tlbEntry->lpf) == lpf) {
477
      tlbEntry->lpf = BX_INVALID_TLB_ENTRY;
478
      tlbEntry->accessBits = 0;
479
    }
480
  }
481
 
482
#if BX_SUPPORT_MONITOR_MWAIT
483
  // invalidating of the TLB entry might change translation for monitored
484
  // page and cause subsequent MWAIT instruction to wait forever
485
  BX_CPU_THIS_PTR monitor.reset_monitor();
486
#endif
487
}
488
 
489
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::INVLPG(bxInstruction_c* i)
490
{
491
  // CPL is always 0 in real mode
492
  if (/* !real_mode() && */ CPL!=0) {
493
    BX_ERROR(("INVLPG: priveledge check failed, generate #GP(0)"));
494
    exception(BX_GP_EXCEPTION, 0);
495
  }
496
 
497
  bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
498
  bx_address laddr = get_laddr(i->seg(), eaddr);
499
 
500
#if BX_SUPPORT_VMX
501
  if (BX_CPU_THIS_PTR in_vmx_guest) {
502
    if (VMEXIT(VMX_VM_EXEC_CTRL2_INVLPG_VMEXIT)) VMexit(VMX_VMEXIT_INVLPG, laddr);
503
  }
504
#endif
505
 
506
#if BX_SUPPORT_SVM
507
  if (BX_CPU_THIS_PTR in_svm_guest) {
508
    if (SVM_INTERCEPT(SVM_INTERCEPT0_INVLPG))
509
      Svm_Vmexit(SVM_VMEXIT_INVLPG, BX_SUPPORT_SVM_EXTENSION(BX_CPUID_SVM_DECODE_ASSIST) ? laddr : 0);
510
  }
511
#endif
512
 
513
#if BX_SUPPORT_X86_64
514
  if (IsCanonical(laddr))
515
#endif
516
  {
517
    BX_INSTR_TLB_CNTRL(BX_CPU_ID, BX_INSTR_INVLPG, laddr);
518
    TLB_invlpg(laddr);
519
  }
520
 
521
  BX_NEXT_TRACE(i);
522
}
523
 
524
// error checking order - page not present, reserved bits, protection
525
#define ERROR_NOT_PRESENT       0x00
526
#define ERROR_PROTECTION        0x01
527
#define ERROR_RESERVED          0x08
528
#define ERROR_CODE_ACCESS       0x10
529
 
530
void BX_CPU_C::page_fault(unsigned fault, bx_address laddr, unsigned user, unsigned rw)
531
{
532
  unsigned isWrite = rw & 1;
533
 
534
  Bit32u error_code = fault | (user << 2) | (isWrite << 1);
535
 
536
#if BX_CPU_LEVEL >= 6
537
  if (rw == BX_EXECUTE) {
538
    if (BX_CPU_THIS_PTR cr4.get_SMEP())
539
      error_code |= ERROR_CODE_ACCESS; // I/D = 1
540
    if (BX_CPU_THIS_PTR cr4.get_PAE() && BX_CPU_THIS_PTR efer.get_NXE())
541
      error_code |= ERROR_CODE_ACCESS;
542
  }
543
#endif
544
 
545
#if BX_SUPPORT_SVM
546
  SvmInterceptException(BX_HARDWARE_EXCEPTION, BX_PF_EXCEPTION, error_code, 1, laddr); // before the CR2 was modified
547
#endif
548
 
549
#if BX_SUPPORT_VMX
550
  VMexit_Event(BX_HARDWARE_EXCEPTION, BX_PF_EXCEPTION, error_code, 1, laddr); // before the CR2 was modified
551
#endif
552
 
553
  BX_CPU_THIS_PTR cr2 = laddr;
554
 
555
#if BX_SUPPORT_X86_64
556
  BX_DEBUG(("page fault for address %08x%08x @ %08x%08x",
557
             GET32H(laddr), GET32L(laddr), GET32H(RIP), GET32L(RIP)));
558
#else
559
  BX_DEBUG(("page fault for address %08x @ %08x", laddr, EIP));
560
#endif
561
 
562
  exception(BX_PF_EXCEPTION, error_code);
563
}
564
 
565
#define BX_LEVEL_PML4  3
566
#define BX_LEVEL_PDPTE 2
567
#define BX_LEVEL_PDE   1
568
#define BX_LEVEL_PTE   0
569
 
570
static const char *bx_paging_level[4] = { "PTE", "PDE", "PDPE", "PML4" }; // keep it 4 letters
571
 
572
#if BX_CPU_LEVEL >= 6
573
 
574
//                Format of a Long Mode Non-Leaf Entry
575
// -----------------------------------------------------------
576
// 00    | Present (P)
577
// 01    | R/W
578
// 02    | U/S
579
// 03    | Page-Level Write-Through (PWT)
580
// 04    | Page-Level Cache-Disable (PCD)
581
// 05    | Accessed (A)
582
// 06    | (ignored)
583
// 07    | Page Size (PS), must be 0 if no Large Page on the level
584
// 11-08 | (ignored)
585
// PA-12 | Physical address of 4-KByte aligned page-directory-pointer table
586
// 51-PA | Reserved (must be zero)
587
// 62-52 | (ignored)
588
// 63    | Execute-Disable (XD) (if EFER.NXE=1, reserved otherwise)
589
// -----------------------------------------------------------
590
 
591
#define PAGING_PAE_RESERVED_BITS (BX_PAGING_PHY_ADDRESS_RESERVED_BITS)
592
 
593
// in legacy PAE mode bits [62:52] are reserved. bit 63 is NXE
594
#define PAGING_LEGACY_PAE_RESERVED_BITS \
595
             (BX_PAGING_PHY_ADDRESS_RESERVED_BITS | BX_CONST64(0x7ff0000000000000))
596
 
597
//       Format of a PDPTE that References a 1-GByte Page
598
// -----------------------------------------------------------
599
// 00    | Present (P)
600
// 01    | R/W
601
// 02    | U/S
602
// 03    | Page-Level Write-Through (PWT)
603
// 04    | Page-Level Cache-Disable (PCD)
604
// 05    | Accessed (A)
605
// 06    | (ignored)
606
// 07    | Page Size, must be 1 to indicate a 1-GByte Page
607
// 08    | Global (G) (if CR4.PGE=1, ignored otherwise)
608
// 11-09 | (ignored)
609
// 12    | PAT (if PAT is supported, reserved otherwise)
610
// 29-13 | Reserved (must be zero)
611
// PA-30 | Physical address of the 1-Gbyte Page
612
// 51-PA | Reserved (must be zero)
613
// 62-52 | (ignored)
614
// 63    | Execute-Disable (XD) (if EFER.NXE=1, reserved otherwise)
615
// -----------------------------------------------------------
616
 
617
#define PAGING_PAE_PDPTE1G_RESERVED_BITS \
618
    (BX_PAGING_PHY_ADDRESS_RESERVED_BITS | BX_CONST64(0x3FFFE000))
619
 
620
//        Format of a PAE PDE that Maps a 2-MByte Page
621
// -----------------------------------------------------------
622
// 00    | Present (P)
623
// 01    | R/W
624
// 02    | U/S
625
// 03    | Page-Level Write-Through (PWT)
626
// 04    | Page-Level Cache-Disable (PCD)
627
// 05    | Accessed (A)
628
// 06    | Dirty (D)
629
// 07    | Page Size (PS), must be 1 to indicate a 2-MByte Page
630
// 08    | Global (G) (if CR4.PGE=1, ignored otherwise)
631
// 11-09 | (ignored)
632
// 12    | PAT (if PAT is supported, reserved otherwise)
633
// 20-13 | Reserved (must be zero)
634
// PA-21 | Physical address of the 2-MByte page
635
// 51-PA | Reserved (must be zero)
636
// 62-52 | ignored in long mode, reserved (must be 0) in legacy PAE mode
637
// 63    | Execute-Disable (XD) (if EFER.NXE=1, reserved otherwise)
638
// -----------------------------------------------------------
639
 
640
#define PAGING_PAE_PDE2M_RESERVED_BITS \
641
    (BX_PAGING_PHY_ADDRESS_RESERVED_BITS | BX_CONST64(0x001FE000))
642
 
643
//        Format of a PAE PTE that Maps a 4-KByte Page
644
// -----------------------------------------------------------
645
// 00    | Present (P)
646
// 01    | R/W
647
// 02    | U/S
648
// 03    | Page-Level Write-Through (PWT)
649
// 04    | Page-Level Cache-Disable (PCD)
650
// 05    | Accessed (A)
651
// 06    | Dirty (D)
652
// 07    | PAT (if PAT is supported, reserved otherwise)
653
// 08    | Global (G) (if CR4.PGE=1, ignored otherwise)
654
// 11-09 | (ignored)
655
// PA-12 | Physical address of the 4-KByte page
656
// 51-PA | Reserved (must be zero)
657
// 62-52 | ignored in long mode, reserved (must be 0) in legacy PAE mode
658
// 63    | Execute-Disable (XD) (if EFER.NXE=1, reserved otherwise)
659
// -----------------------------------------------------------
660
 
661
int BX_CPU_C::check_entry_PAE(const char *s, Bit64u entry, Bit64u reserved, unsigned rw, bx_bool *nx_fault)
662
{
663
  if (!(entry & 0x1)) {
664
    BX_DEBUG(("PAE %s: entry not present", s));
665
    return ERROR_NOT_PRESENT;
666
  }
667
 
668
  if (entry & reserved) {
669
    BX_DEBUG(("PAE %s: reserved bit is set 0x" FMT_ADDRX64, s, entry));
670
    return ERROR_RESERVED | ERROR_PROTECTION;
671
  }
672
 
673
  if (entry & PAGE_DIRECTORY_NX_BIT) {
674
    if (rw == BX_EXECUTE) {
675
      BX_DEBUG(("PAE %s: non-executable page fault occured", s));
676
      *nx_fault = 1;
677
    }
678
  }
679
 
680
  return -1;
681
}
682
 
683
#if BX_SUPPORT_X86_64
684
 
685
// Translate a linear address to a physical address in long mode
686
bx_phy_address BX_CPU_C::translate_linear_long_mode(bx_address laddr, Bit32u &lpf_mask, Bit32u &combined_access, unsigned user, unsigned rw)
687
{
688
  bx_phy_address entry_addr[4];
689
  bx_phy_address ppf = BX_CPU_THIS_PTR cr3 & BX_CR3_PAGING_MASK;
690
  Bit64u entry[4];
691
  bx_bool nx_fault = 0;
692
  int leaf;
693
 
694
  Bit64u offset_mask = BX_CONST64(0x0000ffffffffffff);
695
  lpf_mask = 0xfff;
696
  combined_access = 0x06;
697
 
698
  Bit64u reserved = PAGING_PAE_RESERVED_BITS;
699
  if (! BX_CPU_THIS_PTR efer.get_NXE())
700
    reserved |= PAGE_DIRECTORY_NX_BIT;
701
 
702
  for (leaf = BX_LEVEL_PML4;; --leaf) {
703
    entry_addr[leaf] = ppf + ((laddr >> (9 + 9*leaf)) & 0xff8);
704
#if BX_SUPPORT_VMX >= 2
705
    if (BX_CPU_THIS_PTR in_vmx_guest) {
706
      if (SECONDARY_VMEXEC_CONTROL(VMX_VM_EXEC_CTRL3_EPT_ENABLE))
707
        entry_addr[leaf] = translate_guest_physical(entry_addr[leaf], laddr, 1, 1, BX_READ);
708
    }
709
#endif
710
#if BX_SUPPORT_SVM
711
    if (BX_CPU_THIS_PTR in_svm_guest && SVM_NESTED_PAGING_ENABLED) {
712
      entry_addr[leaf] = nested_walk(entry_addr[leaf], BX_RW, 1);
713
    }
714
#endif
715
    access_read_physical(entry_addr[leaf], 8, &entry[leaf]);
716
    BX_NOTIFY_PHY_MEMORY_ACCESS(entry_addr[leaf], 8, BX_READ, (BX_PTE_ACCESS + leaf), (Bit8u*)(&entry[leaf]));
717
    offset_mask >>= 9;
718
 
719
    Bit64u curr_entry = entry[leaf];
720
    int fault = check_entry_PAE(bx_paging_level[leaf], curr_entry, reserved, rw, &nx_fault);
721
    if (fault >= 0)
722
      page_fault(fault, laddr, user, rw);
723
 
724
    combined_access &= curr_entry; // U/S and R/W
725
    ppf = curr_entry & BX_CONST64(0x000ffffffffff000);
726
 
727
    if (leaf == BX_LEVEL_PTE) break;
728
 
729
    if (curr_entry & 0x80) {
730
      if (leaf > (BX_LEVEL_PDE + !!bx_cpuid_support_1g_paging())) {
731
        BX_DEBUG(("PAE %s: PS bit set !", bx_paging_level[leaf]));
732
        page_fault(ERROR_RESERVED | ERROR_PROTECTION, laddr, user, rw);
733
      }
734
 
735
      ppf &= BX_CONST64(0x000fffffffffe000);
736
      if (ppf & offset_mask) {
737
         BX_DEBUG(("PAE %s: reserved bit is set: 0x" FMT_ADDRX64, bx_paging_level[leaf], curr_entry));
738
         page_fault(ERROR_RESERVED | ERROR_PROTECTION, laddr, user, rw);
739
      }
740
 
741
      lpf_mask = (Bit32u) offset_mask;
742
      break;
743
    }
744
  }
745
 
746
  bx_bool isWrite = (rw & 1); // write or r-m-w
747
 
748
  unsigned priv_index = (BX_CPU_THIS_PTR cr0.get_WP() << 4) | // bit 4
749
                        (user<<3) |                           // bit 3
750
                        (combined_access | isWrite);          // bit 2,1,0
751
 
752
  if (!priv_check[priv_index] || nx_fault)
753
    page_fault(ERROR_PROTECTION, laddr, user, rw);
754
 
755
  if (BX_CPU_THIS_PTR cr4.get_SMEP() && rw == BX_EXECUTE && !user) {
756
    if (combined_access & 0x4) // User page
757
      page_fault(ERROR_PROTECTION, laddr, user, rw);
758
  }
759
 
760
  // SMAP protections are disabled if EFLAGS.AC=1
761
  if (BX_CPU_THIS_PTR cr4.get_SMAP() && ! BX_CPU_THIS_PTR get_AC() && rw != BX_EXECUTE && ! user) {
762
    if (combined_access & 0x4) // User page
763
      page_fault(ERROR_PROTECTION, laddr, user, rw);
764
  }
765
 
766
  if (BX_CPU_THIS_PTR cr4.get_PGE())
767
    combined_access |= (entry[leaf] & 0x100); // G
768
 
769
  // Update A/D bits if needed
770
  update_access_dirty_PAE(entry_addr, entry, BX_LEVEL_PML4, leaf, isWrite);
771
 
772
  return ppf | (laddr & offset_mask);
773
}
774
 
775
#endif
776
 
777
void BX_CPU_C::update_access_dirty_PAE(bx_phy_address *entry_addr, Bit64u *entry, unsigned max_level, unsigned leaf, unsigned write)
778
{
779
  // Update A bit if needed
780
  for (unsigned level=max_level; level > leaf; level--) {
781
    if (!(entry[level] & 0x20)) {
782
      entry[level] |= 0x20;
783
      access_write_physical(entry_addr[level], 8, &entry[level]);
784
      BX_NOTIFY_PHY_MEMORY_ACCESS(entry_addr[level], 8, BX_WRITE,
785
            (BX_PTE_ACCESS + level), (Bit8u*)(&entry[level]));
786
    }
787
  }
788
 
789
  // Update A/D bits if needed
790
  if (!(entry[leaf] & 0x20) || (write && !(entry[leaf] & 0x40))) {
791
    entry[leaf] |= (0x20 | (write<<6)); // Update A and possibly D bits
792
    access_write_physical(entry_addr[leaf], 8, &entry[leaf]);
793
    BX_NOTIFY_PHY_MEMORY_ACCESS(entry_addr[leaf], 8, BX_WRITE,
794
            (BX_PTE_ACCESS + leaf), (Bit8u*)(&entry[leaf]));
795
  }
796
}
797
 
798
//          Format of Legacy PAE PDPTR entry (PDPTE)
799
// -----------------------------------------------------------
800
// 00    | Present (P)
801
// 02-01 | Reserved (must be zero)
802
// 03    | Page-Level Write-Through (PWT) (486+), 0=reserved otherwise
803
// 04    | Page-Level Cache-Disable (PCD) (486+), 0=reserved otherwise
804
// 08-05 | Reserved (must be zero)
805
// 11-09 | (ignored)
806
// PA-12 | Physical address of 4-KByte aligned page directory
807
// 63-PA | Reserved (must be zero)
808
// -----------------------------------------------------------
809
 
810
#define PAGING_PAE_PDPTE_RESERVED_BITS \
811
    (BX_PAGING_PHY_ADDRESS_RESERVED_BITS | BX_CONST64(0xFFF00000000001E6))
812
 
813
bx_bool BX_CPP_AttrRegparmN(1) BX_CPU_C::CheckPDPTR(bx_phy_address cr3_val)
814
{
815
  // with Nested Paging PDPTRs are not loaded for guest page tables but
816
  // accessed on demand as part of the guest page walk
817
#if BX_SUPPORT_SVM
818
  if (BX_CPU_THIS_PTR in_svm_guest && SVM_NESTED_PAGING_ENABLED)
819
    return 1;
820
#endif
821
 
822
  cr3_val &= 0xffffffe0;
823
#if BX_SUPPORT_VMX >= 2
824
  if (BX_CPU_THIS_PTR in_vmx_guest) {
825
    if (SECONDARY_VMEXEC_CONTROL(VMX_VM_EXEC_CTRL3_EPT_ENABLE))
826
      cr3_val = translate_guest_physical(cr3_val, 0, 0, 1, BX_READ);
827
  }
828
#endif
829
 
830
  Bit64u pdptr[4];
831
  unsigned n;
832
 
833
  for (n=0; n<4; n++) {
834
    // read and check PDPTE entries
835
    bx_phy_address pdpe_entry_addr = (bx_phy_address) (cr3_val | (n << 3));
836
    access_read_physical(pdpe_entry_addr, 8, &(pdptr[n]));
837
    BX_NOTIFY_PHY_MEMORY_ACCESS(pdpe_entry_addr, 8, BX_READ, (BX_PDPTR0_ACCESS + n), (Bit8u*) &(pdptr[n]));
838
 
839
    if (pdptr[n] & 0x1) {
840
       if (pdptr[n] & PAGING_PAE_PDPTE_RESERVED_BITS) return 0;
841
    }
842
  }
843
 
844
  // load new PDPTRs
845
  for (n=0; n<4; n++)
846
    BX_CPU_THIS_PTR PDPTR_CACHE.entry[n] = pdptr[n];
847
 
848
  return 1; /* PDPTRs are fine */
849
}
850
 
851
#if BX_SUPPORT_VMX >= 2
852
bx_bool BX_CPP_AttrRegparmN(1) BX_CPU_C::CheckPDPTR(Bit64u *pdptr)
853
{
854
  for (unsigned n=0; n<4; n++) {
855
     if (pdptr[n] & 0x1) {
856
        if (pdptr[n] & PAGING_PAE_PDPTE_RESERVED_BITS) return 0;
857
     }
858
  }
859
 
860
  return 1; /* PDPTRs are fine */
861
}
862
#endif
863
 
864
bx_phy_address BX_CPU_C::translate_linear_load_PDPTR(bx_address laddr, unsigned user, unsigned rw)
865
{
866
  unsigned index = (laddr >> 30) & 0x3;
867
  Bit64u pdptr;
868
 
869
#if BX_SUPPORT_SVM
870
  if (BX_CPU_THIS_PTR in_svm_guest && SVM_NESTED_PAGING_ENABLED)
871
  {
872
    bx_phy_address cr3_val = BX_CPU_THIS_PTR cr3 & 0xffffffe0;
873
    cr3_val = nested_walk(cr3_val, BX_RW, 1);
874
 
875
    bx_phy_address pdpe_entry_addr = (bx_phy_address) (cr3_val | (index << 3));
876
    access_read_physical(pdpe_entry_addr, 8, &pdptr);
877
    BX_NOTIFY_PHY_MEMORY_ACCESS(pdpe_entry_addr, 8, BX_READ, (BX_PDPTR0_ACCESS + index), (Bit8u*) &pdptr);
878
 
879
    if (pdptr & 0x1) {
880
      if (pdptr & PAGING_PAE_PDPTE_RESERVED_BITS) {
881
        BX_DEBUG(("PAE PDPTE%d entry reserved bits set: 0x" FMT_ADDRX64, index, pdptr));
882
        page_fault(ERROR_RESERVED | ERROR_PROTECTION, laddr, user, rw);
883
      }
884
    }
885
  }
886
  else
887
#endif
888
  {
889
    pdptr = BX_CPU_THIS_PTR PDPTR_CACHE.entry[index];
890
  }
891
 
892
  if (! (pdptr & 0x1)) {
893
    BX_DEBUG(("PAE PDPTE entry not present !"));
894
    page_fault(ERROR_NOT_PRESENT, laddr, user, rw);
895
  }
896
 
897
  return pdptr;
898
}
899
 
900
// Translate a linear address to a physical address in PAE paging mode
901
bx_phy_address BX_CPU_C::translate_linear_PAE(bx_address laddr, Bit32u &lpf_mask, Bit32u &combined_access, unsigned user, unsigned rw)
902
{
903
  bx_phy_address entry_addr[2];
904
  Bit64u entry[2];
905
  bx_bool nx_fault = 0;
906
  int leaf;
907
 
908
  lpf_mask = 0xfff;
909
  combined_access = 0x06;
910
 
911
  Bit64u reserved = PAGING_LEGACY_PAE_RESERVED_BITS;
912
  if (! BX_CPU_THIS_PTR efer.get_NXE())
913
    reserved |= PAGE_DIRECTORY_NX_BIT;
914
 
915
  Bit64u pdpte = translate_linear_load_PDPTR(laddr, user, rw);
916
  bx_phy_address ppf = pdpte & BX_CONST64(0x000ffffffffff000);
917
 
918
  for (leaf = BX_LEVEL_PDE;; --leaf) {
919
    entry_addr[leaf] = ppf + ((laddr >> (9 + 9*leaf)) & 0xff8);
920
#if BX_SUPPORT_VMX >= 2
921
    if (BX_CPU_THIS_PTR in_vmx_guest) {
922
      if (SECONDARY_VMEXEC_CONTROL(VMX_VM_EXEC_CTRL3_EPT_ENABLE))
923
        entry_addr[leaf] = translate_guest_physical(entry_addr[leaf], laddr, 1, 1, BX_READ);
924
    }
925
#endif
926
#if BX_SUPPORT_SVM
927
    if (BX_CPU_THIS_PTR in_svm_guest && SVM_NESTED_PAGING_ENABLED) {
928
      entry_addr[leaf] = nested_walk(entry_addr[leaf], BX_RW, 1);
929
    }
930
#endif
931
    access_read_physical(entry_addr[leaf], 8, &entry[leaf]);
932
    BX_NOTIFY_PHY_MEMORY_ACCESS(entry_addr[leaf], 8, BX_READ, (BX_PTE_ACCESS + leaf), (Bit8u*)(&entry[leaf]));
933
 
934
    Bit64u curr_entry = entry[leaf];
935
    int fault = check_entry_PAE(bx_paging_level[leaf], curr_entry, reserved, rw, &nx_fault);
936
    if (fault >= 0)
937
      page_fault(fault, laddr, user, rw);
938
 
939
    combined_access &= curr_entry; // U/S and R/W
940
    ppf = curr_entry & BX_CONST64(0x000ffffffffff000);
941
 
942
    if (leaf == BX_LEVEL_PTE) break;
943
 
944
    // Ignore CR4.PSE in PAE mode
945
    if (curr_entry & 0x80) {
946
      if (curr_entry & PAGING_PAE_PDE2M_RESERVED_BITS) {
947
        BX_DEBUG(("PAE PDE2M: reserved bit is set PDE=0x" FMT_ADDRX64, curr_entry));
948
        page_fault(ERROR_RESERVED | ERROR_PROTECTION, laddr, user, rw);
949
      }
950
 
951
      // Make up the physical page frame address
952
      ppf = (bx_phy_address)(curr_entry & BX_CONST64(0x000fffffffe00000));
953
      lpf_mask = 0x1fffff;
954
      break;
955
    }
956
  }
957
 
958
  bx_bool isWrite = (rw & 1); // write or r-m-w
959
 
960
  unsigned priv_index = (BX_CPU_THIS_PTR cr0.get_WP() << 4) | // bit 4
961
                        (user<<3) |                           // bit 3
962
                        (combined_access | isWrite);          // bit 2,1,0
963
 
964
  if (!priv_check[priv_index] || nx_fault)
965
    page_fault(ERROR_PROTECTION, laddr, user, rw);
966
 
967
  if (BX_CPU_THIS_PTR cr4.get_SMEP() && rw == BX_EXECUTE && !user) {
968
    if (combined_access & 0x4) // User page
969
      page_fault(ERROR_PROTECTION, laddr, user, rw);
970
  }
971
 
972
  // SMAP protections are disabled if EFLAGS.AC=1
973
  if (BX_CPU_THIS_PTR cr4.get_SMAP() && ! BX_CPU_THIS_PTR get_AC() && rw != BX_EXECUTE && ! user) {
974
    if (combined_access & 0x4) // User page
975
      page_fault(ERROR_PROTECTION, laddr, user, rw);
976
  }
977
 
978
  if (BX_CPU_THIS_PTR cr4.get_PGE())
979
    combined_access |= (entry[leaf] & 0x100);     // G
980
 
981
  // Update A/D bits if needed
982
  update_access_dirty_PAE(entry_addr, entry, BX_LEVEL_PDE, leaf, isWrite);
983
 
984
  return ppf | (laddr & lpf_mask);
985
}
986
 
987
#endif
988
 
989
//           Format of a PDE that Maps a 4-MByte Page
990
// -----------------------------------------------------------
991
// 00    | Present (P)
992
// 01    | R/W
993
// 02    | U/S
994
// 03    | Page-Level Write-Through (PWT)
995
// 04    | Page-Level Cache-Disable (PCD)
996
// 05    | Accessed (A)
997
// 06    | Dirty (D)
998
// 07    | Page size, must be 1 to indicate 4-Mbyte page
999
// 08    | Global (G) (if CR4.PGE=1, ignored otherwise)
1000
// 11-09 | (ignored)
1001
// 12    | PAT (if PAT is supported, reserved otherwise)
1002
// PA-13 | Bits PA-32 of physical address of the 4-MByte page
1003
// 21-PA | Reserved (must be zero)
1004
// 31-22 | Bits 31-22 of physical address of the 4-MByte page
1005
// -----------------------------------------------------------
1006
 
1007
#define PAGING_PDE4M_RESERVED_BITS \
1008
    (((1 << (41-BX_PHY_ADDRESS_WIDTH))-1) << (13 + BX_PHY_ADDRESS_WIDTH - 32))
1009
 
1010
// Translate a linear address to a physical address in legacy paging mode
1011
bx_phy_address BX_CPU_C::translate_linear_legacy(bx_address laddr, Bit32u &lpf_mask, Bit32u &combined_access, unsigned user, unsigned rw)
1012
{
1013
  bx_phy_address entry_addr[2], ppf = (Bit32u) BX_CPU_THIS_PTR cr3 & BX_CR3_PAGING_MASK;
1014
  Bit32u entry[2];
1015
  int leaf;
1016
 
1017
  lpf_mask = 0xfff;
1018
  combined_access = 0x06;
1019
 
1020
  for (leaf = BX_LEVEL_PDE;; --leaf) {
1021
    entry_addr[leaf] = ppf + ((laddr >> (10 + 10*leaf)) & 0xffc);
1022
#if BX_SUPPORT_VMX >= 2
1023
    if (BX_CPU_THIS_PTR in_vmx_guest) {
1024
      if (SECONDARY_VMEXEC_CONTROL(VMX_VM_EXEC_CTRL3_EPT_ENABLE))
1025
        entry_addr[leaf] = translate_guest_physical(entry_addr[leaf], laddr, 1, 1, BX_READ);
1026
    }
1027
#endif
1028
#if BX_SUPPORT_SVM
1029
    if (BX_CPU_THIS_PTR in_svm_guest && SVM_NESTED_PAGING_ENABLED) {
1030
      entry_addr[leaf] = nested_walk(entry_addr[leaf], BX_RW, 1);
1031
    }
1032
#endif
1033
    access_read_physical(entry_addr[leaf], 4, &entry[leaf]);
1034
    BX_NOTIFY_PHY_MEMORY_ACCESS(entry_addr[leaf], 4, BX_READ, (BX_PTE_ACCESS + leaf), (Bit8u*)(&entry[leaf]));
1035
 
1036
    Bit32u curr_entry = entry[leaf];
1037
    if (!(curr_entry & 0x1)) {
1038
      BX_DEBUG(("%s: entry not present", bx_paging_level[leaf]));
1039
      page_fault(ERROR_NOT_PRESENT, laddr, user, rw);
1040
    }
1041
 
1042
    combined_access &= curr_entry; // U/S and R/W
1043
    ppf = curr_entry & 0xfffff000;
1044
 
1045
    if (leaf == BX_LEVEL_PTE) break;
1046
 
1047
#if BX_CPU_LEVEL >= 5
1048
    if ((curr_entry & 0x80) != 0 && BX_CPU_THIS_PTR cr4.get_PSE()) {
1049
      // 4M paging, only if CR4.PSE enabled, ignore PDE.PS otherwise
1050
      if (curr_entry & PAGING_PDE4M_RESERVED_BITS) {
1051
        BX_DEBUG(("PSE PDE4M: reserved bit is set: PDE=0x%08x", entry[BX_LEVEL_PDE]));
1052
        page_fault(ERROR_RESERVED | ERROR_PROTECTION, laddr, user, rw);
1053
      }
1054
 
1055
      // make up the physical frame number
1056
      ppf = (curr_entry & 0xffc00000);
1057
#if BX_PHY_ADDRESS_WIDTH > 32
1058
      ppf |= ((bx_phy_address)(curr_entry & 0x003fe000)) << 19;
1059
#endif
1060
      lpf_mask = 0x3fffff;
1061
      break;
1062
    }
1063
#endif
1064
  }
1065
 
1066
  bx_bool isWrite = (rw & 1); // write or r-m-w
1067
 
1068
  unsigned priv_index =
1069
#if BX_CPU_LEVEL >= 4
1070
      (BX_CPU_THIS_PTR cr0.get_WP() << 4) |   // bit 4
1071
#endif
1072
      (user<<3) |                             // bit 3
1073
      (combined_access | isWrite);            // bit 2,1,0
1074
 
1075
  if (!priv_check[priv_index])
1076
    page_fault(ERROR_PROTECTION, laddr, user, rw);
1077
 
1078
#if BX_CPU_LEVEL >= 6
1079
  if (BX_CPU_THIS_PTR cr4.get_SMEP() && rw == BX_EXECUTE && !user) {
1080
    if (combined_access & 0x4) // User page
1081
      page_fault(ERROR_PROTECTION, laddr, user, rw);
1082
  }
1083
 
1084
  // SMAP protections are disabled if EFLAGS.AC=1
1085
  if (BX_CPU_THIS_PTR cr4.get_SMAP() && ! BX_CPU_THIS_PTR get_AC() && rw != BX_EXECUTE && ! user) {
1086
    if (combined_access & 0x4) // User page
1087
      page_fault(ERROR_PROTECTION, laddr, user, rw);
1088
  }
1089
 
1090
  if (BX_CPU_THIS_PTR cr4.get_PGE())
1091
    combined_access |= (entry[leaf] & 0x100); // G
1092
#endif
1093
 
1094
  update_access_dirty(entry_addr, entry, leaf, isWrite);
1095
 
1096
  return ppf | (laddr & lpf_mask);
1097
}
1098
 
1099
void BX_CPU_C::update_access_dirty(bx_phy_address *entry_addr, Bit32u *entry, unsigned leaf, unsigned write)
1100
{
1101
  if (leaf == BX_LEVEL_PTE) {
1102
    // Update PDE A bit if needed
1103
    if (!(entry[BX_LEVEL_PDE] & 0x20)) {
1104
      entry[BX_LEVEL_PDE] |= 0x20;
1105
      access_write_physical(entry_addr[BX_LEVEL_PDE], 4, &entry[BX_LEVEL_PDE]);
1106
      BX_NOTIFY_PHY_MEMORY_ACCESS(entry_addr[BX_LEVEL_PDE], 4, BX_WRITE, BX_PDE_ACCESS, (Bit8u*)(&entry[BX_LEVEL_PDE]));
1107
    }
1108
  }
1109
 
1110
  // Update A/D bits if needed
1111
  if (!(entry[leaf] & 0x20) || (write && !(entry[leaf] & 0x40))) {
1112
    entry[leaf] |= (0x20 | (write<<6)); // Update A and possibly D bits
1113
    access_write_physical(entry_addr[leaf], 4, &entry[leaf]);
1114
    BX_NOTIFY_PHY_MEMORY_ACCESS(entry_addr[leaf], 4, BX_WRITE, (BX_PTE_ACCESS + leaf), (Bit8u*)(&entry[leaf]));
1115
  }
1116
}
1117
 
1118
// Translate a linear address to a physical address
1119
bx_phy_address BX_CPU_C::translate_linear(bx_TLB_entry *tlbEntry, bx_address laddr, unsigned user, unsigned rw)
1120
{
1121
  Bit32u combined_access = 0x06;
1122
  Bit32u lpf_mask = 0xfff; // 4K pages
1123
 
1124
#if BX_SUPPORT_X86_64
1125
  if (! long_mode()) laddr &= 0xffffffff;
1126
#endif
1127
 
1128
  bx_phy_address paddress, ppf, poffset = PAGE_OFFSET(laddr);
1129
  unsigned isWrite = rw & 1; // write or r-m-w
1130
  unsigned isExecute = (rw == BX_EXECUTE);
1131
 
1132
  InstrTLB_Increment(tlbLookups);
1133
  InstrTLB_Stats();
1134
 
1135
  bx_address lpf = LPFOf(laddr);
1136
 
1137
  // already looked up TLB for code access
1138
  if (! isExecute && TLB_LPFOf(tlbEntry->lpf) == lpf)
1139
  {
1140
    paddress = tlbEntry->ppf | poffset;
1141
 
1142
    if (tlbEntry->accessBits & (1 << (/*(isExecute<<2) |*/ (isWrite<<1) | user)))
1143
      return paddress;
1144
 
1145
    // The current access does not have permission according to the info
1146
    // in our TLB cache entry.  Re-walk the page tables, in case there is
1147
    // updated information in the memory image, and let the long path code
1148
    // generate an exception if one is warranted.
1149
  }
1150
 
1151
  InstrTLB_Increment(tlbMisses);
1152
 
1153
  if(BX_CPU_THIS_PTR cr0.get_PG())
1154
  {
1155
    BX_DEBUG(("page walk for address 0x" FMT_LIN_ADDRX, laddr));
1156
 
1157
#if BX_CPU_LEVEL >= 6
1158
#if BX_SUPPORT_X86_64
1159
    if (long_mode())
1160
      paddress = translate_linear_long_mode(laddr, lpf_mask, combined_access, user, rw);
1161
    else
1162
#endif
1163
      if (BX_CPU_THIS_PTR cr4.get_PAE())
1164
        paddress = translate_linear_PAE(laddr, lpf_mask, combined_access, user, rw);
1165
      else
1166
#endif 
1167
        paddress = translate_linear_legacy(laddr, lpf_mask, combined_access, user, rw);
1168
 
1169
#if BX_CPU_LEVEL >= 5
1170
    if (lpf_mask > 0xfff)
1171
      BX_CPU_THIS_PTR TLB.split_large = 1;
1172
#endif
1173
  }
1174
  else {
1175
    // no paging
1176
    paddress = (bx_phy_address) laddr;
1177
  }
1178
 
1179
  // Calculate physical memory address and fill in TLB cache entry
1180
#if BX_SUPPORT_VMX >= 2
1181
  if (BX_CPU_THIS_PTR in_vmx_guest) {
1182
    if (SECONDARY_VMEXEC_CONTROL(VMX_VM_EXEC_CTRL3_EPT_ENABLE)) {
1183
      paddress = translate_guest_physical(paddress, laddr, 1, 0, rw);
1184
    }
1185
  }
1186
#endif
1187
#if BX_SUPPORT_SVM
1188
  if (BX_CPU_THIS_PTR in_svm_guest && SVM_NESTED_PAGING_ENABLED) {
1189
    paddress = nested_walk(paddress, rw, 0);
1190
  }
1191
#endif
1192
  paddress = A20ADDR(paddress);
1193
  ppf = PPFOf(paddress);
1194
 
1195
  // direct memory access is NOT allowed by default
1196
  tlbEntry->lpf = lpf | TLB_NoHostPtr;
1197
  tlbEntry->lpf_mask = lpf_mask;
1198
  tlbEntry->ppf = ppf;
1199
  tlbEntry->accessBits = 0;
1200
 
1201
  tlbEntry->accessBits |= TLB_SysReadOK;
1202
  if (isWrite)
1203
    tlbEntry->accessBits |= TLB_SysWriteOK;
1204
  if (isExecute)
1205
    tlbEntry->accessBits |= TLB_SysExecuteOK;
1206
 
1207
  if (! BX_CPU_THIS_PTR cr0.get_PG()
1208
#if BX_SUPPORT_VMX >= 2
1209
        && ! (BX_CPU_THIS_PTR in_vmx_guest && SECONDARY_VMEXEC_CONTROL(VMX_VM_EXEC_CTRL3_EPT_ENABLE))
1210
#endif
1211
#if BX_SUPPORT_SVM
1212
        && ! (BX_CPU_THIS_PTR in_svm_guest && SVM_NESTED_PAGING_ENABLED)
1213
#endif
1214
    ) {
1215
    tlbEntry->accessBits |= TLB_UserReadOK |
1216
                            TLB_UserWriteOK |
1217
                            TLB_UserExecuteOK;
1218
  }
1219
  else {
1220
    if ((combined_access & 4) != 0) { // User Page
1221
 
1222
      if (user) {
1223
        tlbEntry->accessBits |= TLB_UserReadOK;
1224
        if (isWrite)
1225
          tlbEntry->accessBits |= TLB_UserWriteOK;
1226
        if (isExecute)
1227
          tlbEntry->accessBits |= TLB_UserExecuteOK;
1228
      }
1229
 
1230
#if BX_CPU_LEVEL >= 6
1231
      if (BX_CPU_THIS_PTR cr4.get_SMEP())
1232
        tlbEntry->accessBits &= ~TLB_SysExecuteOK;
1233
 
1234
      if (BX_CPU_THIS_PTR cr4.get_SMAP())
1235
        tlbEntry->accessBits &= ~(TLB_SysReadOK | TLB_SysWriteOK);
1236
#endif
1237
 
1238
    }
1239
  }
1240
 
1241
#if BX_CPU_LEVEL >= 6
1242
  if (combined_access & 0x100) // Global bit
1243
    tlbEntry->accessBits |= TLB_GlobalPage;
1244
#endif
1245
 
1246
  // Attempt to get a host pointer to this physical page. Put that
1247
  // pointer in the TLB cache. Note if the request is vetoed, NULL
1248
  // will be returned, and it's OK to OR zero in anyways.
1249
  tlbEntry->hostPageAddr = BX_CPU_THIS_PTR getHostMemAddr(ppf, rw);
1250
 
1251
  if (tlbEntry->hostPageAddr) {
1252
    // All access allowed also via direct pointer
1253
#if BX_X86_DEBUGGER
1254
    if (! hwbreakpoint_check(laddr, BX_HWDebugMemW, BX_HWDebugMemRW))
1255
#endif
1256
//AO modif start
1257
         tlbEntry->lpf = lpf | TLB_NoHostPtr;
1258
//       tlbEntry->lpf = lpf; // allow direct access with HostPtr
1259
//AO modif end
1260
  }
1261
  return paddress;
1262
}
1263
 
1264
#if BX_SUPPORT_SVM
1265
 
1266
void BX_CPU_C::nested_page_fault(unsigned fault, bx_phy_address guest_paddr, unsigned rw, unsigned is_page_walk)
1267
{
1268
  unsigned isWrite = rw & 1;
1269
 
1270
  Bit64u error_code = fault | (1 << 2) | (isWrite << 1);
1271
  if (rw == BX_EXECUTE)
1272
    error_code |= ERROR_CODE_ACCESS; // I/D = 1
1273
 
1274
  if (is_page_walk)
1275
    error_code |= BX_CONST64(1) << 32;
1276
  else
1277
    error_code |= BX_CONST64(1) << 33;
1278
 
1279
  Svm_Vmexit(SVM_VMEXIT_NPF, error_code, guest_paddr);
1280
}
1281
 
1282
bx_phy_address BX_CPU_C::nested_walk_long_mode(bx_phy_address guest_paddr, unsigned rw, bx_bool is_page_walk)
1283
{
1284
  bx_phy_address entry_addr[4];
1285
  Bit64u entry[4];
1286
  bx_bool nx_fault = 0;
1287
  int leaf;
1288
 
1289
  SVM_CONTROLS *ctrls = &BX_CPU_THIS_PTR vmcb.ctrls;
1290
  SVM_HOST_STATE *host_state = &BX_CPU_THIS_PTR vmcb.host_state;
1291
  bx_phy_address ppf = ctrls->ncr3 & BX_CR3_PAGING_MASK;
1292
  Bit64u offset_mask = BX_CONST64(0x0000ffffffffffff);
1293
  unsigned combined_access = 0x06;
1294
 
1295
  Bit64u reserved = PAGING_PAE_RESERVED_BITS;
1296
  if (! host_state->efer.get_NXE())
1297
    reserved |= PAGE_DIRECTORY_NX_BIT;
1298
 
1299
  for (leaf = BX_LEVEL_PML4;; --leaf) {
1300
    entry_addr[leaf] = ppf + ((guest_paddr >> (9 + 9*leaf)) & 0xff8);
1301
    access_read_physical(entry_addr[leaf], 8, &entry[leaf]);
1302
    BX_NOTIFY_PHY_MEMORY_ACCESS(entry_addr[leaf], 8, BX_READ, (BX_PTE_ACCESS + leaf), (Bit8u*)(&entry[leaf]));
1303
    offset_mask >>= 9;
1304
 
1305
    Bit64u curr_entry = entry[leaf];
1306
    int fault = check_entry_PAE(bx_paging_level[leaf], curr_entry, reserved, rw, &nx_fault);
1307
    if (fault >= 0)
1308
      nested_page_fault(fault, guest_paddr, rw, is_page_walk);
1309
 
1310
    combined_access &= curr_entry; // U/S and R/W
1311
    ppf = curr_entry & BX_CONST64(0x000ffffffffff000);
1312
 
1313
    if (leaf == BX_LEVEL_PTE) break;
1314
 
1315
    if (curr_entry & 0x80) {
1316
      if (leaf > (BX_LEVEL_PDE + !!bx_cpuid_support_1g_paging())) {
1317
        BX_DEBUG(("Nested PAE Walk %s: PS bit set !", bx_paging_level[leaf]));
1318
        nested_page_fault(ERROR_RESERVED | ERROR_PROTECTION, guest_paddr, rw, is_page_walk);
1319
      }
1320
 
1321
      ppf &= BX_CONST64(0x000fffffffffe000);
1322
      if (ppf & offset_mask) {
1323
        BX_DEBUG(("Nested PAE Walk %s: reserved bit is set: 0x" FMT_ADDRX64, bx_paging_level[leaf], curr_entry));
1324
        nested_page_fault(ERROR_RESERVED | ERROR_PROTECTION, guest_paddr, rw, is_page_walk);
1325
      }
1326
 
1327
      break;
1328
    }
1329
  }
1330
 
1331
  bx_bool isWrite = (rw & 1); // write or r-m-w
1332
 
1333
  unsigned priv_index = (1<<3) /* user */ | (combined_access | isWrite);
1334
 
1335
  if (!priv_check[priv_index] || nx_fault)
1336
    nested_page_fault(ERROR_PROTECTION, guest_paddr, rw, is_page_walk);
1337
 
1338
  // Update A/D bits if needed
1339
  update_access_dirty_PAE(entry_addr, entry, BX_LEVEL_PML4, leaf, isWrite);
1340
 
1341
  // Make up the physical page frame address
1342
  return ppf | (bx_phy_address)(guest_paddr & offset_mask);
1343
}
1344
 
1345
bx_phy_address BX_CPU_C::nested_walk_PAE(bx_phy_address guest_paddr, unsigned rw, bx_bool is_page_walk)
1346
{
1347
  bx_phy_address entry_addr[2];
1348
  Bit64u entry[2];
1349
  bx_bool nx_fault = 0;
1350
  int leaf;
1351
 
1352
  unsigned combined_access = 0x06;
1353
 
1354
  SVM_CONTROLS *ctrls = &BX_CPU_THIS_PTR vmcb.ctrls;
1355
  SVM_HOST_STATE *host_state = &BX_CPU_THIS_PTR vmcb.host_state;
1356
  bx_phy_address ncr3 = ctrls->ncr3 & 0xffffffe0;
1357
  unsigned index = (guest_paddr >> 30) & 0x3;
1358
  Bit64u pdptr;
1359
 
1360
  bx_phy_address pdpe_entry_addr = (bx_phy_address) (ncr3 | (index << 3));
1361
  access_read_physical(pdpe_entry_addr, 8, &pdptr);
1362
  BX_NOTIFY_PHY_MEMORY_ACCESS(pdpe_entry_addr, 8, BX_READ, (BX_PDPTR0_ACCESS + index), (Bit8u*) &pdptr);
1363
 
1364
  if (! (pdptr & 0x1)) {
1365
    BX_DEBUG(("Nested PAE Walk PDPTE%d entry not present !", index));
1366
    nested_page_fault(ERROR_NOT_PRESENT, guest_paddr, rw, is_page_walk);
1367
  }
1368
 
1369
  if (pdptr & PAGING_PAE_PDPTE_RESERVED_BITS) {
1370
    BX_DEBUG(("Nested PAE Walk PDPTE%d entry reserved bits set: 0x" FMT_ADDRX64, index, pdptr));
1371
    nested_page_fault(ERROR_RESERVED | ERROR_PROTECTION, guest_paddr, rw, is_page_walk);
1372
  }
1373
 
1374
  Bit64u reserved = PAGING_LEGACY_PAE_RESERVED_BITS;
1375
  if (! host_state->efer.get_NXE())
1376
    reserved |= PAGE_DIRECTORY_NX_BIT;
1377
 
1378
  bx_phy_address ppf = pdptr & BX_CONST64(0x000ffffffffff000);
1379
 
1380
  for (leaf = BX_LEVEL_PDE;; --leaf) {
1381
    entry_addr[leaf] = ppf + ((guest_paddr >> (9 + 9*leaf)) & 0xff8);
1382
    access_read_physical(entry_addr[leaf], 8, &entry[leaf]);
1383
    BX_NOTIFY_PHY_MEMORY_ACCESS(entry_addr[leaf], 8, BX_READ, (BX_PTE_ACCESS + leaf), (Bit8u*)(&entry[leaf]));
1384
 
1385
    Bit64u curr_entry = entry[leaf];
1386
    int fault = check_entry_PAE(bx_paging_level[leaf], curr_entry, reserved, rw, &nx_fault);
1387
    if (fault >= 0)
1388
      nested_page_fault(fault, guest_paddr, rw, is_page_walk);
1389
 
1390
    combined_access &= curr_entry; // U/S and R/W
1391
    ppf = curr_entry & BX_CONST64(0x000ffffffffff000);
1392
 
1393
    if (leaf == BX_LEVEL_PTE) break;
1394
 
1395
    // Ignore CR4.PSE in PAE mode
1396
    if (curr_entry & 0x80) {
1397
      if (curr_entry & PAGING_PAE_PDE2M_RESERVED_BITS) {
1398
        BX_DEBUG(("PAE PDE2M: reserved bit is set PDE=0x" FMT_ADDRX64, curr_entry));
1399
        nested_page_fault(ERROR_RESERVED | ERROR_PROTECTION, guest_paddr, rw, is_page_walk);
1400
      }
1401
 
1402
      // Make up the physical page frame address
1403
      ppf = (bx_phy_address)((curr_entry & BX_CONST64(0x000fffffffe00000)) | (guest_paddr & 0x001ff000));
1404
      break;
1405
    }
1406
  }
1407
 
1408
  bx_bool isWrite = (rw & 1); // write or r-m-w
1409
 
1410
  unsigned priv_index = (1<<3) /* user */ | (combined_access | isWrite);
1411
 
1412
  if (!priv_check[priv_index] || nx_fault)
1413
    nested_page_fault(ERROR_PROTECTION, guest_paddr, rw, is_page_walk);
1414
 
1415
  // Update A/D bits if needed
1416
  update_access_dirty_PAE(entry_addr, entry, BX_LEVEL_PDE, leaf, isWrite);
1417
 
1418
  Bit32u page_offset = PAGE_OFFSET(guest_paddr);
1419
  return ppf | page_offset;
1420
}
1421
 
1422
bx_phy_address BX_CPU_C::nested_walk_legacy(bx_phy_address guest_paddr, unsigned rw, bx_bool is_page_walk)
1423
{
1424
  bx_phy_address entry_addr[2];
1425
  Bit32u entry[2];
1426
  int leaf;
1427
 
1428
  SVM_CONTROLS *ctrls = &BX_CPU_THIS_PTR vmcb.ctrls;
1429
  SVM_HOST_STATE *host_state = &BX_CPU_THIS_PTR vmcb.host_state;
1430
  bx_phy_address ppf = ctrls->ncr3 & BX_CR3_PAGING_MASK;
1431
  unsigned combined_access = 0x06;
1432
 
1433
  for (leaf = BX_LEVEL_PDE;; --leaf) {
1434
    entry_addr[leaf] = ppf + ((guest_paddr >> (10 + 10*leaf)) & 0xffc);
1435
    access_read_physical(entry_addr[leaf], 4, &entry[leaf]);
1436
    BX_NOTIFY_PHY_MEMORY_ACCESS(entry_addr[leaf], 4, BX_READ, (BX_PTE_ACCESS + leaf), (Bit8u*)(&entry[leaf]));
1437
 
1438
    Bit32u curr_entry = entry[leaf];
1439
    if (!(curr_entry & 0x1)) {
1440
      BX_DEBUG(("Nested %s Walk: entry not present", bx_paging_level[leaf]));
1441
      nested_page_fault(ERROR_NOT_PRESENT, guest_paddr, rw, is_page_walk);
1442
    }
1443
 
1444
    combined_access &= curr_entry; // U/S and R/W
1445
    ppf = curr_entry & 0xfffff000;
1446
 
1447
    if (leaf == BX_LEVEL_PTE) break;
1448
 
1449
    if ((curr_entry & 0x80) != 0 && host_state->cr4.get_PSE()) {
1450
      // 4M paging, only if CR4.PSE enabled, ignore PDE.PS otherwise
1451
      if (curr_entry & PAGING_PDE4M_RESERVED_BITS) {
1452
        BX_DEBUG(("Nested PSE Walk PDE4M: reserved bit is set: PDE=0x%08x", entry[BX_LEVEL_PDE]));
1453
        nested_page_fault(ERROR_RESERVED | ERROR_PROTECTION, guest_paddr, rw, is_page_walk);
1454
      }
1455
 
1456
      // make up the physical frame number
1457
      ppf = (curr_entry & 0xffc00000) | (guest_paddr & 0x003ff000);
1458
#if BX_PHY_ADDRESS_WIDTH > 32
1459
      ppf |= ((bx_phy_address)(curr_entry & 0x003fe000)) << 19;
1460
#endif
1461
      break;
1462
    }
1463
  }
1464
 
1465
  bx_bool isWrite = (rw & 1); // write or r-m-w
1466
 
1467
  unsigned priv_index = (1<<3) /* user */ | (combined_access | isWrite);
1468
 
1469
  if (!priv_check[priv_index])
1470
    nested_page_fault(ERROR_PROTECTION, guest_paddr, rw, is_page_walk);
1471
 
1472
  update_access_dirty(entry_addr, entry, leaf, isWrite);
1473
 
1474
  Bit32u page_offset = PAGE_OFFSET(guest_paddr);
1475
  return ppf | page_offset;
1476
}
1477
 
1478
bx_phy_address BX_CPU_C::nested_walk(bx_phy_address guest_paddr, unsigned rw, bx_bool is_page_walk)
1479
{
1480
  SVM_HOST_STATE *host_state = &BX_CPU_THIS_PTR vmcb.host_state;
1481
 
1482
  BX_DEBUG(("Nested walk for guest paddr 0x" FMT_PHY_ADDRX, guest_paddr));
1483
 
1484
  if (host_state->efer.get_LMA())
1485
    return nested_walk_long_mode(guest_paddr, rw, is_page_walk);
1486
  else if (host_state->cr4.get_PAE())
1487
    return nested_walk_PAE(guest_paddr, rw, is_page_walk);
1488
  else
1489
    return nested_walk_legacy(guest_paddr, rw, is_page_walk);
1490
}
1491
 
1492
#endif
1493
 
1494
#if BX_SUPPORT_VMX >= 2
1495
 
1496
/* EPT access type */
1497
#define BX_EPT_READ    0x01
1498
#define BX_EPT_WRITE   0x02
1499
#define BX_EPT_EXECUTE 0x04
1500
 
1501
/* EPT access mask */
1502
#define BX_EPT_ENTRY_NOT_PRESENT        0x00
1503
#define BX_EPT_ENTRY_READ_ONLY          0x01
1504
#define BX_EPT_ENTRY_WRITE_ONLY         0x02
1505
#define BX_EPT_ENTRY_READ_WRITE         0x03
1506
#define BX_EPT_ENTRY_EXECUTE_ONLY       0x04
1507
#define BX_EPT_ENTRY_READ_EXECUTE       0x05
1508
#define BX_EPT_ENTRY_WRITE_EXECUTE      0x06
1509
#define BX_EPT_ENTRY_READ_WRITE_EXECUTE 0x07
1510
 
1511
#define BX_SUPPRESS_EPT_VIOLATION_EXCEPTION BX_CONST64(0x8000000000000000)
1512
 
1513
//                   Format of a EPT Entry
1514
// -----------------------------------------------------------
1515
// 00    | Read access
1516
// 01    | Write access
1517
// 02    | Execute Access
1518
// 05-03 | EPT Memory type (for leaf entries, reserved otherwise)
1519
// 06    | Ignore PAT memory type (for leaf entries, reserved otherwise)
1520
// 07    | Page Size, must be 1 to indicate a Large Page
1521
// 11-08 | (ignored)
1522
// PA-12 | Physical address
1523
// 51-PA | Reserved (must be zero)
1524
// 63-52 | (ignored)
1525
// -----------------------------------------------------------
1526
 
1527
#define PAGING_EPT_RESERVED_BITS (BX_PAGING_PHY_ADDRESS_RESERVED_BITS)
1528
 
1529
bx_phy_address BX_CPU_C::translate_guest_physical(bx_phy_address guest_paddr, bx_address guest_laddr, bx_bool guest_laddr_valid, bx_bool is_page_walk, unsigned rw)
1530
{
1531
  VMCS_CACHE *vm = &BX_CPU_THIS_PTR vmcs;
1532
  bx_phy_address entry_addr[4], ppf = LPFOf(vm->eptptr);
1533
  Bit64u entry[4];
1534
  int leaf;
1535
 
1536
  Bit32u combined_access = 0x7, access_mask = 0;
1537
  Bit64u offset_mask = BX_CONST64(0x0000ffffffffffff);
1538
 
1539
  BX_DEBUG(("EPT walk for guest paddr 0x" FMT_PHY_ADDRX, guest_paddr));
1540
 
1541
  // when EPT A/D enabled treat guest page table accesses as writes
1542
  if (BX_VMX_EPT_ACCESS_DIRTY_ENABLED && is_page_walk && guest_laddr_valid)
1543
    rw = BX_WRITE;
1544
 
1545
  if (rw == BX_EXECUTE) access_mask |= BX_EPT_EXECUTE;
1546
  if (rw & 1) access_mask |= BX_EPT_WRITE; // write or r-m-w
1547
  if (rw == BX_READ) access_mask |= BX_EPT_READ;
1548
 
1549
  Bit32u vmexit_reason = 0;
1550
 
1551
  for (leaf = BX_LEVEL_PML4;; --leaf) {
1552
    entry_addr[leaf] = ppf + ((guest_paddr >> (9 + 9*leaf)) & 0xff8);
1553
    access_read_physical(entry_addr[leaf], 8, &entry[leaf]);
1554
    BX_NOTIFY_PHY_MEMORY_ACCESS(entry_addr[leaf], 8, BX_READ, (BX_EPT_PTE_ACCESS + leaf), (Bit8u*)(&entry[leaf]));
1555
 
1556
    offset_mask >>= 9;
1557
    Bit64u curr_entry = entry[leaf];
1558
    Bit32u curr_access_mask = curr_entry & 0x7;
1559
 
1560
    combined_access &= curr_access_mask;
1561
 
1562
    if (curr_access_mask == BX_EPT_ENTRY_NOT_PRESENT) {
1563
      BX_DEBUG(("EPT %s: not present", bx_paging_level[leaf]));
1564
      vmexit_reason = VMX_VMEXIT_EPT_VIOLATION;
1565
      break;
1566
    }
1567
 
1568
    if (curr_access_mask == BX_EPT_ENTRY_WRITE_ONLY || curr_access_mask == BX_EPT_ENTRY_WRITE_EXECUTE) {
1569
      BX_DEBUG(("EPT %s: EPT misconfiguration mask=%d", bx_paging_level[leaf], curr_access_mask));
1570
      vmexit_reason = VMX_VMEXIT_EPT_MISCONFIGURATION;
1571
      break;
1572
    }
1573
 
1574
    extern bx_bool isMemTypeValidMTRR(unsigned memtype);
1575
    if (! isMemTypeValidMTRR((curr_entry >> 3) & 7)) {
1576
      BX_DEBUG(("EPT %s: EPT misconfiguration memtype=%d",
1577
        bx_paging_level[leaf], (unsigned)((curr_entry >> 3) & 7)));
1578
      vmexit_reason = VMX_VMEXIT_EPT_MISCONFIGURATION;
1579
      break;
1580
    }
1581
 
1582
    if (curr_entry & PAGING_EPT_RESERVED_BITS) {
1583
      BX_DEBUG(("EPT %s: reserved bit is set 0x" FMT_ADDRX64, bx_paging_level[leaf], curr_entry));
1584
      vmexit_reason = VMX_VMEXIT_EPT_MISCONFIGURATION;
1585
      break;
1586
    }
1587
 
1588
    ppf = curr_entry & BX_CONST64(0x000ffffffffff000);
1589
 
1590
    if (leaf == BX_LEVEL_PTE) break;
1591
 
1592
    if (curr_entry & 0x80) {
1593
      if (leaf > (BX_LEVEL_PDE + !!bx_cpuid_support_1g_paging())) {
1594
        BX_DEBUG(("EPT %s: PS bit set !", bx_paging_level[leaf]));
1595
        vmexit_reason = VMX_VMEXIT_EPT_MISCONFIGURATION;
1596
        break;
1597
      }
1598
 
1599
      ppf &= BX_CONST64(0x000fffffffffe000);
1600
      if (ppf & offset_mask) {
1601
         BX_DEBUG(("EPT %s: reserved bit is set: 0x" FMT_ADDRX64, bx_paging_level[leaf], curr_entry));
1602
         vmexit_reason = VMX_VMEXIT_EPT_MISCONFIGURATION;
1603
         break;
1604
      }
1605
 
1606
      // Make up the physical page frame address
1607
      ppf += (bx_phy_address)(guest_paddr & offset_mask);
1608
      break;
1609
    }
1610
  }
1611
 
1612
  if (!vmexit_reason && (access_mask & combined_access) != access_mask) {
1613
    vmexit_reason = VMX_VMEXIT_EPT_VIOLATION;
1614
  }
1615
 
1616
  if (vmexit_reason) {
1617
    BX_ERROR(("VMEXIT: EPT %s for guest paddr 0x" FMT_PHY_ADDRX " laddr 0x" FMT_ADDRX,
1618
       (vmexit_reason == VMX_VMEXIT_EPT_VIOLATION) ? "violation" : "misconfig", guest_paddr, guest_laddr));
1619
 
1620
    Bit32u vmexit_qualification = 0;
1621
 
1622
    if (vmexit_reason == VMX_VMEXIT_EPT_VIOLATION) {
1623
      // no VMExit qualification for EPT Misconfiguration VMExit
1624
      vmexit_qualification = access_mask | (combined_access << 3);
1625
      if (guest_laddr_valid) {
1626
        vmexit_qualification |= (1<<7);
1627
        if (! is_page_walk) vmexit_qualification |= (1<<8);
1628
      }
1629
      if (BX_CPU_THIS_PTR nmi_unblocking_iret)
1630
        vmexit_qualification |= (1 << 12);
1631
 
1632
      if (SECONDARY_VMEXEC_CONTROL(VMX_VM_EXEC_CTRL3_EPT_VIOLATION_EXCEPTION)) {
1633
        if ((entry[leaf] & BX_SUPPRESS_EPT_VIOLATION_EXCEPTION) == 0)
1634
          Virtualization_Exception(vmexit_qualification, guest_paddr, guest_laddr);
1635
      }
1636
    }
1637
 
1638
    VMwrite64(VMCS_64BIT_GUEST_PHYSICAL_ADDR, guest_paddr);
1639
    VMwrite_natural(VMCS_GUEST_LINEAR_ADDR, guest_laddr);
1640
    VMexit(vmexit_reason, vmexit_qualification);
1641
  }
1642
 
1643
  if (BX_VMX_EPT_ACCESS_DIRTY_ENABLED) {
1644
    update_ept_access_dirty(entry_addr, entry, leaf, rw & 1);
1645
  }
1646
 
1647
  Bit32u page_offset = PAGE_OFFSET(guest_paddr);
1648
  return ppf | page_offset;
1649
}
1650
 
1651
// Access bit 8, Dirty bit 9
1652
void BX_CPU_C::update_ept_access_dirty(bx_phy_address *entry_addr, Bit64u *entry, unsigned leaf, unsigned write)
1653
{
1654
  // Update A bit if needed
1655
  for (unsigned level=BX_LEVEL_PML4; level > leaf; level--) {
1656
    if (!(entry[level] & 0x100)) {
1657
      entry[level] |= 0x100;
1658
      access_write_physical(entry_addr[level], 8, &entry[level]);
1659
      BX_NOTIFY_PHY_MEMORY_ACCESS(entry_addr[level], 8, BX_WRITE, (BX_EPT_PTE_ACCESS + level), (Bit8u*)(&entry[level]));
1660
    }
1661
  }
1662
 
1663
  // Update A/D bits if needed
1664
  if (!(entry[leaf] & 0x100) || (write && !(entry[leaf] & 0x200))) {
1665
    entry[leaf] |= (0x100 | (write<<9)); // Update A and possibly D bits
1666
    access_write_physical(entry_addr[leaf], 8, &entry[leaf]);
1667
    BX_NOTIFY_PHY_MEMORY_ACCESS(entry_addr[leaf], 8, BX_WRITE, (BX_EPT_PTE_ACCESS + leaf), (Bit8u*)(&entry[leaf]));
1668
  }
1669
}
1670
 
1671
#endif
1672
 
1673
#if BX_DEBUGGER || BX_DISASM || BX_INSTRUMENTATION || BX_GDBSTUB
1674
 
1675
#if BX_DEBUGGER
1676
 
1677
void dbg_print_paging_pte(int level, Bit64u entry)
1678
{
1679
  dbg_printf("%4s: 0x%08x%08x", bx_paging_level[level], GET32H(entry), GET32L(entry));
1680
 
1681
  if (entry & BX_CONST64(0x8000000000000000))
1682
    dbg_printf(" XD");
1683
  else
1684
    dbg_printf("   ");
1685
 
1686
  if (level == BX_LEVEL_PTE) {
1687
    dbg_printf("    %s %s %s",
1688
      (entry & 0x0100) ? "G" : "g",
1689
      (entry & 0x0080) ? "PAT" : "pat",
1690
      (entry & 0x0040) ? "D" : "d");
1691
  }
1692
  else {
1693
    if (entry & 0x80) {
1694
      dbg_printf(" PS %s %s %s",
1695
        (entry & 0x0100) ? "G" : "g",
1696
        (entry & 0x1000) ? "PAT" : "pat",
1697
        (entry & 0x0040) ? "D" : "d");
1698
    }
1699
    else {
1700
      dbg_printf(" ps        ");
1701
    }
1702
  }
1703
 
1704
  dbg_printf(" %s %s %s %s %s %s\n",
1705
    (entry & 0x20) ? "A" : "a",
1706
    (entry & 0x10) ? "PCD" : "pcd",
1707
    (entry & 0x08) ? "PWT" : "pwt",
1708
    (entry & 0x04) ? "U" : "S",
1709
    (entry & 0x02) ? "W" : "R",
1710
    (entry & 0x01) ? "P" : "p");
1711
}
1712
 
1713
#if BX_SUPPORT_VMX >= 2
1714
void dbg_print_ept_paging_pte(int level, Bit64u entry)
1715
{
1716
  dbg_printf("EPT %4s: 0x%08x%08x", bx_paging_level[level], GET32H(entry), GET32L(entry));
1717
 
1718
  if (level != BX_LEVEL_PTE && (entry & 0x80))
1719
    dbg_printf(" PS");
1720
  else
1721
    dbg_printf("   ");
1722
 
1723
  dbg_printf(" %s %s %s\n",
1724
    (entry & 0x04) ? "E" : "e",
1725
    (entry & 0x02) ? "W" : "w",
1726
    (entry & 0x01) ? "R" : "r");
1727
}
1728
#endif
1729
 
1730
#endif // BX_DEBUGGER
1731
 
1732
#if BX_SUPPORT_VMX >= 2
1733
bx_bool BX_CPU_C::dbg_translate_guest_physical(bx_phy_address guest_paddr, bx_phy_address *phy, bx_bool verbose)
1734
{
1735
  VMCS_CACHE *vm = &BX_CPU_THIS_PTR vmcs;
1736
  bx_phy_address pt_address = LPFOf(vm->eptptr);
1737
  Bit64u offset_mask = BX_CONST64(0x0000ffffffffffff);
1738
 
1739
  for (int level = 3; level >= 0; --level) {
1740
    Bit64u pte;
1741
    pt_address += ((guest_paddr >> (9 + 9*level)) & 0xff8);
1742
    offset_mask >>= 9;
1743
    BX_MEM(0)->readPhysicalPage(BX_CPU_THIS, pt_address, 8, &pte);
1744
#if BX_DEBUGGER
1745
    if (verbose)
1746
      dbg_print_ept_paging_pte(level, pte);
1747
#endif
1748
    switch(pte & 7) {
1749
    case BX_EPT_ENTRY_NOT_PRESENT:
1750
    case BX_EPT_ENTRY_WRITE_ONLY:
1751
    case BX_EPT_ENTRY_WRITE_EXECUTE:
1752
      return 0;
1753
    }
1754
    if (pte & BX_PAGING_PHY_ADDRESS_RESERVED_BITS)
1755
      return 0;
1756
 
1757
    pt_address = bx_phy_address(pte & BX_CONST64(0x000ffffffffff000));
1758
 
1759
    if (level == BX_LEVEL_PTE) break;
1760
 
1761
    if (pte & 0x80) {
1762
       if (level > (BX_LEVEL_PDE + !!bx_cpuid_support_1g_paging()))
1763
         return 0;
1764
 
1765
        pt_address &= BX_CONST64(0x000fffffffffe000);
1766
        if (pt_address & offset_mask) return 0;
1767
        break;
1768
      }
1769
  }
1770
 
1771
  *phy = pt_address + (bx_phy_address)(guest_paddr & offset_mask);
1772
  return 1;
1773
}
1774
#endif
1775
 
1776
bx_bool BX_CPU_C::dbg_xlate_linear2phy(bx_address laddr, bx_phy_address *phy, bx_bool verbose)
1777
{
1778
  bx_phy_address paddress;
1779
 
1780
#if BX_SUPPORT_X86_64
1781
  if (! long_mode()) laddr &= 0xffffffff;
1782
#endif
1783
 
1784
  if (! BX_CPU_THIS_PTR cr0.get_PG()) {
1785
    paddress = (bx_phy_address) laddr;
1786
  }
1787
  else {
1788
    bx_phy_address pt_address = BX_CPU_THIS_PTR cr3 & BX_CR3_PAGING_MASK;
1789
 
1790
    // see if page is in the TLB first
1791
    if (! verbose) {
1792
      bx_address lpf = LPFOf(laddr);
1793
      unsigned TLB_index = BX_TLB_INDEX_OF(lpf, 0);
1794
      bx_TLB_entry *tlbEntry  = &BX_CPU_THIS_PTR TLB.entry[TLB_index];
1795
 
1796
      if (TLB_LPFOf(tlbEntry->lpf) == lpf) {
1797
        paddress = tlbEntry->ppf | PAGE_OFFSET(laddr);
1798
        *phy = paddress;
1799
        return 1;
1800
      }
1801
    }
1802
 
1803
#if BX_CPU_LEVEL >= 6
1804
    if (BX_CPU_THIS_PTR cr4.get_PAE()) {
1805
      Bit64u offset_mask = BX_CONST64(0x0000ffffffffffff);
1806
 
1807
      int level = 3;
1808
      if (! long_mode()) {
1809
        pt_address = BX_CPU_THIS_PTR PDPTR_CACHE.entry[(laddr >> 30) & 3];
1810
        if (! (pt_address & 0x1))
1811
           goto page_fault;
1812
        pt_address &= BX_CONST64(0x000ffffffffff000);
1813
        offset_mask >>= 18;
1814
        level = 1;
1815
      }
1816
 
1817
      for (; level >= 0; --level) {
1818
        Bit64u pte;
1819
        pt_address += ((laddr >> (9 + 9*level)) & 0xff8);
1820
        offset_mask >>= 9;
1821
#if BX_SUPPORT_VMX >= 2
1822
        if (BX_CPU_THIS_PTR in_vmx_guest) {
1823
          if (SECONDARY_VMEXEC_CONTROL(VMX_VM_EXEC_CTRL3_EPT_ENABLE)) {
1824
            if (! dbg_translate_guest_physical(pt_address, &pt_address, verbose))
1825
              goto page_fault;
1826
          }
1827
        }
1828
#endif
1829
        BX_MEM(0)->readPhysicalPage(BX_CPU_THIS, pt_address, 8, &pte);
1830
#if BX_DEBUGGER
1831
        if (verbose)
1832
          dbg_print_paging_pte(level, pte);
1833
#endif
1834
        if(!(pte & 1))
1835
          goto page_fault;
1836
        if (pte & BX_PAGING_PHY_ADDRESS_RESERVED_BITS)
1837
          goto page_fault;
1838
        pt_address = bx_phy_address(pte & BX_CONST64(0x000ffffffffff000));
1839
        if (level == BX_LEVEL_PTE) break;
1840
        if (pte & 0x80) {
1841
          // large page
1842
          pt_address &= BX_CONST64(0x000fffffffffe000);
1843
          if (pt_address & offset_mask)
1844
            goto page_fault;
1845
          if (bx_cpuid_support_1g_paging() && level == BX_LEVEL_PDPTE) break;
1846
          if (level == BX_LEVEL_PDE) break;
1847
          goto page_fault;
1848
        }
1849
      }
1850
      paddress = pt_address + (bx_phy_address)(laddr & offset_mask);
1851
    }
1852
    else   // not PAE
1853
#endif
1854
    {
1855
      Bit32u offset_mask = 0xfff;
1856
      for (int level = 1; level >= 0; --level) {
1857
        Bit32u pte;
1858
        pt_address += ((laddr >> (10 + 10*level)) & 0xffc);
1859
#if BX_SUPPORT_VMX >= 2
1860
        if (BX_CPU_THIS_PTR in_vmx_guest) {
1861
          if (SECONDARY_VMEXEC_CONTROL(VMX_VM_EXEC_CTRL3_EPT_ENABLE)) {
1862
            if (! dbg_translate_guest_physical(pt_address, &pt_address, verbose))
1863
              goto page_fault;
1864
          }
1865
        }
1866
#endif
1867
        BX_MEM(0)->readPhysicalPage(BX_CPU_THIS, pt_address, 4, &pte);
1868
#if BX_DEBUGGER
1869
        if (verbose)
1870
          dbg_print_paging_pte(level, pte);
1871
#endif
1872
        if (!(pte & 1))
1873
          goto page_fault;
1874
        pt_address = pte & 0xfffff000;
1875
#if BX_CPU_LEVEL >= 6
1876
        if (level == BX_LEVEL_PDE && (pte & 0x80) != 0 && BX_CPU_THIS_PTR cr4.get_PSE()) {
1877
          offset_mask = 0x3fffff;
1878
          pt_address = pte & 0xffc00000;
1879
#if BX_PHY_ADDRESS_WIDTH > 32
1880
          pt_address += ((bx_phy_address)(pte & 0x003fe000)) << 19;
1881
#endif
1882
          break;
1883
        }
1884
#endif
1885
      }
1886
      paddress = pt_address + (bx_phy_address)(laddr & offset_mask);
1887
    }
1888
  }
1889
#if BX_SUPPORT_VMX >= 2
1890
  if (BX_CPU_THIS_PTR in_vmx_guest) {
1891
    if (SECONDARY_VMEXEC_CONTROL(VMX_VM_EXEC_CTRL3_EPT_ENABLE)) {
1892
      if (! dbg_translate_guest_physical(paddress, &paddress, verbose))
1893
        goto page_fault;
1894
    }
1895
  }
1896
#endif
1897
 
1898
  *phy = A20ADDR(paddress);
1899
  return 1;
1900
 
1901
page_fault:
1902
  *phy = 0;
1903
  return 0;
1904
}
1905
#endif
1906
 
1907
void BX_CPU_C::access_write_linear(bx_address laddr, unsigned len, unsigned curr_pl, void *data)
1908
{
1909
  Bit32u pageOffset = PAGE_OFFSET(laddr);
1910
 
1911
  bx_TLB_entry *tlbEntry = BX_TLB_ENTRY_OF(laddr);
1912
 
1913
  /* check for reference across multiple pages */
1914
  if ((pageOffset + len) <= 4096) {
1915
    // Access within single page.
1916
    BX_CPU_THIS_PTR address_xlation.paddress1 = translate_linear(tlbEntry, laddr, (curr_pl==3), BX_WRITE);
1917
    BX_CPU_THIS_PTR address_xlation.pages     = 1;
1918
 
1919
//AO    BX_NOTIFY_LIN_MEMORY_ACCESS(laddr, BX_CPU_THIS_PTR address_xlation.paddress1,
1920
//AO                          len, curr_pl, BX_WRITE, (Bit8u*) data);
1921
 
1922
    access_write_physical(BX_CPU_THIS_PTR address_xlation.paddress1, len, data);
1923
 
1924
#if BX_X86_DEBUGGER
1925
    hwbreakpoint_match(laddr, len, BX_WRITE);
1926
#endif
1927
  }
1928
  else {
1929
    // access across 2 pages
1930
    BX_CPU_THIS_PTR address_xlation.paddress1 = translate_linear(tlbEntry, laddr, (curr_pl == 3), BX_WRITE);
1931
    BX_CPU_THIS_PTR address_xlation.len1 = 4096 - pageOffset;
1932
    BX_CPU_THIS_PTR address_xlation.len2 = len - BX_CPU_THIS_PTR address_xlation.len1;
1933
    BX_CPU_THIS_PTR address_xlation.pages = 2;
1934
    bx_address laddr2 = laddr + BX_CPU_THIS_PTR address_xlation.len1;
1935
#if BX_SUPPORT_X86_64
1936
    if (! long64_mode()) laddr2 &= 0xffffffff; /* handle linear address wrap in legacy mode */
1937
#endif
1938
    BX_CPU_THIS_PTR address_xlation.paddress2 = translate_linear(BX_TLB_ENTRY_OF(laddr2), laddr2, (curr_pl == 3), BX_WRITE);
1939
 
1940
#ifdef BX_LITTLE_ENDIAN
1941
//AO    BX_NOTIFY_LIN_MEMORY_ACCESS(laddr, BX_CPU_THIS_PTR address_xlation.paddress1,
1942
//AO        BX_CPU_THIS_PTR address_xlation.len1, curr_pl, 
1943
//AO        BX_WRITE, (Bit8u*) data);
1944
    access_write_physical(BX_CPU_THIS_PTR address_xlation.paddress1,
1945
        BX_CPU_THIS_PTR address_xlation.len1, data);
1946
//AO    BX_NOTIFY_LIN_MEMORY_ACCESS(laddr2, BX_CPU_THIS_PTR address_xlation.paddress2,
1947
//AO        BX_CPU_THIS_PTR address_xlation.len2, curr_pl, 
1948
//AO        BX_WRITE, ((Bit8u*)data) + BX_CPU_THIS_PTR address_xlation.len1);
1949
    access_write_physical(BX_CPU_THIS_PTR address_xlation.paddress2,
1950
        BX_CPU_THIS_PTR address_xlation.len2,
1951
        ((Bit8u*)data) + BX_CPU_THIS_PTR address_xlation.len1);
1952
#else // BX_BIG_ENDIAN
1953
//AO    BX_NOTIFY_LIN_MEMORY_ACCESS(laddr, BX_CPU_THIS_PTR address_xlation.paddress1,
1954
//AO        BX_CPU_THIS_PTR address_xlation.len1, curr_pl, 
1955
//AO        BX_WRITE, ((Bit8u*)data) + (len - BX_CPU_THIS_PTR address_xlation.len1));
1956
    access_write_physical(BX_CPU_THIS_PTR address_xlation.paddress1,
1957
        BX_CPU_THIS_PTR address_xlation.len1,
1958
        ((Bit8u*)data) + (len - BX_CPU_THIS_PTR address_xlation.len1));
1959
//AO    BX_NOTIFY_LIN_MEMORY_ACCESS(laddr2, BX_CPU_THIS_PTR address_xlation.paddress2,
1960
//AO        BX_CPU_THIS_PTR address_xlation.len2, curr_pl, 
1961
//AO        BX_WRITE, (Bit8u*) data);
1962
    access_write_physical(BX_CPU_THIS_PTR address_xlation.paddress2,
1963
        BX_CPU_THIS_PTR address_xlation.len2, data);
1964
#endif
1965
 
1966
#if BX_X86_DEBUGGER
1967
    hwbreakpoint_match(laddr,  BX_CPU_THIS_PTR address_xlation.len1, BX_WRITE);
1968
    hwbreakpoint_match(laddr2, BX_CPU_THIS_PTR address_xlation.len2, BX_WRITE);
1969
#endif
1970
  }
1971
}
1972
 
1973
void BX_CPU_C::access_read_linear(bx_address laddr, unsigned len, unsigned curr_pl, unsigned xlate_rw, void *data)
1974
{
1975
  BX_ASSERT(xlate_rw == BX_READ || xlate_rw == BX_RW);
1976
 
1977
  Bit32u pageOffset = PAGE_OFFSET(laddr);
1978
 
1979
  bx_TLB_entry *tlbEntry = BX_TLB_ENTRY_OF(laddr);
1980
 
1981
  /* check for reference across multiple pages */
1982
  if ((pageOffset + len) <= 4096) {
1983
    // Access within single page.
1984
    BX_CPU_THIS_PTR address_xlation.paddress1 = translate_linear(tlbEntry, laddr, (curr_pl == 3), xlate_rw);
1985
    BX_CPU_THIS_PTR address_xlation.pages     = 1;
1986
    access_read_physical(BX_CPU_THIS_PTR address_xlation.paddress1, len, data);
1987
//AO    BX_NOTIFY_LIN_MEMORY_ACCESS(laddr, BX_CPU_THIS_PTR address_xlation.paddress1, len, curr_pl, BX_READ, (Bit8u*) data);
1988
 
1989
#if BX_X86_DEBUGGER
1990
    hwbreakpoint_match(laddr, len, xlate_rw);
1991
#endif
1992
  }
1993
  else {
1994
    // access across 2 pages
1995
    BX_CPU_THIS_PTR address_xlation.paddress1 = translate_linear(tlbEntry, laddr, (curr_pl == 3), xlate_rw);
1996
    BX_CPU_THIS_PTR address_xlation.len1 = 4096 - pageOffset;
1997
    BX_CPU_THIS_PTR address_xlation.len2 = len - BX_CPU_THIS_PTR address_xlation.len1;
1998
    BX_CPU_THIS_PTR address_xlation.pages = 2;
1999
    bx_address laddr2 = laddr + BX_CPU_THIS_PTR address_xlation.len1;
2000
#if BX_SUPPORT_X86_64
2001
    if (! long64_mode()) laddr2 &= 0xffffffff; /* handle linear address wrap in legacy mode */
2002
#endif
2003
    BX_CPU_THIS_PTR address_xlation.paddress2 = translate_linear(BX_TLB_ENTRY_OF(laddr2), laddr2, (curr_pl == 3), xlate_rw);
2004
 
2005
#ifdef BX_LITTLE_ENDIAN
2006
    access_read_physical(BX_CPU_THIS_PTR address_xlation.paddress1,
2007
        BX_CPU_THIS_PTR address_xlation.len1, data);
2008
//AO    BX_NOTIFY_LIN_MEMORY_ACCESS(laddr, BX_CPU_THIS_PTR address_xlation.paddress1,
2009
//AO        BX_CPU_THIS_PTR address_xlation.len1, curr_pl,
2010
//AO        BX_READ, (Bit8u*) data);
2011
    access_read_physical(BX_CPU_THIS_PTR address_xlation.paddress2,
2012
        BX_CPU_THIS_PTR address_xlation.len2,
2013
        ((Bit8u*)data) + BX_CPU_THIS_PTR address_xlation.len1);
2014
//AO    BX_NOTIFY_LIN_MEMORY_ACCESS(laddr2, BX_CPU_THIS_PTR address_xlation.paddress2,
2015
//AO        BX_CPU_THIS_PTR address_xlation.len2, curr_pl,
2016
//AO        BX_READ, ((Bit8u*)data) + BX_CPU_THIS_PTR address_xlation.len1);
2017
#else // BX_BIG_ENDIAN
2018
    access_read_physical(BX_CPU_THIS_PTR address_xlation.paddress1,
2019
        BX_CPU_THIS_PTR address_xlation.len1,
2020
        ((Bit8u*)data) + (len - BX_CPU_THIS_PTR address_xlation.len1));
2021
//AO    BX_NOTIFY_LIN_MEMORY_ACCESS(laddr, BX_CPU_THIS_PTR address_xlation.paddress1,
2022
//AO        BX_CPU_THIS_PTR address_xlation.len1, curr_pl,
2023
//AO        BX_READ, ((Bit8u*)data) + (len - BX_CPU_THIS_PTR address_xlation.len1));
2024
    access_read_physical(BX_CPU_THIS_PTR address_xlation.paddress2,
2025
        BX_CPU_THIS_PTR address_xlation.len2, data);
2026
//AO    BX_NOTIFY_LIN_MEMORY_ACCESS(laddr2, BX_CPU_THIS_PTR address_xlation.paddress2,
2027
//AO        BX_CPU_THIS_PTR address_xlation.len2, curr_pl, 
2028
//AO        BX_READ, (Bit8u*) data);
2029
#endif
2030
 
2031
#if BX_X86_DEBUGGER
2032
    hwbreakpoint_match(laddr,  BX_CPU_THIS_PTR address_xlation.len1, xlate_rw);
2033
    hwbreakpoint_match(laddr2, BX_CPU_THIS_PTR address_xlation.len2, xlate_rw);
2034
#endif
2035
  }
2036
}
2037
 
2038
void BX_CPU_C::access_write_physical(bx_phy_address paddr, unsigned len, void *data)
2039
{
2040
#if BX_SUPPORT_VMX && BX_SUPPORT_X86_64
2041
  if (is_virtual_apic_page(paddr)) {
2042
    VMX_Virtual_Apic_Write(paddr, len, data);
2043
    return;
2044
  }
2045
#endif
2046
 
2047
#if BX_SUPPORT_APIC
2048
  if (BX_CPU_THIS_PTR lapic.is_selected(paddr)) {
2049
    BX_CPU_THIS_PTR lapic.write(paddr, data, len);
2050
    return;
2051
  }
2052
#endif
2053
 
2054
  BX_MEM(0)->writePhysicalPage(BX_CPU_THIS, paddr, len, data);
2055
}
2056
 
2057
void BX_CPU_C::access_read_physical(bx_phy_address paddr, unsigned len, void *data)
2058
{
2059
#if BX_SUPPORT_VMX && BX_SUPPORT_X86_64
2060
  if (is_virtual_apic_page(paddr)) {
2061
    paddr = VMX_Virtual_Apic_Read(paddr, len, data);
2062
  }
2063
#endif
2064
 
2065
#if BX_SUPPORT_APIC
2066
  if (BX_CPU_THIS_PTR lapic.is_selected(paddr)) {
2067
    BX_CPU_THIS_PTR lapic.read(paddr, data, len);
2068
    return;
2069
  }
2070
#endif
2071
 
2072
  BX_MEM(0)->readPhysicalPage(BX_CPU_THIS, paddr, len, data);
2073
}
2074
 
2075
bx_hostpageaddr_t BX_CPU_C::getHostMemAddr(bx_phy_address paddr, unsigned rw)
2076
{
2077
#if BX_SUPPORT_VMX && BX_SUPPORT_X86_64
2078
  if (is_virtual_apic_page(paddr))
2079
    return 0; // Do not allow direct access to virtual apic page
2080
#endif
2081
 
2082
#if BX_SUPPORT_APIC
2083
  if (BX_CPU_THIS_PTR lapic.is_selected(paddr))
2084
    return 0; // Vetoed!  APIC address space
2085
#endif
2086
 
2087
  return (bx_hostpageaddr_t) BX_MEM(0)->getHostMemAddr(BX_CPU_THIS, paddr, rw);
2088
}
2089
 
2090
#if BX_LARGE_RAMFILE
2091
bx_bool BX_CPU_C::check_addr_in_tlb_buffers(const Bit8u *addr, const Bit8u *end)
2092
{
2093
  for (unsigned tlb_entry_num=0; tlb_entry_num < BX_TLB_SIZE; tlb_entry_num++) {
2094
    if (((BX_CPU_THIS_PTR TLB.entry[tlb_entry_num].hostPageAddr)>=(const bx_hostpageaddr_t)addr) &&
2095
        ((BX_CPU_THIS_PTR TLB.entry[tlb_entry_num].hostPageAddr)<(const bx_hostpageaddr_t)end))
2096
      return true;
2097
  }
2098
  return false;
2099
}
2100
#endif

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