1 |
2 |
alfik |
/////////////////////////////////////////////////////////////////////////
|
2 |
|
|
// $Id: segment_ctrl.cc 11313 2012-08-05 13:52:40Z sshwarts $
|
3 |
|
|
/////////////////////////////////////////////////////////////////////////
|
4 |
|
|
//
|
5 |
|
|
// Copyright (C) 2001-2012 The Bochs Project
|
6 |
|
|
//
|
7 |
|
|
// This library is free software; you can redistribute it and/or
|
8 |
|
|
// modify it under the terms of the GNU Lesser General Public
|
9 |
|
|
// License as published by the Free Software Foundation; either
|
10 |
|
|
// version 2 of the License, or (at your option) any later version.
|
11 |
|
|
//
|
12 |
|
|
// This library is distributed in the hope that it will be useful,
|
13 |
|
|
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
14 |
|
|
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
15 |
|
|
// Lesser General Public License for more details.
|
16 |
|
|
//
|
17 |
|
|
// You should have received a copy of the GNU Lesser General Public
|
18 |
|
|
// License along with this library; if not, write to the Free Software
|
19 |
|
|
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
|
20 |
|
|
//
|
21 |
|
|
/////////////////////////////////////////////////////////////////////////
|
22 |
|
|
|
23 |
|
|
#define NEED_CPU_REG_SHORTCUTS 1
|
24 |
|
|
#include "bochs.h"
|
25 |
|
|
#include "cpu.h"
|
26 |
|
|
#define LOG_THIS BX_CPU_THIS_PTR
|
27 |
|
|
|
28 |
|
|
// LES/LDS can't be called from long64 mode
|
29 |
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LES_GwMp(bxInstruction_c *i)
|
30 |
|
|
{
|
31 |
|
|
BX_ASSERT(BX_CPU_THIS_PTR cpu_mode != BX_MODE_LONG_64);
|
32 |
|
|
|
33 |
|
|
Bit32u eaddr = (Bit32u) BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
34 |
|
|
|
35 |
|
|
Bit16u reg_16 = read_virtual_word_32(i->seg(), eaddr);
|
36 |
|
|
Bit16u es = read_virtual_word_32(i->seg(), (eaddr + 2) & i->asize_mask());
|
37 |
|
|
|
38 |
|
|
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES], es);
|
39 |
|
|
|
40 |
|
|
BX_WRITE_16BIT_REG(i->dst(), reg_16);
|
41 |
|
|
|
42 |
|
|
BX_NEXT_INSTR(i);
|
43 |
|
|
}
|
44 |
|
|
|
45 |
|
|
// LES/LDS can't be called from long64 mode
|
46 |
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LES_GdMp(bxInstruction_c *i)
|
47 |
|
|
{
|
48 |
|
|
BX_ASSERT(BX_CPU_THIS_PTR cpu_mode != BX_MODE_LONG_64);
|
49 |
|
|
|
50 |
|
|
Bit32u eaddr = (Bit32u) BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
51 |
|
|
|
52 |
|
|
Bit16u es = read_virtual_word_32(i->seg(), (eaddr + 4) & i->asize_mask());
|
53 |
|
|
Bit32u reg_32 = read_virtual_dword_32(i->seg(), eaddr);
|
54 |
|
|
|
55 |
|
|
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES], es);
|
56 |
|
|
|
57 |
|
|
BX_WRITE_32BIT_REGZ(i->dst(), reg_32);
|
58 |
|
|
|
59 |
|
|
BX_NEXT_INSTR(i);
|
60 |
|
|
}
|
61 |
|
|
|
62 |
|
|
// LES/LDS can't be called from long64 mode
|
63 |
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LDS_GwMp(bxInstruction_c *i)
|
64 |
|
|
{
|
65 |
|
|
BX_ASSERT(BX_CPU_THIS_PTR cpu_mode != BX_MODE_LONG_64);
|
66 |
|
|
|
67 |
|
|
Bit32u eaddr = (Bit32u) BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
68 |
|
|
|
69 |
|
|
Bit16u reg_16 = read_virtual_word_32(i->seg(), eaddr);
|
70 |
|
|
Bit16u ds = read_virtual_word_32(i->seg(), (eaddr + 2) & i->asize_mask());
|
71 |
|
|
|
72 |
|
|
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS], ds);
|
73 |
|
|
|
74 |
|
|
BX_WRITE_16BIT_REG(i->dst(), reg_16);
|
75 |
|
|
|
76 |
|
|
BX_NEXT_INSTR(i);
|
77 |
|
|
}
|
78 |
|
|
|
79 |
|
|
// LES/LDS can't be called from long64 mode
|
80 |
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LDS_GdMp(bxInstruction_c *i)
|
81 |
|
|
{
|
82 |
|
|
BX_ASSERT(BX_CPU_THIS_PTR cpu_mode != BX_MODE_LONG_64);
|
83 |
|
|
|
84 |
|
|
Bit32u eaddr = (Bit32u) BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
85 |
|
|
|
86 |
|
|
Bit16u ds = read_virtual_word_32(i->seg(), (eaddr + 4) & i->asize_mask());
|
87 |
|
|
Bit32u reg_32 = read_virtual_dword_32(i->seg(), eaddr);
|
88 |
|
|
|
89 |
|
|
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS], ds);
|
90 |
|
|
|
91 |
|
|
BX_WRITE_32BIT_REGZ(i->dst(), reg_32);
|
92 |
|
|
|
93 |
|
|
BX_NEXT_INSTR(i);
|
94 |
|
|
}
|
95 |
|
|
|
96 |
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LFS_GwMp(bxInstruction_c *i)
|
97 |
|
|
{
|
98 |
|
|
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
99 |
|
|
|
100 |
|
|
Bit16u reg_16 = read_virtual_word(i->seg(), eaddr);
|
101 |
|
|
Bit16u fs = read_virtual_word(i->seg(), (eaddr + 2) & i->asize_mask());
|
102 |
|
|
|
103 |
|
|
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS], fs);
|
104 |
|
|
|
105 |
|
|
BX_WRITE_16BIT_REG(i->dst(), reg_16);
|
106 |
|
|
|
107 |
|
|
BX_NEXT_INSTR(i);
|
108 |
|
|
}
|
109 |
|
|
|
110 |
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LFS_GdMp(bxInstruction_c *i)
|
111 |
|
|
{
|
112 |
|
|
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
113 |
|
|
|
114 |
|
|
Bit16u fs = read_virtual_word(i->seg(), (eaddr + 4) & i->asize_mask());
|
115 |
|
|
Bit32u reg_32 = read_virtual_dword(i->seg(), eaddr);
|
116 |
|
|
|
117 |
|
|
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS], fs);
|
118 |
|
|
|
119 |
|
|
BX_WRITE_32BIT_REGZ(i->dst(), reg_32);
|
120 |
|
|
|
121 |
|
|
BX_NEXT_INSTR(i);
|
122 |
|
|
}
|
123 |
|
|
|
124 |
|
|
#if BX_SUPPORT_X86_64
|
125 |
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LFS_GqMp(bxInstruction_c *i)
|
126 |
|
|
{
|
127 |
|
|
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
128 |
|
|
|
129 |
|
|
Bit16u fs = read_virtual_word_64(i->seg(), (eaddr + 8) & i->asize_mask());
|
130 |
|
|
Bit64u reg_64 = read_virtual_qword_64(i->seg(), eaddr);
|
131 |
|
|
|
132 |
|
|
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS], fs);
|
133 |
|
|
|
134 |
|
|
BX_WRITE_64BIT_REG(i->dst(), reg_64);
|
135 |
|
|
|
136 |
|
|
BX_NEXT_INSTR(i);
|
137 |
|
|
}
|
138 |
|
|
#endif
|
139 |
|
|
|
140 |
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LGS_GwMp(bxInstruction_c *i)
|
141 |
|
|
{
|
142 |
|
|
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
143 |
|
|
|
144 |
|
|
Bit16u reg_16 = read_virtual_word(i->seg(), eaddr);
|
145 |
|
|
Bit16u gs = read_virtual_word(i->seg(), (eaddr + 2) & i->asize_mask());
|
146 |
|
|
|
147 |
|
|
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS], gs);
|
148 |
|
|
|
149 |
|
|
BX_WRITE_16BIT_REG(i->dst(), reg_16);
|
150 |
|
|
|
151 |
|
|
BX_NEXT_INSTR(i);
|
152 |
|
|
}
|
153 |
|
|
|
154 |
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LGS_GdMp(bxInstruction_c *i)
|
155 |
|
|
{
|
156 |
|
|
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
157 |
|
|
|
158 |
|
|
Bit16u gs = read_virtual_word(i->seg(), (eaddr + 4) & i->asize_mask());
|
159 |
|
|
Bit32u reg_32 = read_virtual_dword(i->seg(), eaddr);
|
160 |
|
|
|
161 |
|
|
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS], gs);
|
162 |
|
|
|
163 |
|
|
BX_WRITE_32BIT_REGZ(i->dst(), reg_32);
|
164 |
|
|
|
165 |
|
|
BX_NEXT_INSTR(i);
|
166 |
|
|
}
|
167 |
|
|
|
168 |
|
|
#if BX_SUPPORT_X86_64
|
169 |
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LGS_GqMp(bxInstruction_c *i)
|
170 |
|
|
{
|
171 |
|
|
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
172 |
|
|
|
173 |
|
|
Bit16u gs = read_virtual_word_64(i->seg(), (eaddr + 8) & i->asize_mask());
|
174 |
|
|
Bit64u reg_64 = read_virtual_qword_64(i->seg(), eaddr);
|
175 |
|
|
|
176 |
|
|
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS], gs);
|
177 |
|
|
|
178 |
|
|
BX_WRITE_64BIT_REG(i->dst(), reg_64);
|
179 |
|
|
|
180 |
|
|
BX_NEXT_INSTR(i);
|
181 |
|
|
}
|
182 |
|
|
#endif
|
183 |
|
|
|
184 |
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LSS_GwMp(bxInstruction_c *i)
|
185 |
|
|
{
|
186 |
|
|
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
187 |
|
|
|
188 |
|
|
Bit16u reg_16 = read_virtual_word(i->seg(), eaddr);
|
189 |
|
|
Bit16u ss = read_virtual_word(i->seg(), (eaddr + 2) & i->asize_mask());
|
190 |
|
|
|
191 |
|
|
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS], ss);
|
192 |
|
|
|
193 |
|
|
BX_WRITE_16BIT_REG(i->dst(), reg_16);
|
194 |
|
|
|
195 |
|
|
BX_NEXT_INSTR(i);
|
196 |
|
|
}
|
197 |
|
|
|
198 |
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LSS_GdMp(bxInstruction_c *i)
|
199 |
|
|
{
|
200 |
|
|
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
201 |
|
|
|
202 |
|
|
Bit16u ss = read_virtual_word(i->seg(), (eaddr + 4) & i->asize_mask());
|
203 |
|
|
Bit32u reg_32 = read_virtual_dword(i->seg(), eaddr);
|
204 |
|
|
|
205 |
|
|
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS], ss);
|
206 |
|
|
|
207 |
|
|
BX_WRITE_32BIT_REGZ(i->dst(), reg_32);
|
208 |
|
|
|
209 |
|
|
BX_NEXT_INSTR(i);
|
210 |
|
|
}
|
211 |
|
|
|
212 |
|
|
#if BX_SUPPORT_X86_64
|
213 |
|
|
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::LSS_GqMp(bxInstruction_c *i)
|
214 |
|
|
{
|
215 |
|
|
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
|
216 |
|
|
|
217 |
|
|
Bit16u ss = read_virtual_word_64(i->seg(), (eaddr + 8) & i->asize_mask());
|
218 |
|
|
Bit64u reg_64 = read_virtual_qword_64(i->seg(), eaddr);
|
219 |
|
|
|
220 |
|
|
load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS], ss);
|
221 |
|
|
|
222 |
|
|
BX_WRITE_64BIT_REG(i->dst(), reg_64);
|
223 |
|
|
|
224 |
|
|
BX_NEXT_INSTR(i);
|
225 |
|
|
}
|
226 |
|
|
#endif
|