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/////////////////////////////////////////////////////////////////////////
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// $Id: instrument.h 11295 2012-07-24 15:32:55Z sshwarts $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2006-2012 Stanislav Shwartsman
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// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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#if BX_INSTRUMENTATION
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class bxInstruction_c;
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// define if you want to store instruction opcode bytes in bxInstruction_c
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//#define BX_INSTR_STORE_OPCODE_BYTES
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void bx_instr_init_env(void);
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void bx_instr_exit_env(void);
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// called from the CPU core
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void bx_instr_initialize(unsigned cpu);
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void bx_instr_exit(unsigned cpu);
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void bx_instr_reset(unsigned cpu, unsigned type);
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void bx_instr_hlt(unsigned cpu);
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void bx_instr_mwait(unsigned cpu, bx_phy_address addr, unsigned len, Bit32u flags);
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void bx_instr_debug_promt();
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void bx_instr_debug_cmd(const char *cmd);
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void bx_instr_cnear_branch_taken(unsigned cpu, bx_address branch_eip, bx_address new_eip);
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void bx_instr_cnear_branch_not_taken(unsigned cpu, bx_address branch_eip);
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void bx_instr_ucnear_branch(unsigned cpu, unsigned what, bx_address branch_eip, bx_address new_eip);
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void bx_instr_far_branch(unsigned cpu, unsigned what, Bit16u new_cs, bx_address new_eip);
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void bx_instr_opcode(unsigned cpu, bxInstruction_c *i, const Bit8u *opcode, unsigned len, bx_bool is32, bx_bool is64);
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//AO extended; was cpu,vector
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void bx_instr_interrupt(unsigned cpu, unsigned vector, unsigned type, bx_bool push_error, Bit16u error_code);
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void bx_instr_exception(unsigned cpu, unsigned vector, unsigned error_code);
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void bx_instr_hwinterrupt(unsigned cpu, unsigned vector, Bit16u cs, bx_address eip);
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void bx_instr_tlb_cntrl(unsigned cpu, unsigned what, bx_phy_address new_cr3);
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void bx_instr_cache_cntrl(unsigned cpu, unsigned what);
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void bx_instr_prefetch_hint(unsigned cpu, unsigned what, unsigned seg, bx_address offset);
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void bx_instr_clflush(unsigned cpu, bx_address laddr, bx_phy_address paddr);
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void bx_instr_before_execution(unsigned cpu, bxInstruction_c *i);
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void bx_instr_after_execution(unsigned cpu, bxInstruction_c *i);
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void bx_instr_repeat_iteration(unsigned cpu, bxInstruction_c *i);
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void bx_instr_inp(Bit16u addr, unsigned len);
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void bx_instr_inp2(Bit16u addr, unsigned len, unsigned val);
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void bx_instr_outp(Bit16u addr, unsigned len, unsigned val);
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void bx_instr_lin_access(unsigned cpu, bx_address lin, bx_address phy, unsigned len, unsigned rw);
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void bx_instr_phy_access(unsigned cpu, bx_address phy, unsigned len, unsigned rw);
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void bx_instr_wrmsr(unsigned cpu, unsigned addr, Bit64u value);
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/* initialization/deinitialization of instrumentalization*/
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#define BX_INSTR_INIT_ENV() bx_instr_init_env()
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#define BX_INSTR_EXIT_ENV() bx_instr_exit_env()
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/* simulation init, shutdown, reset */
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#define BX_INSTR_INITIALIZE(cpu_id) bx_instr_initialize(cpu_id)
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#define BX_INSTR_EXIT(cpu_id) bx_instr_exit(cpu_id)
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#define BX_INSTR_RESET(cpu_id, type) bx_instr_reset(cpu_id, type)
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#define BX_INSTR_HLT(cpu_id) bx_instr_hlt(cpu_id)
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#define BX_INSTR_MWAIT(cpu_id, addr, len, flags) \
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bx_instr_mwait(cpu_id, addr, len, flags)
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/* called from command line debugger */
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#define BX_INSTR_DEBUG_PROMPT() bx_instr_debug_promt()
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#define BX_INSTR_DEBUG_CMD(cmd) bx_instr_debug_cmd(cmd)
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/* branch resolution */
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#define BX_INSTR_CNEAR_BRANCH_TAKEN(cpu_id, branch_eip, new_eip) bx_instr_cnear_branch_taken(cpu_id, branch_eip, new_eip)
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#define BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(cpu_id, branch_eip) bx_instr_cnear_branch_not_taken(cpu_id, branch_eip)
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#define BX_INSTR_UCNEAR_BRANCH(cpu_id, what, branch_eip, new_eip) bx_instr_ucnear_branch(cpu_id, what, branch_eip, new_eip)
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#define BX_INSTR_FAR_BRANCH(cpu_id, what, new_cs, new_eip) bx_instr_far_branch(cpu_id, what, new_cs, new_eip)
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/* decoding completed */
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#define BX_INSTR_OPCODE(cpu_id, i, opcode, len, is32, is64) \
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bx_instr_opcode(cpu_id, i, opcode, len, is32, is64)
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/* exceptional case and interrupt */
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#define BX_INSTR_EXCEPTION(cpu_id, vector, error_code) \
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bx_instr_exception(cpu_id, vector, error_code)
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//AO extended; was cpu_id, vector
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#define BX_INSTR_INTERRUPT(cpu_id, vector, type, push_error, error_code) bx_instr_interrupt(cpu_id, vector, type, push_error, error_code)
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#define BX_INSTR_HWINTERRUPT(cpu_id, vector, cs, eip) bx_instr_hwinterrupt(cpu_id, vector, cs, eip)
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/* TLB/CACHE control instruction executed */
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#define BX_INSTR_CLFLUSH(cpu_id, laddr, paddr) bx_instr_clflush(cpu_id, laddr, paddr)
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#define BX_INSTR_CACHE_CNTRL(cpu_id, what) bx_instr_cache_cntrl(cpu_id, what)
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#define BX_INSTR_TLB_CNTRL(cpu_id, what, new_cr3) bx_instr_tlb_cntrl(cpu_id, what, new_cr3)
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#define BX_INSTR_PREFETCH_HINT(cpu_id, what, seg, offset) \
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bx_instr_prefetch_hint(cpu_id, what, seg, offset)
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/* execution */
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#define BX_INSTR_BEFORE_EXECUTION(cpu_id, i) bx_instr_before_execution(cpu_id, i)
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#define BX_INSTR_AFTER_EXECUTION(cpu_id, i) bx_instr_after_execution(cpu_id, i)
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#define BX_INSTR_REPEAT_ITERATION(cpu_id, i) bx_instr_repeat_iteration(cpu_id, i)
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/* linear memory access */
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#define BX_INSTR_LIN_ACCESS(cpu_id, lin, phy, len, rw) bx_instr_lin_access(cpu_id, lin, phy, len, rw)
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/* physical memory access */
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#define BX_INSTR_PHY_ACCESS(cpu_id, phy, len, rw) bx_instr_phy_access(cpu_id, phy, len, rw)
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/* feedback from device units */
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#define BX_INSTR_INP(addr, len) bx_instr_inp(addr, len)
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#define BX_INSTR_INP2(addr, len, val) bx_instr_inp2(addr, len, val)
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#define BX_INSTR_OUTP(addr, len, val) bx_instr_outp(addr, len, val)
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/* wrmsr callback */
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#define BX_INSTR_WRMSR(cpu_id, addr, value) bx_instr_wrmsr(cpu_id, addr, value)
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#else
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/* initialization/deinitialization of instrumentalization */
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#define BX_INSTR_INIT_ENV()
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#define BX_INSTR_EXIT_ENV()
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/* simulation init, shutdown, reset */
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#define BX_INSTR_INITIALIZE(cpu_id)
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#define BX_INSTR_EXIT(cpu_id)
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#define BX_INSTR_RESET(cpu_id, type)
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#define BX_INSTR_HLT(cpu_id)
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#define BX_INSTR_MWAIT(cpu_id, addr, len, flags)
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/* called from command line debugger */
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#define BX_INSTR_DEBUG_PROMPT()
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#define BX_INSTR_DEBUG_CMD(cmd)
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/* branch resolution */
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#define BX_INSTR_CNEAR_BRANCH_TAKEN(cpu_id, branch_eip, new_eip)
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#define BX_INSTR_CNEAR_BRANCH_NOT_TAKEN(cpu_id, branch_eip)
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#define BX_INSTR_UCNEAR_BRANCH(cpu_id, what, branch_eip, new_eip)
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#define BX_INSTR_FAR_BRANCH(cpu_id, what, new_cs, new_eip)
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/* decoding completed */
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#define BX_INSTR_OPCODE(cpu_id, i, opcode, len, is32, is64)
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/* exceptional case and interrupt */
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#define BX_INSTR_EXCEPTION(cpu_id, vector, error_code)
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#define BX_INSTR_INTERRUPT(cpu_id, vector)
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#define BX_INSTR_HWINTERRUPT(cpu_id, vector, cs, eip)
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/* TLB/CACHE control instruction executed */
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#define BX_INSTR_CLFLUSH(cpu_id, laddr, paddr)
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#define BX_INSTR_CACHE_CNTRL(cpu_id, what)
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#define BX_INSTR_TLB_CNTRL(cpu_id, what, new_cr3)
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#define BX_INSTR_PREFETCH_HINT(cpu_id, what, seg, offset)
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/* execution */
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#define BX_INSTR_BEFORE_EXECUTION(cpu_id, i)
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#define BX_INSTR_AFTER_EXECUTION(cpu_id, i)
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#define BX_INSTR_REPEAT_ITERATION(cpu_id, i)
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/* linear memory access */
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#define BX_INSTR_LIN_ACCESS(cpu_id, lin, phy, len, rw)
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/* physical memory access */
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#define BX_INSTR_PHY_ACCESS(cpu_id, phy, len, rw)
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/* feedback from device units */
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#define BX_INSTR_INP(addr, len)
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#define BX_INSTR_INP2(addr, len, val)
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#define BX_INSTR_OUTP(addr, len, val)
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/* wrmsr callback */
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#define BX_INSTR_WRMSR(cpu_id, addr, value)
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#endif
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