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[/] [ao486/] [trunk/] [rtl/] [ao486/] [autogen/] [dcache_control_ram.v] - Blame information for rev 2

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Line No. Rev Author Line
1 2 alfik
//======================================================== conditions
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wire cond_0 = init_done == `FALSE;
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wire cond_1 = invd_counter == 8'd255;
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wire cond_2 = state == STATE_IDLE;
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wire cond_3 = init_done && invddata_do;
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wire cond_4 = init_done && wbinvddata_do;
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wire cond_5 = state == STATE_INVD;
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wire cond_6 = state == STATE_WBINVD;
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wire cond_7 = wbinvd_valid;
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wire cond_8 = writeline_done;
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wire cond_9 = wbinvd_counter == 10'd1023;
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//======================================================== saves
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wire [9:0] wbinvd_counter_to_reg =
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    (cond_6 && cond_7 && cond_8)? (      wbinvd_counter_next) :
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    (cond_6 && ~cond_7)? ( wbinvd_counter_next) :
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    wbinvd_counter;
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wire  after_invalidate_to_reg =
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    (cond_0 && cond_1)? ( `TRUE) :
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    (cond_2)? ( `FALSE) :
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    (cond_5 && cond_1)? ( `TRUE) :
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    (cond_6 && cond_7 && cond_8 && cond_9)? ( `TRUE) :
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    (cond_6 && ~cond_7 && cond_9)? ( `TRUE) :
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    after_invalidate;
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wire [7:0] invd_counter_to_reg =
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    (cond_0)? ( invd_counter + 8'd1) :
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    (cond_5)? ( invd_counter + 8'd1) :
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    invd_counter;
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wire [1:0] state_to_reg =
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    (cond_2 && cond_3)? ( STATE_INVD) :
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    (cond_2 && ~cond_3 && cond_4)? ( STATE_WBINVD) :
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    (cond_5 && cond_1)? ( STATE_IDLE) :
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    (cond_6 && cond_7 && cond_8 && cond_9)? ( STATE_IDLE) :
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    (cond_6 && ~cond_7 && cond_9)? ( STATE_IDLE) :
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    state;
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wire  init_done_to_reg =
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    (cond_0 && cond_1)? (        `TRUE) :
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    init_done;
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//======================================================== always
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always @(posedge clk or negedge rst_n) begin
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    if(rst_n == 1'b0) wbinvd_counter <= 10'd0;
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    else              wbinvd_counter <= wbinvd_counter_to_reg;
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end
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always @(posedge clk or negedge rst_n) begin
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    if(rst_n == 1'b0) after_invalidate <= 1'd0;
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    else              after_invalidate <= after_invalidate_to_reg;
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end
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always @(posedge clk or negedge rst_n) begin
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    if(rst_n == 1'b0) invd_counter <= 8'd0;
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    else              invd_counter <= invd_counter_to_reg;
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end
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always @(posedge clk or negedge rst_n) begin
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    if(rst_n == 1'b0) state <= 2'd0;
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    else              state <= state_to_reg;
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end
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always @(posedge clk or negedge rst_n) begin
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    if(rst_n == 1'b0) init_done <= 1'd0;
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    else              init_done <= init_done_to_reg;
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end
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//======================================================== sets
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assign wbinvddata_done =
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    (cond_6 && cond_7 && cond_8 && cond_9)? (`TRUE) :
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    (cond_6 && ~cond_7 && cond_9)? (`TRUE) :
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    1'd0;
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assign writeline_do =
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    (cond_6 && cond_7)? (`TRUE) :
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    1'd0;
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assign wbinvdread_address =
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    (cond_2 && ~cond_3 && cond_4)? ( wbinvd_counter[9:2]) :
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    (cond_6 && cond_7 && cond_8)? ( wbinvd_counter_next[9:2]) :
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    (cond_6 && cond_7 && ~cond_8)? ( wbinvd_counter[9:2]) :
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    (cond_6 && ~cond_7)? ( wbinvd_counter_next[9:2]) :
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    8'd0;
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assign wbinvdread_do =
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    (cond_2 && ~cond_3 && cond_4)? (`TRUE) :
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    (cond_6 && cond_7 && cond_8)? (`TRUE) :
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    (cond_6 && ~cond_7)? (`TRUE) :
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    1'd0;
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assign writeline_line =
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    (cond_6 && cond_7)? (    wbinvd_line[127:0]) :
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    128'd0;
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assign start_wbinvd =
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    (cond_2 && ~cond_3 && cond_4)? (`TRUE) :
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    1'd0;
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assign invddata_done =
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    (cond_5 && cond_1)? (`TRUE) :
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    1'd0;
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assign writeline_address =
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    (cond_6 && cond_7)? ( { wbinvd_line[147:128], wbinvd_counter[9:2], 4'd0 }) :
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    32'd0;
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assign wbinvd_write_control =
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    (cond_6 && cond_7 && cond_8)? ( wbinvd_counter[1:0] == 2'd3) :
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    (cond_6 && ~cond_7)? ( wbinvd_counter[1:0] == 2'd3) :
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    1'd0;

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