Subversion Repositories ao486

wire [4:0] rd_call_gate_param;

assign rd_call_gate_param = glob_param_3[24:20] - 5'd1;

wire rd_io_allow_1_fault;

wire rd_io_allow_2_fault;

assign rd_io_allow_1_fault = rd_cmd == `CMD_io_allow && rd_cmdex == `CMDEX_io_allow_1 && (   ~(tr_cache_valid) || (tr_cache[`DESC_BITS_TYPE] != `DESC_TSS_AVAIL_386 && tr_cache[`DESC_BITS_TYPE] != `DESC_TSS_BUSY_386) || tr_limit < 32'd103 );

assign rd_io_allow_2_fault = rd_cmd == `CMD_io_allow && rd_cmdex == `CMDEX_io_allow_2 && ({ 16'd0, rd_memory_last[15:0] } + { 16'd0, 3'd0, glob_param_1[15:3] }) >= tr_limit;

assign rd_io_allow_fault = rd_io_allow_1_fault || rd_io_allow_2_fault;

wire rd_imul_modregrm_mutex_busy;

assign rd_imul_modregrm_mutex_busy = (  rd_decoder[3]  && rd_mutex_busy_modregrm_reg) || (~(rd_decoder[3]) && rd_mutex_busy_eax);

wire rd_arith_modregrm_to_rm;

wire rd_arith_modregrm_to_reg;

assign rd_arith_modregrm_to_rm = ~(rd_decoder[1]);

assign rd_arith_modregrm_to_reg= rd_decoder[1];

wire rd_in_condition;

assign rd_in_condition = (rd_mutex_busy_active && (rd_cmdex == `CMDEX_IN_imm || rd_cmdex == `CMDEX_IN_dx) && ~(io_allow_check_needed)) || (rd_cmdex == `CMDEX_IN_dx && rd_mutex_busy_edx);

wire [31:0] rd_offset_for_esp_from_tss;

wire [31:0] rd_offset_for_ss_from_tss;

wire [31:0] r_limit_for_ss_esp_from_tss;

wire        rd_ss_esp_from_tss_386;

assign rd_ss_esp_from_tss_386 = tr_cache[`DESC_BITS_TYPE] == `DESC_TSS_AVAIL_386 || tr_cache[`DESC_BITS_TYPE] == `DESC_TSS_BUSY_386;

assign r_limit_for_ss_esp_from_tss = (rd_ss_esp_from_tss_386)?   { 27'd0, glob_descriptor[`DESC_BITS_DPL], 3'd0 } + 32'd11 : { 28'd0, glob_descriptor[`DESC_BITS_DPL], 2'd0 } + 32'd5;

assign rd_offset_for_ss_from_tss = (rd_ss_esp_from_tss_386)?   { 27'd0, glob_descriptor[`DESC_BITS_DPL], 3'd0 } + 32'd8 : { 28'd0, glob_descriptor[`DESC_BITS_DPL], 2'd0 } + 32'd4;

assign rd_offset_for_esp_from_tss = (rd_ss_esp_from_tss_386)?   { 27'd0, glob_descriptor[`DESC_BITS_DPL], 3'd0 } + 32'd4 : { 28'd0, glob_descriptor[`DESC_BITS_DPL], 2'd0 } + 32'd2;

assign rd_ss_esp_from_tss_fault = (   (rd_cmd == `CMD_CALL_2 && rd_cmdex == `CMDEX_CALL_2_call_gate_more_STEP_0) || (rd_cmd == `CMD_int_2  && rd_cmdex == `CMDEX_int_2_int_trap_gate_more_STEP_0) ) && r_limit_for_ss_esp_from_tss > tr_limit;

wire [31:0] rd_task_switch_linear_next;

reg [31:0] rd_task_switch_linear_reg;

assign rd_task_switch_linear_next = (glob_descriptor[`DESC_BITS_TYPE] <= 4'd3)? rd_task_switch_linear_reg + 32'd2 : rd_task_switch_linear_reg + 32'd4;

always @(posedge clk or negedge rst_n) begin if(rst_n == 1'b0)                                                               rd_task_switch_linear_reg <= 32'd0; else if(rd_cmd == `CMD_task_switch && rd_cmdex == `CMDEX_task_switch_STEP_12)   rd_task_switch_linear_reg <= rd_system_linear; else if(rd_ready)                                                               rd_task_switch_linear_reg <= rd_task_switch_linear_next;

end

//======================================================== conditions

wire cond_0 = rd_cmd == `CMD_XADD && rd_cmdex == `CMDEX_XADD_FIRST;

wire cond_1 = rd_modregrm_mod == 2'b11;

wire cond_2 = rd_mutex_busy_modregrm_reg || rd_mutex_busy_modregrm_rm;

wire cond_3 = rd_modregrm_mod != 2'b11;

wire cond_4 = rd_mutex_busy_modregrm_reg || rd_mutex_busy_memory;

wire cond_5 = ~(read_for_rd_ready);

wire cond_6 = rd_cmd == `CMD_XADD && rd_cmdex == `CMDEX_XADD_LAST;

wire cond_7 = rd_cmd == `CMD_CALL && rd_cmdex == `CMDEX_CALL_Ev_STEP_0;

wire cond_8 = rd_mutex_busy_modregrm_rm;

wire cond_9 = rd_mutex_busy_memory;

wire cond_10 = rd_cmd == `CMD_CALL && rd_cmdex == `CMDEX_CALL_Jv_STEP_0;

wire cond_11 = rd_cmd == `CMD_CALL && (rd_cmdex == `CMDEX_CALL_Ep_STEP_0 || rd_cmdex == `CMDEX_CALL_Ep_STEP_1);

wire cond_12 = rd_cmdex == `CMDEX_CALL_Ep_STEP_1;

wire cond_13 = rd_cmd == `CMD_CALL && rd_cmdex == `CMDEX_CALL_Ap_STEP_0;

wire cond_14 = rd_cmd == `CMD_CALL && rd_cmdex == `CMDEX_CALL_Ap_STEP_1;

wire cond_15 = rd_cmd == `CMD_CALL && rd_cmdex == `CMDEX_CALL_protected_STEP_0;

wire cond_16 = rd_mutex_busy_active;

wire cond_17 = glob_param_1[15:2] != 14'd0;

wire cond_18 = rd_cmd == `CMD_CALL_2 && rd_cmdex == `CMDEX_CALL_2_task_gate_STEP_0;

wire cond_19 = rd_cmd == `CMD_CALL_2 && rd_cmdex == `CMDEX_CALL_2_task_gate_STEP_1;

wire cond_20 = glob_param_1[`SELECTOR_BIT_TI] == 1'b0;

wire cond_21 = rd_cmd == `CMD_CALL_2 && rd_cmdex == `CMDEX_CALL_2_call_gate_STEP_1;

wire cond_22 = rd_cmd == `CMD_CALL_3 && (rd_cmdex == `CMDEX_CALL_3_call_gate_more_STEP_4 || rd_cmdex == `CMDEX_CALL_3_call_gate_more_STEP_5);

wire cond_23 = ~(glob_param_3[19]);

wire cond_24 = glob_param_3[19];

wire cond_25 = rd_ready;

wire cond_26 = rd_cmdex == `CMDEX_CALL_3_call_gate_more_STEP_4;

wire cond_27 = rd_cmd == `CMD_PUSH_MOV_SEG && { rd_cmdex[3], 3'b0 } == `CMDEX_PUSH_MOV_SEG_implicit;

wire cond_28 = rd_cmd == `CMD_PUSH_MOV_SEG && { rd_cmdex[3], 3'b0 } == `CMDEX_PUSH_MOV_SEG_modregrm;

wire cond_29 = ~(write_virtual_check_ready);

wire cond_30 = rd_cmd == `CMD_NEG;

wire cond_31 = rd_cmd == `CMD_INVLPG && rd_cmdex == `CMDEX_INVLPG_STEP_1;

wire cond_32 = ~(rd_address_effective_ready);

wire cond_33 = rd_cmd == `CMD_io_allow && rd_cmdex == `CMDEX_io_allow_1;

wire cond_34 = rd_io_allow_1_fault || rd_mutex_busy_active;

wire cond_35 = rd_cmd == `CMD_io_allow && rd_cmdex == `CMDEX_io_allow_2;

wire cond_36 = rd_io_allow_2_fault;

wire cond_37 = rd_cmd == `CMD_SCAS;

wire cond_38 = rd_mutex_busy_memory || (rd_mutex_busy_ecx && rd_prefix_group_1_rep != 2'd0);

wire cond_39 = ~(rd_string_ignore);

wire cond_40 = rd_cmd == `CMD_INC_DEC && { rd_cmdex[3:1], 1'b0 } == `CMDEX_INC_DEC_modregrm;

wire cond_41 = rd_cmd == `CMD_INC_DEC && { rd_cmdex[3:1], 1'b0 } == `CMDEX_INC_DEC_implicit;

wire cond_42 = rd_mutex_busy_implicit_reg;

wire cond_43 = rd_cmd == `CMD_RET_near && rd_cmdex != `CMDEX_RET_near_LAST;

wire cond_44 = rd_cmd == `CMD_ARPL;

wire cond_45 = rd_mutex_busy_modregrm_rm || rd_mutex_busy_modregrm_reg;

wire cond_46 = rd_mutex_busy_memory || rd_mutex_busy_modregrm_reg;

wire cond_47 = rd_cmd == `CMD_BSWAP;

wire cond_48 = rd_cmd == `CMD_LxS && rd_cmdex == `CMDEX_LxS_STEP_1;

wire cond_49 = ~(rd_address_effective_ready) || rd_mutex_busy_memory;

wire cond_50 = rd_operand_16bit;

wire cond_51 = rd_cmd == `CMD_LxS && rd_cmdex == `CMDEX_LxS_STEP_2;

wire cond_52 = rd_operand_32bit;

wire cond_53 = rd_cmd == `CMD_LxS && rd_cmdex == `CMDEX_LxS_STEP_3;

wire cond_54 = rd_cmd == `CMD_LxS && rd_cmdex == `CMDEX_LxS_STEP_LAST;

wire cond_55 = (rd_cmd == `CMD_MOV_to_seg || rd_cmd == `CMD_LLDT || rd_cmd == `CMD_LTR) && rd_cmdex == `CMDEX_MOV_to_seg_LLDT_LTR_STEP_1;

wire cond_56 = rd_cmd == `CMD_MOV_to_seg || cpl == 2'd0;

wire cond_57 = rd_cmd == `CMD_MOV_to_seg;

wire cond_58 = rd_cmd == `CMD_LLDT;

wire cond_59 = rd_cmd == `CMD_LTR;

wire cond_60 = rd_cmd == `CMD_CLC || rd_cmd == `CMD_CMC || rd_cmd == `CMD_CLD || rd_cmd == `CMD_STC || rd_cmd == `CMD_STD || rd_cmd == `CMD_SAHF;

wire cond_61 = rd_cmd == `CMD_int && rd_cmdex == `CMDEX_int_task_gate_STEP_0;

wire cond_62 = rd_cmd == `CMD_int && rd_cmdex == `CMDEX_int_task_gate_STEP_1;

wire cond_63 = rd_cmd == `CMD_int && rd_cmdex == `CMDEX_int_int_trap_gate_STEP_1;

wire cond_64 = rd_cmd == `CMD_int && rd_cmdex == `CMDEX_int_real_STEP_3;

wire cond_65 = rd_cmd == `CMD_int && rd_cmdex == `CMDEX_int_real_STEP_4;

wire cond_66 = rd_cmd == `CMD_int && rd_cmdex == `CMDEX_int_protected_STEP_1;

wire cond_67 = rd_cmd == `CMD_AAM || rd_cmd == `CMD_AAD;

wire cond_68 = rd_mutex_busy_eax;

wire cond_69 = rd_cmd == `CMD_load_seg && rd_cmdex == `CMDEX_load_seg_STEP_1;

wire cond_70 = v8086_mode;

wire cond_71 = real_mode;

wire cond_72 = protected_mode;

wire cond_73 = rd_cmd == `CMD_load_seg && rd_cmdex == `CMDEX_load_seg_STEP_2;

wire cond_74 = ~(protected_mode && glob_param_1[15:2] == 14'd0);

wire cond_75 = rd_cmd == `CMD_POP_seg && rd_cmdex == `CMDEX_POP_seg_STEP_1;

wire cond_76 = { rd_cmd[6:2], 2'd0 } == `CMD_BTx;

wire cond_77 = rd_mutex_busy_modregrm_rm || (rd_cmdex == `CMDEX_BTx_modregrm && rd_mutex_busy_modregrm_reg);

wire cond_78 = rd_mutex_busy_memory || (rd_cmdex == `CMDEX_BTx_modregrm && rd_mutex_busy_modregrm_reg);

wire cond_79 = rd_cmd == `CMD_IRET && rd_cmdex <= `CMDEX_IRET_real_v86_STEP_2;

wire cond_80 = rd_cmdex >`CMDEX_IRET_real_v86_STEP_0;

wire cond_81 = rd_cmdex == `CMDEX_IRET_real_v86_STEP_0;

wire cond_82 = rd_cmdex == `CMDEX_IRET_real_v86_STEP_1;

wire cond_83 = rd_cmdex == `CMDEX_IRET_real_v86_STEP_2;

wire cond_84 = rd_mutex_busy_memory || (rd_mutex_busy_eflags && v8086_mode);

wire cond_85 = ~(v8086_mode) || iopl == 2'd3;

wire cond_86 = rd_cmd == `CMD_IRET && rd_cmdex == `CMDEX_IRET_protected_STEP_0;

wire cond_87 = rd_mutex_busy_memory || rd_mutex_busy_eflags;

wire cond_88 = rd_cmd == `CMD_IRET && rd_cmdex == `CMDEX_IRET_task_switch_STEP_0;

wire cond_89 = rd_cmd == `CMD_IRET && rd_cmdex == `CMDEX_IRET_task_switch_STEP_1;

wire cond_90 = ~(rd_descriptor_not_in_limits);

wire cond_91 = rd_cmd == `CMD_IRET && rd_cmdex >= `CMDEX_IRET_protected_STEP_1 && rd_cmdex <= `CMDEX_IRET_protected_STEP_3;

wire cond_92 = rd_cmdex == `CMDEX_IRET_protected_STEP_1;

wire cond_93 = rd_cmdex == `CMDEX_IRET_protected_STEP_2;

wire cond_94 = rd_cmdex == `CMDEX_IRET_protected_STEP_3;

wire cond_95 = rd_cmd == `CMD_IRET && rd_cmdex >= `CMDEX_IRET_protected_to_v86_STEP_0;

wire cond_96 = rd_cmdex == `CMDEX_IRET_protected_to_v86_STEP_0;

wire cond_97 = rd_cmd == `CMD_IRET_2 && rd_cmdex == `CMDEX_IRET_2_protected_outer_STEP_0;

wire cond_98 = rd_cmd == `CMD_IRET_2 && rd_cmdex >= `CMDEX_IRET_2_protected_outer_STEP_1 && rd_cmdex <= `CMDEX_IRET_2_protected_outer_STEP_3;

wire cond_99 = rd_cmdex == `CMDEX_IRET_2_protected_outer_STEP_1;

wire cond_100 = rd_cmdex == `CMDEX_IRET_2_protected_outer_STEP_2;

wire cond_101 = rd_cmdex == `CMDEX_IRET_2_protected_outer_STEP_3;

wire cond_102 = rd_cmd == `CMD_IRET_2 && rd_cmdex >= `CMDEX_IRET_2_protected_outer_STEP_6;

wire cond_103 = rd_cmd == `CMD_POP && rd_cmdex == `CMDEX_POP_implicit;

wire cond_104 = rd_mutex_busy_memory || rd_mutex_busy_esp;

wire cond_105 = rd_cmd == `CMD_POP && rd_cmdex == `CMDEX_POP_modregrm_STEP_0;

wire cond_106 = rd_cmd == `CMD_POP && rd_cmdex == `CMDEX_POP_modregrm_STEP_1;

wire cond_107 = rd_cmd == `CMD_IDIV || rd_cmd == `CMD_DIV;

wire cond_108 = rd_mutex_busy_eax || (rd_decoder[0] && rd_mutex_busy_edx) || rd_mutex_busy_modregrm_rm;

wire cond_109 = rd_mutex_busy_eax || (rd_decoder[0] && rd_mutex_busy_edx) || rd_mutex_busy_memory;

wire cond_110 = rd_cmd == `CMD_Shift && rd_cmdex != `CMDEX_Shift_implicit;

wire cond_111 = rd_cmd == `CMD_Shift && rd_cmdex == `CMDEX_Shift_implicit;

wire cond_112 = rd_mutex_busy_modregrm_rm || rd_mutex_busy_ecx;

wire cond_113 = rd_mutex_busy_memory || rd_mutex_busy_ecx;

wire cond_114 = rd_cmd == `CMD_CMPS && rd_cmdex == `CMDEX_CMPS_FIRST;

wire cond_115 = rd_cmd == `CMD_CMPS && rd_cmdex == `CMDEX_CMPS_LAST;

wire cond_116 = rd_cmd == `CMD_control_reg && rd_cmdex == `CMDEX_control_reg_SMSW_STEP_0;

wire cond_117 = rd_cmd == `CMD_control_reg && rd_cmdex == `CMDEX_control_reg_LMSW_STEP_0;

wire cond_118 = cpl == 2'd0;

wire cond_119 = rd_cmd == `CMD_control_reg && rd_cmdex == `CMDEX_control_reg_MOV_load_STEP_0;

wire cond_120 = rd_cmd == `CMD_control_reg && rd_cmdex == `CMDEX_control_reg_MOV_store_STEP_0;

wire cond_121 = (rd_cmd == `CMD_LGDT || rd_cmd == `CMD_LIDT) && (rd_cmdex == `CMDEX_LGDT_LIDT_STEP_1 || rd_cmdex == `CMDEX_LGDT_LIDT_STEP_2);

wire cond_122 = rd_cmdex == `CMDEX_LGDT_LIDT_STEP_1;

wire cond_123 = rd_cmdex == `CMDEX_LGDT_LIDT_STEP_2;

wire cond_124 = rd_cmd == `CMD_PUSHA;

wire cond_125 = (rd_cmdex == `CMDEX_PUSHA_STEP_0 && rd_mutex_busy_eax) || (rd_cmdex == `CMDEX_PUSHA_STEP_1 && rd_mutex_busy_ecx) || (rd_cmdex == `CMDEX_PUSHA_STEP_2 && rd_mutex_busy_edx);

wire cond_126 = rd_cmd == `CMD_SETcc;

wire cond_127 = rd_cmd == `CMD_CMPXCHG;

wire cond_128 = rd_cmd == `CMD_ENTER && rd_cmdex == `CMDEX_ENTER_FIRST;

wire cond_129 = rd_mutex_busy_ebp;

wire cond_130 = rd_cmd == `CMD_ENTER && rd_cmdex == `CMDEX_ENTER_LAST;

wire cond_131 = rd_cmd == `CMD_ENTER && rd_cmdex == `CMDEX_ENTER_PUSH;

wire cond_132 = rd_cmd == `CMD_ENTER && rd_cmdex == `CMDEX_ENTER_LOOP;

wire cond_133 = rd_cmd == `CMD_IMUL && rd_cmdex == `CMDEX_IMUL_modregrm_imm;

wire cond_134 = rd_decoder[1:0] == 2'b11;

wire cond_135 = rd_cmd == `CMD_IMUL && rd_cmdex == `CMDEX_IMUL_modregrm;

wire cond_136 = rd_imul_modregrm_mutex_busy || rd_mutex_busy_modregrm_rm;

wire cond_137 = rd_imul_modregrm_mutex_busy || rd_mutex_busy_memory;

wire cond_138 = rd_cmd == `CMD_LEAVE;

wire cond_139 = { rd_cmd[6:1], 1'd0 } == `CMD_SHxD && rd_cmdex != `CMDEX_SHxD_implicit;

wire cond_140 = { rd_cmd[6:1], 1'd0 } == `CMD_SHxD && rd_cmdex == `CMDEX_SHxD_implicit;

wire cond_141 = rd_mutex_busy_modregrm_rm || rd_mutex_busy_ecx || rd_mutex_busy_modregrm_reg;

wire cond_142 = rd_mutex_busy_memory || rd_mutex_busy_ecx || rd_mutex_busy_modregrm_reg;

wire cond_143 = { rd_cmd[6:3], 3'd0 } == `CMD_Arith && rd_cmdex == `CMDEX_Arith_modregrm;

wire cond_144 = rd_decoder[5:3] != 3'b111;

wire cond_145 = rd_decoder[5:3] != 3'b111 && rd_arith_modregrm_to_rm;

wire cond_146 = rd_decoder[5:3] != 3'b111 && rd_arith_modregrm_to_reg;

wire cond_147 = { rd_cmd[6:3], 3'd0 } == `CMD_Arith && rd_cmdex == `CMDEX_Arith_modregrm_imm;

wire cond_148 = rd_decoder[13:11] != 3'b111;

wire cond_149 = { rd_cmd[6:3], 3'd0 } == `CMD_Arith && rd_cmdex == `CMDEX_Arith_immediate;

wire cond_150 = rd_cmd == `CMD_MUL;

wire cond_151 = rd_mutex_busy_eax || rd_mutex_busy_modregrm_rm;

wire cond_152 = rd_mutex_busy_eax || rd_mutex_busy_memory;

wire cond_153 = rd_cmd == `CMD_LOOP;

wire cond_154 = rd_cmd == `CMD_TEST && rd_cmdex == `CMDEX_TEST_modregrm;

wire cond_155 = rd_cmd == `CMD_TEST && rd_cmdex == `CMDEX_TEST_modregrm_imm;

wire cond_156 = rd_cmd == `CMD_TEST && rd_cmdex == `CMDEX_TEST_immediate;

wire cond_157 = rd_cmd == `CMD_RET_far && rd_cmdex == `CMDEX_RET_far_outer_STEP_3;

wire cond_158 = rd_cmd == `CMD_RET_far && rd_cmdex == `CMDEX_RET_far_STEP_1;

wire cond_159 = real_mode || v8086_mode;

wire cond_160 = rd_cmd == `CMD_RET_far && rd_cmdex == `CMDEX_RET_far_STEP_2;

wire cond_161 = rd_cmd == `CMD_RET_far && rd_cmdex == `CMDEX_RET_far_outer_STEP_4;

wire cond_162 = rd_cmd == `CMD_LODS;

wire cond_163 = rd_cmd == `CMD_XCHG && rd_cmdex == `CMDEX_XCHG_implicit;

wire cond_164 = rd_mutex_busy_implicit_reg || rd_mutex_busy_eax;

wire cond_165 = rd_cmd == `CMD_XCHG && rd_cmdex == `CMDEX_XCHG_modregrm;

wire cond_166 = rd_cmd == `CMD_XCHG && rd_cmdex == `CMDEX_XCHG_modregrm_LAST;

wire cond_167 = rd_cmd == `CMD_PUSH && (rd_cmdex == `CMDEX_PUSH_immediate || rd_cmdex == `CMDEX_PUSH_immediate_se);

wire cond_168 = rd_cmd == `CMD_PUSH && rd_cmdex == `CMDEX_PUSH_implicit;

wire cond_169 = rd_cmd == `CMD_PUSH && rd_cmdex == `CMDEX_PUSH_modregrm;

wire cond_170 = rd_cmd == `CMD_INT_INTO && rd_cmdex == `CMDEX_INT_INTO_INTO_STEP_0;

wire cond_171 = rd_mutex_busy_eflags;

wire cond_172 = rd_cmd == `CMD_CPUID;

wire cond_173 = rd_cmd == `CMD_IN && rd_cmdex != `CMDEX_IN_idle;

wire cond_174 = rd_in_condition;

wire cond_175 = ~(io_allow_check_needed) || rd_cmdex == `CMDEX_IN_protected;

wire cond_176 = ~(rd_io_ready);

wire cond_177 = rd_cmd == `CMD_NOT;

wire cond_178 = (rd_cmd == `CMD_LAR || rd_cmd == `CMD_LSL || rd_cmd == `CMD_VERR || rd_cmd == `CMD_VERW) && rd_cmdex == `CMDEX_LAR_LSL_VERR_VERW_STEP_1;

wire cond_179 = (rd_cmd == `CMD_LAR || rd_cmd == `CMD_LSL || rd_cmd == `CMD_VERR || rd_cmd == `CMD_VERW) && rd_cmdex == `CMDEX_LAR_LSL_VERR_VERW_STEP_2;

wire cond_180 = ~(glob_param_1[15:2] == 14'd0) && ~(rd_descriptor_not_in_limits);

wire cond_181 = (rd_cmd == `CMD_LAR || rd_cmd == `CMD_LSL) && rd_cmdex == `CMDEX_LAR_LSL_VERR_VERW_STEP_LAST;

wire cond_182 = rd_cmd == `CMD_LAR;

wire cond_183 = exe_mutex[`MUTEX_ACTIVE_BIT];

wire cond_184 = glob_param_2[1:0] == 2'd0 && ((glob_param_2[2] == 1'd0 && rd_cmd == `CMD_LAR) || (glob_param_2[3] == 1'd0 && rd_cmd == `CMD_LSL));

wire cond_185 = (rd_cmd == `CMD_VERR || rd_cmd == `CMD_VERW) && rd_cmdex == `CMDEX_LAR_LSL_VERR_VERW_STEP_LAST;

wire cond_186 = glob_param_2[1:0] == 2'd0 && ((glob_param_2[4] == 1'd0 && rd_cmd == `CMD_VERR) || (glob_param_2[5] == 1'd0 && rd_cmd == `CMD_VERW));

wire cond_187 =  (rd_cmd == `CMD_int_2  && rd_cmdex == `CMDEX_int_2_int_trap_gate_more_STEP_0) || (rd_cmd == `CMD_CALL_2 && rd_cmdex == `CMDEX_CALL_2_call_gate_more_STEP_0) ;

wire cond_188 = rd_ss_esp_from_tss_fault;

wire cond_189 =  (rd_cmd == `CMD_int_2 && rd_cmdex == `CMDEX_int_2_int_trap_gate_more_STEP_1) || (rd_cmd == `CMD_CALL_2 && rd_cmdex == `CMDEX_CALL_2_call_gate_more_STEP_1) ;

wire cond_190 =  (rd_cmd == `CMD_int_2 && rd_cmdex == `CMDEX_int_2_int_trap_gate_more_STEP_2) || (rd_cmd == `CMD_CALL_2 && rd_cmdex == `CMDEX_CALL_2_call_gate_more_STEP_2) ;

wire cond_191 = rd_cmd == `CMD_STOS;

wire cond_192 = rd_mutex_busy_eax || (rd_mutex_busy_ecx && rd_prefix_group_1_rep != 2'd0);

wire cond_193 = rd_cmd == `CMD_INS && (rd_cmdex == `CMDEX_INS_real_1 || rd_cmdex == `CMDEX_INS_protected_1);

wire cond_194 = rd_mutex_busy_ecx && rd_prefix_group_1_rep != 2'd0;

wire cond_195 = ~(rd_string_ignore) && ~(io_allow_check_needed && rd_cmdex == `CMDEX_INS_real_1);

wire cond_196 = rd_cmd == `CMD_INS && (rd_cmdex == `CMDEX_INS_real_2 || rd_cmdex == `CMDEX_INS_protected_2);

wire cond_197 = rd_mutex_busy_edx || (rd_mutex_busy_ecx && rd_prefix_group_1_rep != 2'd0);

wire cond_198 = rd_cmd == `CMD_OUTS;

wire cond_199 = ~(rd_string_ignore) && ~(io_allow_check_needed && rd_cmdex == `CMDEX_OUTS_first);

wire cond_200 = rd_cmd == `CMD_PUSHF;

wire cond_201 = rd_cmd == `CMD_JMP && rd_cmdex == `CMDEX_JMP_Jv_STEP_0;

wire cond_202 = rd_cmd == `CMD_JMP  && rd_cmdex == `CMDEX_JMP_Ap_STEP_1;

wire cond_203 = rd_cmd == `CMD_JMP_2 && rd_cmdex == `CMDEX_JMP_2_call_gate_STEP_0;

wire cond_204 = rd_cmd == `CMD_JMP_2 && rd_cmdex == `CMDEX_JMP_2_call_gate_STEP_1;

wire cond_205 = rd_cmd == `CMD_JMP  && rd_cmdex == `CMDEX_JMP_Ev_STEP_0;

wire cond_206 = rd_cmd == `CMD_JMP  && (rd_cmdex == `CMDEX_JMP_Ep_STEP_0  || rd_cmdex == `CMDEX_JMP_Ep_STEP_1);

wire cond_207 = rd_cmdex == `CMDEX_JMP_Ep_STEP_1;

wire cond_208 = rd_cmd == `CMD_JMP  && rd_cmdex == `CMDEX_JMP_Ap_STEP_0;

wire cond_209 = rd_cmd == `CMD_JMP && rd_cmdex == `CMDEX_JMP_protected_STEP_0;

wire cond_210 = rd_cmd == `CMD_JMP && rd_cmdex == `CMDEX_JMP_task_gate_STEP_0;

wire cond_211 = rd_cmd == `CMD_JMP && rd_cmdex == `CMDEX_JMP_task_gate_STEP_1;

wire cond_212 = rd_cmd == `CMD_OUT;

wire cond_213 = rd_cmd == `CMD_MOV && rd_cmdex == `CMDEX_MOV_memoffset;

wire cond_214 = ~(rd_decoder[1]);

wire cond_215 = rd_mutex_busy_eax || ~(write_virtual_check_ready);

wire cond_216 = rd_cmd == `CMD_MOV && rd_cmdex == `CMDEX_MOV_modregrm && rd_decoder[1];

wire cond_217 = rd_cmd == `CMD_MOV && rd_cmdex == `CMDEX_MOV_modregrm && ~(rd_decoder[1]);

wire cond_218 = rd_mutex_busy_modregrm_reg;

wire cond_219 = rd_cmd == `CMD_MOV && rd_cmdex == `CMDEX_MOV_modregrm_imm;

wire cond_220 = rd_cmd == `CMD_MOV && rd_cmdex == `CMDEX_MOV_immediate;

wire cond_221 = rd_cmd == `CMD_LAHF || rd_cmd == `CMD_CBW || rd_cmd == `CMD_CWD;

wire cond_222 = rd_cmd == `CMD_POPF && rd_cmdex == `CMDEX_POPF_STEP_0;

wire cond_223 = rd_cmd == `CMD_CLI || rd_cmd == `CMD_STI;

wire cond_224 = rd_cmd == `CMD_BOUND && rd_cmdex == `CMDEX_BOUND_STEP_FIRST;

wire cond_225 = rd_cmd == `CMD_BOUND && rd_cmdex == `CMDEX_BOUND_STEP_LAST;

wire cond_226 = rd_cmd == `CMD_SALC && rd_cmdex == `CMDEX_SALC_STEP_0;

wire cond_227 = rd_cmd == `CMD_task_switch && rd_cmdex == `CMDEX_task_switch_STEP_6;

wire cond_228 = glob_param_1[`TASK_SWITCH_SOURCE_BITS] == `TASK_SWITCH_FROM_JUMP || glob_param_1[`TASK_SWITCH_SOURCE_BITS] == `TASK_SWITCH_FROM_IRET;

wire cond_229 = rd_cmd == `CMD_task_switch && rd_cmdex == `CMDEX_task_switch_STEP_9;

wire cond_230 = rd_cmd == `CMD_task_switch_2 && rd_cmdex <= `CMDEX_task_switch_2_STEP_7;

wire cond_231 = rd_cmd == `CMD_task_switch_2 && rd_cmdex == `CMDEX_task_switch_2_STEP_13;

wire cond_232 = rd_cmd == `CMD_task_switch && rd_cmdex >= `CMDEX_task_switch_STEP_12 && rd_cmdex <= `CMDEX_task_switch_STEP_14;

wire cond_233 = rd_cmdex == `CMDEX_task_switch_STEP_12 && glob_descriptor[`DESC_BITS_TYPE] <= 4'd3;

wire cond_234 = rd_cmdex == `CMDEX_task_switch_STEP_12 && glob_descriptor[`DESC_BITS_TYPE] >  4'd3;

wire cond_235 = rd_cmdex == `CMDEX_task_switch_STEP_13 || rd_cmdex == `CMDEX_task_switch_STEP_14;

wire cond_236 = rd_cmdex != `CMDEX_task_switch_STEP_12 || (glob_descriptor[`DESC_BITS_TYPE] > 4'd3 && cr0_pg);

wire cond_237 = rd_cmd == `CMD_task_switch_3;

wire cond_238 = rd_cmdex <= `CMDEX_task_switch_3_STEP_12 || glob_descriptor[`DESC_BITS_TYPE] > 4'd3;

wire cond_239 = rd_cmd == `CMD_task_switch_4 && rd_cmdex == `CMDEX_task_switch_4_STEP_0;

wire cond_240 = glob_param_1[`TASK_SWITCH_SOURCE_BITS] != `TASK_SWITCH_FROM_IRET;

wire cond_241 = rd_cmd == `CMD_task_switch_4 && rd_cmdex == `CMDEX_task_switch_4_STEP_2;

wire cond_242 = glob_param_1[`SELECTOR_BIT_TI] == 1'b0 && glob_param_1[15:2] != 14'd0 && ~(rd_descriptor_not_in_limits);

wire cond_243 = rd_cmd == `CMD_task_switch_4 && rd_cmdex >= `CMDEX_task_switch_4_STEP_3 && rd_cmdex <= `CMDEX_task_switch_4_STEP_8;

wire cond_244 = glob_param_1[15:2] != 14'd0 && ~(rd_descriptor_not_in_limits);

wire cond_245 = rd_cmd == `CMD_LEA;

wire cond_246 = (rd_cmd == `CMD_SGDT || rd_cmd == `CMD_SIDT);

wire cond_247 = rd_cmdex == `CMDEX_SGDT_SIDT_STEP_1;

wire cond_248 = rd_cmdex == `CMDEX_SGDT_SIDT_STEP_2;

wire cond_249 = rd_cmd == `CMD_MOVS;

wire cond_250 = rd_cmd == `CMD_MOVSX || rd_cmd == `CMD_MOVZX;

wire cond_251 = rd_cmd == `CMD_POPA;

wire cond_252 = rd_cmdex[2:0] > 3'd0;

wire cond_253 = rd_cmdex[2:0] == 3'd7;

wire cond_254 = rd_cmd == `CMD_debug_reg && rd_cmdex == `CMDEX_debug_reg_MOV_store_STEP_0;

wire cond_255 = rd_cmd == `CMD_debug_reg && rd_cmdex == `CMDEX_debug_reg_MOV_load_STEP_0;

wire cond_256 = rd_cmd == `CMD_XLAT;

wire cond_257 = rd_cmd == `CMD_AAA || rd_cmd == `CMD_AAS || rd_cmd == `CMD_DAA || rd_cmd == `CMD_DAS;

wire cond_258 = { rd_cmd[6:1], 1'd0 } == `CMD_BSx;

//======================================================== saves

//======================================================== always

//======================================================== sets

assign rd_glob_param_5_set =

    (cond_22 && ~cond_16)? (`TRUE) :

    (cond_98 && cond_100)? (`TRUE) :

    (cond_190 && ~cond_16 && cond_90)? (`TRUE) :

    (cond_190 && ~cond_16 && ~cond_90)? (`TRUE) :

    1'd0;

assign rd_glob_param_2_set =

    (cond_43)? (`TRUE) :

    (cond_48 && ~cond_49 && cond_50)? (`TRUE) :

    (cond_53 && ~cond_50)? (`TRUE) :

    (cond_64)? (`TRUE) :

    (cond_79 && cond_81)? (`TRUE) :

    (cond_89 && ~cond_16 && cond_90)? (`TRUE) :

    (cond_89 && ~cond_16 && ~cond_90)? (`TRUE) :

    (cond_91 && cond_94)? (`TRUE) :

    (cond_98 && cond_101)? (`TRUE) :

    (cond_158 && ~cond_9 && cond_159)? (`TRUE) :

    (cond_160 && ~cond_9 && cond_72)? (`TRUE) :

    (cond_179 && cond_180 && ~cond_9)? (`TRUE) :

    (cond_179 && ~cond_180)? (`TRUE) :

    (cond_203 && ~cond_16)? (`TRUE) :

    (cond_227 && ~cond_16 && cond_228)? (`TRUE) :

    (cond_241 && ~cond_16 && cond_242)? (`TRUE) :

    (cond_241 && ~cond_16 && ~cond_242)? (`TRUE) :

    (cond_243 && ~cond_16 && cond_70)? (`TRUE) :

    (cond_243 && ~cond_16 && ~cond_70 && cond_244)? (`TRUE) :

    (cond_243 && ~cond_16 && ~cond_70 && ~cond_244)? (`TRUE) :

    1'd0;

assign rd_req_all =

    (cond_251 && cond_253)? (`TRUE) :

    1'd0;

assign rd_req_esp =

    (cond_27)? (`TRUE) :

    (cond_43)? (`TRUE) :

    (cond_75)? (`TRUE) :

    (cond_103)? (`TRUE) :

    (cond_105)? (`TRUE) :

    (cond_124)? (`TRUE) :

    (cond_128)? (`TRUE) :

    (cond_130)? (`TRUE) :

    (cond_131)? (`TRUE) :

    (cond_132)? (`TRUE) :

    (cond_138 && ~cond_9)? (`TRUE) :

    (cond_167)? (`TRUE) :

    (cond_168)? (`TRUE) :

    (cond_169)? (`TRUE) :

    (cond_200)? (`TRUE) :

    (cond_222)? (`TRUE) :

    1'd0;

assign rd_src_is_cmdex =

    (cond_124)? (`TRUE) :

    (cond_128)? (`TRUE) :

    (cond_230)? (`TRUE) :

    1'd0;

assign rd_req_implicit_reg =

    (cond_41)? (`TRUE) :

    (cond_47)? (`TRUE) :

    (cond_103)? (`TRUE) :

    (cond_163)? (`TRUE) :

    (cond_220)? (`TRUE) :

    1'd0;

assign rd_req_reg =

    (cond_6)? (`TRUE) :

    (cond_54)? (`TRUE) :

    (cond_133)? (`TRUE) :

    (cond_135)? (          rd_decoder[3]) :

    (cond_143 && cond_1 && cond_144)? ( rd_arith_modregrm_to_reg) :

    (cond_143 && cond_3 && cond_146)? (`TRUE) :

    (cond_166)? (`TRUE) :

    (cond_181 && ~cond_183 && cond_184)? (`TRUE) :

    (cond_216)? (`TRUE) :

    (cond_245)? (`TRUE) :

    (cond_258)? (`TRUE) :

    1'd0;

assign rd_dst_is_0 =

    (cond_30)? (`TRUE) :

    1'd0;

assign address_esi =

    (cond_114)? (`TRUE) :

    (cond_162)? (`TRUE) :

    (cond_198)? (`TRUE) :

    (cond_249)? (`TRUE) :

    1'd0;

assign address_stack_save =

    (cond_22 && cond_26)? (`TRUE) :

    (cond_91 && cond_92)? (`TRUE) :

    (cond_95 && cond_96)? (`TRUE) :

    (cond_98 && cond_99)? (`TRUE) :

    (cond_158)? (`TRUE) :

    (cond_157)? (`TRUE) :

    1'd0;

assign read_rmw_virtual =

    (cond_0 && cond_3 && ~cond_4)? (`TRUE) :

    (cond_30 && cond_3 && ~cond_9)? (`TRUE) :

    (cond_40 && cond_3 && ~cond_9)? (`TRUE) :

    (cond_44 && cond_3 && ~cond_46)? (`TRUE) :

    (cond_76 && cond_3 && ~cond_78)? (    rd_cmd[1:0] != 2'd0) :

    (cond_110 && cond_3 && ~cond_9)? (`TRUE) :

    (cond_111 && cond_3 && ~cond_113)? (`TRUE) :

    (cond_127 && cond_3 && ~cond_4)? (`TRUE) :

    (cond_130)? (`TRUE) :

    (cond_139 && cond_3 && ~cond_46)? (`TRUE) :

    (cond_140 && cond_3 && ~cond_142)? (`TRUE) :

    (cond_143 && cond_3 && ~cond_46 && cond_145)? (`TRUE) :

    (cond_147 && cond_3 && ~cond_9 && cond_148)? (`TRUE) :

    (cond_165 && cond_3 && ~cond_4)? (`TRUE) :

    (cond_177 && cond_3 && ~cond_9)? (`TRUE) :

    (cond_193 && ~cond_194 && cond_195)? (`TRUE) :

    1'd0;

assign address_stack_pop_speedup =

    (cond_79 && cond_80)? (`TRUE) :

    (cond_160)? (  real_mode || v8086_mode) :

    (cond_251 && cond_252)? (`TRUE) :

    1'd0;

assign io_read =

    (cond_173 && ~cond_174 && cond_175)? (`TRUE) :

    (cond_196 && ~cond_197 && cond_195)? (`TRUE) :

    1'd0;

assign address_leave =

    (cond_138)? (`TRUE) :

    1'd0;

assign rd_dst_is_eax =

    (cond_37 && ~cond_38 && cond_39)? (`TRUE) :

    (cond_67)? (`TRUE) :

    (cond_149)? (`TRUE) :

    (cond_156)? (`TRUE) :

    (cond_213 && cond_214)? (`TRUE) :

    (cond_256)? (`TRUE) :

    (cond_257)? (`TRUE) :

    1'd0;

assign rd_src_is_imm =

    (cond_10)? (`TRUE) :

    (cond_13)? (`TRUE) :

    (cond_67)? (`TRUE) :

    (cond_149)? (`TRUE) :

    (cond_156)? (`TRUE) :

    (cond_167)? (`TRUE) :

    (cond_208)? (`TRUE) :

    (cond_220)? (`TRUE) :

    1'd0;

assign address_bits_transform =

    (cond_76)? ( rd_cmdex == `CMDEX_BTx_modregrm) :

    1'd0;

assign rd_src_is_1 =

    (cond_40)? (`TRUE) :

    (cond_41)? (`TRUE) :

    (cond_110)? (            rd_cmdex == `CMDEX_Shift_modregrm) :

    1'd0;

assign read_system_dword =

    (cond_189)? ( rd_ss_esp_from_tss_386) :

    (cond_232 && cond_236 && ~cond_9)? ( glob_descriptor[`DESC_BITS_TYPE] >  4'd3) :

    (cond_237 && cond_238)? ( glob_descriptor[`DESC_BITS_TYPE] >  4'd3 && rd_cmdex <= `CMDEX_task_switch_3_STEP_7) :

    1'd0;

assign address_stack_for_ret_first =

    (cond_158)? (`TRUE) :

    1'd0;

assign rd_req_eax =

    (cond_67)? (`TRUE) :

    (cond_107)? (`TRUE) :

    (cond_127)? (`TRUE) :

    (cond_135)? (          ~(rd_decoder[3])) :

    (cond_149 && cond_144)? (`TRUE) :

    (cond_150)? (`TRUE) :

    (cond_162 && ~cond_38 && cond_39)? (`TRUE) :

    (cond_163)? (`TRUE) :

    (cond_172)? (`TRUE) :

    (cond_213 && cond_214)? (`TRUE) :

    (cond_221)? ( rd_cmd != `CMD_CWD) :

    (cond_226)? (`TRUE) :

    (cond_256)? (`TRUE) :