1 |
2 |
alfik |
//======================================================== conditions
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2 |
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wire cond_0 = state == STATE_IDLE;
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3 |
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wire cond_1 = tlbflushsingle_do;
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4 |
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wire cond_2 = tlbflushall_do || tlbflushall_do_waiting;
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5 |
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wire cond_3 = ~(wr_reset) && tlbwrite_do && ~(write_ac) && cr0_am && acflag && tlbwrite_cpl == 2'd3 &&
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6 |
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( (tlbwrite_length_full == 3'd2 && tlbwrite_address[0] != 1'b0) || (tlbwrite_length_full == 3'd4 && tlbwrite_address[1:0] != 2'b00) )
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7 |
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;
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8 |
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wire cond_4 = ~(wr_reset) && tlbwrite_do && ~(write_pf) && ~(write_ac);
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9 |
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wire cond_5 = ~(exe_reset) && tlbcheck_do && ~(tlbcheck_done) && ~(check_pf);
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10 |
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wire cond_6 = ~(rd_reset) && tlbread_do && ~(read_ac) && cr0_am && acflag && tlbread_cpl == 2'd3 &&
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11 |
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( (tlbread_length_full == 4'd2 && tlbread_address[0] != 1'b0) || (tlbread_length_full == 4'd4 && tlbread_address[1:0] != 2'b00))
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12 |
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;
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13 |
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wire cond_7 = ~(rd_reset) && tlbread_do && ~(read_pf) && ~(read_ac);
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14 |
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wire cond_8 = ~(pr_reset) && tlbcoderequest_do && ~(code_pf) && ~(tlbcode_do);
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15 |
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wire cond_9 = state == STATE_WRITE_DOUBLE;
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16 |
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wire cond_10 = write_double_state == WRITE_DOUBLE_CHECK;
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17 |
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wire cond_11 = state == STATE_WRITE_WAIT;
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18 |
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wire cond_12 = dcachewrite_done;
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19 |
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wire cond_13 = state == STATE_READ_WAIT;
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20 |
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wire cond_14 = dcacheread_done;
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21 |
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wire cond_15 = state == STATE_READ_CHECK;
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22 |
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wire cond_16 = cr0_pg;
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23 |
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wire cond_17 = ~(cr0_pg) || translate_valid;
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24 |
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wire cond_18 = cr0_pg && fault;
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25 |
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wire cond_19 = state == STATE_WRITE_CHECK;
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26 |
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wire cond_20 = translate_valid && write_double_state != WRITE_DOUBLE_NONE;
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27 |
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wire cond_21 = state == STATE_CHECK_CHECK;
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28 |
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wire cond_22 = state == STATE_CODE_CHECK;
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29 |
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wire cond_23 = pr_reset || pr_reset_waiting;
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30 |
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wire cond_24 = state == STATE_LOAD_PDE;
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31 |
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wire cond_25 = dcacheread_data[0] == `FALSE;
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32 |
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wire cond_26 = current_type == TYPE_CODE && ~(pr_reset) && ~(pr_reset_waiting);
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33 |
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wire cond_27 = current_type == TYPE_CHECK;
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34 |
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wire cond_28 = current_type == TYPE_WRITE;
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35 |
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wire cond_29 = current_type == TYPE_READ;
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36 |
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wire cond_30 = state == STATE_LOAD_PTE_START;
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37 |
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wire cond_31 = state == STATE_RETRY;
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38 |
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wire cond_32 = state == STATE_LOAD_PTE;
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39 |
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wire cond_33 = dcacheread_data[0] == `FALSE || fault_before_pte;
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40 |
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wire cond_34 = ((current_type == TYPE_READ && ~(pipeline_after_read_empty)) || (current_type == TYPE_CODE && (~(pipeline_after_prefetch_empty) || pr_reset_waiting))) &&
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41 |
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(pde[5] == `FALSE || dcacheread_data[5] == `FALSE || (dcacheread_data[6] == `FALSE && rw));
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42 |
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wire cond_35 = state == STATE_LOAD_PTE_END;
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43 |
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wire cond_36 = pde[5] == `FALSE;
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44 |
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wire cond_37 = pte[5] == `FALSE || (pte[6] == `FALSE && rw);
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45 |
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wire cond_38 = current_type == TYPE_WRITE && write_double_state != WRITE_DOUBLE_NONE;
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46 |
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wire cond_39 = state == STATE_READ_WAIT_START;
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47 |
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wire cond_40 = state == STATE_SAVE_PDE;
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48 |
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wire cond_41 = state == STATE_SAVE_PTE_START;
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49 |
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wire cond_42 = state == STATE_WRITE_WAIT_START;
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50 |
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wire cond_43 = state == STATE_SAVE_PTE;
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51 |
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//======================================================== saves
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52 |
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wire [1:0] current_type_to_reg =
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53 |
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(cond_15 && ~cond_17)? ( TYPE_READ) :
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54 |
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(cond_19 && ~cond_17)? ( TYPE_WRITE) :
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55 |
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(cond_21 && ~cond_17)? ( TYPE_CHECK) :
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56 |
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(cond_22 && ~cond_23 && ~cond_17)? ( TYPE_CODE) :
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57 |
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current_type;
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58 |
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wire read_pf_to_reg =
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59 |
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(cond_0)? ( `FALSE) :
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60 |
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(cond_15 && cond_17 && cond_18)? ( `TRUE) :
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61 |
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(cond_24 && cond_14 && cond_25 && ~cond_26 && ~cond_27 && ~cond_28 && cond_29)? ( `TRUE) :
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62 |
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(cond_32 && cond_14 && cond_33 && ~cond_26 && ~cond_27 && ~cond_28 && cond_29)? ( `TRUE) :
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63 |
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read_pf;
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64 |
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wire [31:0] pde_to_reg =
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65 |
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(cond_24 && cond_14)? ( dcacheread_data[31:0]) :
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66 |
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pde;
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67 |
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wire write_pf_to_reg =
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68 |
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(cond_0)? ( `FALSE) :
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69 |
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(cond_19 && cond_17 && cond_18)? ( `TRUE) :
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70 |
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(cond_24 && cond_14 && cond_25 && ~cond_26 && ~cond_27 && cond_28)? ( `TRUE) :
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71 |
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(cond_32 && cond_14 && cond_33 && ~cond_26 && ~cond_27 && cond_28)? ( `TRUE) :
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72 |
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write_pf;
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73 |
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wire [4:0] state_to_reg =
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74 |
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(cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && cond_4)? ( STATE_WRITE_CHECK) :
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75 |
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(cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && ~cond_4 && cond_5)? ( STATE_CHECK_CHECK) :
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76 |
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(cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && ~cond_4 && ~cond_5 && ~cond_6 && cond_7)? ( STATE_READ_CHECK) :
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77 |
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(cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && ~cond_4 && ~cond_5 && ~cond_6 && ~cond_7 && cond_8)? ( STATE_CODE_CHECK) :
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78 |
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(cond_9 && cond_10)? ( STATE_WRITE_CHECK) :
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79 |
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(cond_9 && ~cond_10)? ( STATE_WRITE_CHECK) :
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80 |
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(cond_11 && cond_12)? ( STATE_IDLE) :
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81 |
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(cond_13 && cond_14)? ( STATE_IDLE) :
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82 |
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(cond_15 && cond_17 && cond_18)? ( STATE_IDLE) :
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83 |
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(cond_15 && cond_17 && ~cond_18)? ( STATE_READ_WAIT) :
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84 |
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(cond_15 && ~cond_17)? ( STATE_LOAD_PDE) :
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85 |
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(cond_19 && cond_17 && cond_18)? ( STATE_IDLE) :
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86 |
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(cond_19 && cond_17 && ~cond_18 && cond_20)? ( STATE_WRITE_DOUBLE) :
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87 |
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(cond_19 && cond_17 && ~cond_18 && ~cond_20)? ( STATE_WRITE_WAIT) :
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88 |
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(cond_19 && ~cond_17)? ( STATE_LOAD_PDE) :
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89 |
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(cond_21 && cond_17)? ( STATE_IDLE) :
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90 |
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(cond_21 && ~cond_17)? ( STATE_LOAD_PDE) :
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91 |
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(cond_22 && cond_23)? ( STATE_IDLE) :
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92 |
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(cond_22 && ~cond_23 && cond_17)? ( STATE_IDLE) :
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93 |
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(cond_22 && ~cond_23 && ~cond_17)? ( STATE_LOAD_PDE) :
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94 |
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(cond_24 && cond_14 && cond_25)? ( STATE_IDLE) :
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95 |
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(cond_24 && cond_14 && ~cond_25)? ( STATE_LOAD_PTE_START) :
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96 |
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(cond_30)? ( STATE_LOAD_PTE) :
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97 |
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(cond_31)? ( STATE_IDLE) :
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98 |
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(cond_32 && cond_14 && cond_33)? ( STATE_IDLE) :
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99 |
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(cond_32 && cond_14 && ~cond_33 && cond_34)? ( STATE_RETRY) :
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100 |
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(cond_32 && cond_14 && ~cond_33 && ~cond_34)? ( STATE_LOAD_PTE_END) :
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101 |
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(cond_35 && cond_36)? ( STATE_SAVE_PDE) :
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102 |
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(cond_35 && ~cond_36 && cond_37)? ( STATE_SAVE_PTE) :
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103 |
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(cond_35 && ~cond_36 && ~cond_37 && cond_38)? ( STATE_WRITE_DOUBLE) :
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104 |
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(cond_35 && ~cond_36 && ~cond_37 && ~cond_38 && cond_28)? ( STATE_WRITE_WAIT) :
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105 |
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(cond_35 && ~cond_36 && ~cond_37 && ~cond_38 && ~cond_28 && cond_29)? ( STATE_READ_WAIT_START) :
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106 |
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(cond_35 && ~cond_36 && ~cond_37 && ~cond_38 && ~cond_28 && ~cond_29)? ( STATE_IDLE) :
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107 |
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(cond_39)? ( STATE_READ_WAIT) :
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108 |
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(cond_40 && cond_12 && cond_37)? ( STATE_SAVE_PTE_START) :
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109 |
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(cond_40 && cond_12 && ~cond_37 && cond_28)? ( STATE_WRITE_WAIT_START) :
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110 |
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(cond_40 && cond_12 && ~cond_37 && ~cond_28 && cond_29)? ( STATE_READ_WAIT) :
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111 |
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(cond_40 && cond_12 && ~cond_37 && ~cond_28 && ~cond_29)? ( STATE_IDLE) :
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112 |
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(cond_41)? ( STATE_SAVE_PTE) :
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113 |
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(cond_42 && cond_38)? ( STATE_WRITE_DOUBLE) :
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114 |
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(cond_42 && ~cond_38)? ( STATE_WRITE_WAIT) :
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115 |
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(cond_43 && cond_12 && cond_28)? ( STATE_WRITE_WAIT_START) :
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116 |
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(cond_43 && cond_12 && ~cond_28 && cond_29)? ( STATE_READ_WAIT) :
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117 |
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(cond_43 && cond_12 && ~cond_28 && ~cond_29)? ( STATE_IDLE) :
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118 |
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state;
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119 |
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wire [31:0] tlb_read_pf_cr2_to_reg =
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120 |
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(cond_15 && cond_17 && cond_18)? ( linear) :
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121 |
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(cond_24 && cond_14 && cond_25 && ~cond_26 && ~cond_27 && ~cond_28 && cond_29)? ( linear) :
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122 |
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(cond_32 && cond_14 && cond_33 && ~cond_26 && ~cond_27 && ~cond_28 && cond_29)? ( linear) :
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123 |
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tlb_read_pf_cr2;
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124 |
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wire [31:0] tlb_code_pf_cr2_to_reg =
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125 |
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(cond_22 && ~cond_23 && cond_17 && cond_18)? ( linear) :
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126 |
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(cond_24 && cond_14 && cond_25 && cond_26)? ( linear) :
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127 |
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(cond_32 && cond_14 && cond_33 && cond_26)? ( linear) :
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128 |
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tlb_code_pf_cr2;
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129 |
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wire check_pf_to_reg =
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130 |
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(cond_21 && cond_17 && cond_18)? ( `TRUE) :
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131 |
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(cond_24 && cond_14 && cond_25 && ~cond_26 && cond_27)? ( `TRUE) :
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132 |
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(cond_32 && cond_14 && cond_33 && ~cond_26 && cond_27)? ( `TRUE) :
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133 |
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check_pf;
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134 |
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wire su_to_reg =
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135 |
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(cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && cond_4)? ( tlbwrite_cpl == 2'd3) :
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136 |
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(cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && ~cond_4 && cond_5)? ( `FALSE) :
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137 |
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(cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && ~cond_4 && ~cond_5 && ~cond_6 && cond_7)? ( tlbread_cpl == 2'd3) :
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138 |
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(cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && ~cond_4 && ~cond_5 && ~cond_6 && ~cond_7 && cond_8)? ( tlbcoderequest_su) :
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139 |
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su;
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140 |
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wire [15:0] tlb_check_pf_error_code_to_reg =
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141 |
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(cond_21 && cond_17 && cond_18)? ({ 13'd0, su, rw, `TRUE }) :
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142 |
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(cond_24 && cond_14 && cond_25 && ~cond_26 && cond_27)? ({ 13'd0, su, rw, `FALSE }) :
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143 |
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(cond_32 && cond_14 && cond_33 && ~cond_26 && cond_27)? ({ 13'd0, su, rw, dcacheread_data[0] }) :
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144 |
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tlb_check_pf_error_code;
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145 |
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wire [15:0] tlb_write_pf_error_code_to_reg =
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146 |
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(cond_19 && cond_17 && cond_18)? ( { 13'd0, su, rw, `TRUE }) :
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147 |
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(cond_24 && cond_14 && cond_25 && ~cond_26 && ~cond_27 && cond_28)? ({ 13'd0, su, rw, `FALSE }) :
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148 |
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(cond_32 && cond_14 && cond_33 && ~cond_26 && ~cond_27 && cond_28)? ({ 13'd0, su, rw, dcacheread_data[0] }) :
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149 |
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tlb_write_pf_error_code;
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150 |
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wire [31:0] write_double_linear_to_reg =
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151 |
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(cond_9 && cond_10)? ( linear) :
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152 |
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write_double_linear;
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153 |
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wire tlbcode_cache_disable_to_reg =
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154 |
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(cond_22 && ~cond_23 && cond_17 && ~cond_18)? ( cr0_cd || translate_pcd || memtype_cache_disable) :
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155 |
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tlbcode_cache_disable;
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156 |
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wire [31:0] linear_to_reg =
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157 |
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(cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && cond_4)? ( tlbwrite_address) :
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158 |
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(cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && ~cond_4 && cond_5)? ( tlbcheck_address) :
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159 |
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(cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && ~cond_4 && ~cond_5 && ~cond_6 && cond_7)? ( tlbread_address) :
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160 |
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(cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && ~cond_4 && ~cond_5 && ~cond_6 && ~cond_7 && cond_8)? ( tlbcoderequest_address) :
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161 |
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(cond_9 && cond_10)? ( { linear[31:12], 12'd0 } + 32'h00001000) :
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162 |
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(cond_9 && ~cond_10)? ( write_double_linear) :
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163 |
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linear;
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164 |
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wire [15:0] tlb_code_pf_error_code_to_reg =
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165 |
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(cond_22 && ~cond_23 && cond_17 && cond_18)? ({ 13'd0, su, rw, `TRUE }) :
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166 |
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(cond_24 && cond_14 && cond_25 && cond_26)? ( { 13'd0, su, rw, `FALSE }) :
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167 |
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(cond_32 && cond_14 && cond_33 && cond_26)? ( { 13'd0, su, rw, dcacheread_data[0] }) :
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168 |
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tlb_code_pf_error_code;
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169 |
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wire tlbcode_do_to_reg =
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170 |
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(cond_0)? ( `FALSE) :
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171 |
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(cond_22 && ~cond_23 && cond_17 && ~cond_18)? ( `TRUE) :
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172 |
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tlbcode_do;
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173 |
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wire wp_to_reg =
|
174 |
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(cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && cond_4)? ( cr0_wp) :
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175 |
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(cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && ~cond_4 && cond_5)? ( cr0_wp) :
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176 |
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(cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && ~cond_4 && ~cond_5 && ~cond_6 && cond_7)? ( cr0_wp) :
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177 |
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(cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && ~cond_4 && ~cond_5 && ~cond_6 && ~cond_7 && cond_8)? ( cr0_wp) :
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178 |
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wp;
|
179 |
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wire tlbcheck_done_to_reg =
|
180 |
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(cond_0)? ( `FALSE) :
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181 |
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(cond_21 && cond_17 && ~cond_18)? ( `TRUE) :
|
182 |
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tlbcheck_done;
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183 |
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wire [31:0] tlb_write_pf_cr2_to_reg =
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184 |
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(cond_19 && cond_17 && cond_18)? ( linear) :
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185 |
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(cond_24 && cond_14 && cond_25 && ~cond_26 && ~cond_27 && cond_28)? ( linear) :
|
186 |
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(cond_32 && cond_14 && cond_33 && ~cond_26 && ~cond_27 && cond_28)? ( linear) :
|
187 |
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tlb_write_pf_cr2;
|
188 |
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wire read_ac_to_reg =
|
189 |
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(cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && ~cond_4 && ~cond_5 && cond_6)? ( `TRUE) :
|
190 |
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read_ac;
|
191 |
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wire [31:0] pte_to_reg =
|
192 |
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(cond_32 && cond_14)? ( dcacheread_data[31:0]) :
|
193 |
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pte;
|
194 |
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wire [31:0] tlb_check_pf_cr2_to_reg =
|
195 |
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(cond_21 && cond_17 && cond_18)? ( linear) :
|
196 |
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(cond_24 && cond_14 && cond_25 && ~cond_26 && cond_27)? ( linear) :
|
197 |
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(cond_32 && cond_14 && cond_33 && ~cond_26 && cond_27)? ( linear) :
|
198 |
|
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tlb_check_pf_cr2;
|
199 |
|
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wire [15:0] tlb_read_pf_error_code_to_reg =
|
200 |
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(cond_15 && cond_17 && cond_18)? ( { 13'd0, su, rw, `TRUE }) :
|
201 |
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(cond_24 && cond_14 && cond_25 && ~cond_26 && ~cond_27 && ~cond_28 && cond_29)? ( { 13'd0, su, rw, `FALSE }) :
|
202 |
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(cond_32 && cond_14 && cond_33 && ~cond_26 && ~cond_27 && ~cond_28 && cond_29)? ( { 13'd0, su, rw, dcacheread_data[0] }) :
|
203 |
|
|
tlb_read_pf_error_code;
|
204 |
|
|
wire [1:0] write_double_state_to_reg =
|
205 |
|
|
(cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && cond_4)? ( (cr0_pg && tlbwrite_length != tlbwrite_length_full && { 1'b0, tlbwrite_address[11:0] } + { 10'd0, tlbwrite_length_full } >= 13'h1000)? WRITE_DOUBLE_CHECK : WRITE_DOUBLE_NONE) :
|
206 |
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(cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && ~cond_4 && cond_5)? ( WRITE_DOUBLE_NONE) :
|
207 |
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(cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && ~cond_4 && ~cond_5 && ~cond_6 && cond_7)? ( WRITE_DOUBLE_NONE) :
|
208 |
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(cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && ~cond_4 && ~cond_5 && ~cond_6 && ~cond_7 && cond_8)? ( WRITE_DOUBLE_NONE) :
|
209 |
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(cond_9 && cond_10)? ( WRITE_DOUBLE_RESTART) :
|
210 |
|
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(cond_9 && ~cond_10)? ( WRITE_DOUBLE_NONE) :
|
211 |
|
|
write_double_state;
|
212 |
|
|
wire write_ac_to_reg =
|
213 |
|
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(cond_0 && ~cond_1 && ~cond_2 && cond_3)? ( `TRUE) :
|
214 |
|
|
write_ac;
|
215 |
|
|
wire [31:0] tlbcode_physical_to_reg =
|
216 |
|
|
(cond_22 && ~cond_23 && cond_17 && ~cond_18)? ( memtype_physical) :
|
217 |
|
|
tlbcode_physical;
|
218 |
|
|
wire rw_to_reg =
|
219 |
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(cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && cond_4)? ( `TRUE) :
|
220 |
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(cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && ~cond_4 && cond_5)? ( tlbcheck_rw) :
|
221 |
|
|
(cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && ~cond_4 && ~cond_5 && ~cond_6 && cond_7)? ( tlbread_rmw) :
|
222 |
|
|
(cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && ~cond_4 && ~cond_5 && ~cond_6 && ~cond_7 && cond_8)? ( `FALSE) :
|
223 |
|
|
rw;
|
224 |
|
|
wire code_pf_to_reg =
|
225 |
|
|
(cond_22 && ~cond_23 && cond_17 && cond_18)? ( `TRUE) :
|
226 |
|
|
(cond_24 && cond_14 && cond_25 && cond_26)? ( `TRUE) :
|
227 |
|
|
(cond_32 && cond_14 && cond_33 && cond_26)? ( `TRUE) :
|
228 |
|
|
code_pf;
|
229 |
|
|
//======================================================== always
|
230 |
|
|
always @(posedge clk or negedge rst_n) begin
|
231 |
|
|
if(rst_n == 1'b0) current_type <= 2'd0;
|
232 |
|
|
else current_type <= current_type_to_reg;
|
233 |
|
|
end
|
234 |
|
|
always @(posedge clk or negedge rst_n) begin
|
235 |
|
|
if(rst_n == 1'b0) pde <= 32'd0;
|
236 |
|
|
else pde <= pde_to_reg;
|
237 |
|
|
end
|
238 |
|
|
always @(posedge clk or negedge rst_n) begin
|
239 |
|
|
if(rst_n == 1'b0) state <= 5'd0;
|
240 |
|
|
else state <= state_to_reg;
|
241 |
|
|
end
|
242 |
|
|
always @(posedge clk or negedge rst_n) begin
|
243 |
|
|
if(rst_n == 1'b0) tlb_read_pf_cr2 <= 32'd0;
|
244 |
|
|
else tlb_read_pf_cr2 <= tlb_read_pf_cr2_to_reg;
|
245 |
|
|
end
|
246 |
|
|
always @(posedge clk or negedge rst_n) begin
|
247 |
|
|
if(rst_n == 1'b0) tlb_code_pf_cr2 <= 32'd0;
|
248 |
|
|
else tlb_code_pf_cr2 <= tlb_code_pf_cr2_to_reg;
|
249 |
|
|
end
|
250 |
|
|
always @(posedge clk or negedge rst_n) begin
|
251 |
|
|
if(rst_n == 1'b0) su <= 1'd0;
|
252 |
|
|
else su <= su_to_reg;
|
253 |
|
|
end
|
254 |
|
|
always @(posedge clk or negedge rst_n) begin
|
255 |
|
|
if(rst_n == 1'b0) tlb_check_pf_error_code <= 16'd0;
|
256 |
|
|
else tlb_check_pf_error_code <= tlb_check_pf_error_code_to_reg;
|
257 |
|
|
end
|
258 |
|
|
always @(posedge clk or negedge rst_n) begin
|
259 |
|
|
if(rst_n == 1'b0) tlb_write_pf_error_code <= 16'd0;
|
260 |
|
|
else tlb_write_pf_error_code <= tlb_write_pf_error_code_to_reg;
|
261 |
|
|
end
|
262 |
|
|
always @(posedge clk or negedge rst_n) begin
|
263 |
|
|
if(rst_n == 1'b0) write_double_linear <= 32'd0;
|
264 |
|
|
else write_double_linear <= write_double_linear_to_reg;
|
265 |
|
|
end
|
266 |
|
|
always @(posedge clk or negedge rst_n) begin
|
267 |
|
|
if(rst_n == 1'b0) tlbcode_cache_disable <= 1'd0;
|
268 |
|
|
else tlbcode_cache_disable <= tlbcode_cache_disable_to_reg;
|
269 |
|
|
end
|
270 |
|
|
always @(posedge clk or negedge rst_n) begin
|
271 |
|
|
if(rst_n == 1'b0) linear <= 32'd0;
|
272 |
|
|
else linear <= linear_to_reg;
|
273 |
|
|
end
|
274 |
|
|
always @(posedge clk or negedge rst_n) begin
|
275 |
|
|
if(rst_n == 1'b0) tlb_code_pf_error_code <= 16'd0;
|
276 |
|
|
else tlb_code_pf_error_code <= tlb_code_pf_error_code_to_reg;
|
277 |
|
|
end
|
278 |
|
|
always @(posedge clk or negedge rst_n) begin
|
279 |
|
|
if(rst_n == 1'b0) tlbcode_do <= 1'd0;
|
280 |
|
|
else tlbcode_do <= tlbcode_do_to_reg;
|
281 |
|
|
end
|
282 |
|
|
always @(posedge clk or negedge rst_n) begin
|
283 |
|
|
if(rst_n == 1'b0) wp <= 1'd0;
|
284 |
|
|
else wp <= wp_to_reg;
|
285 |
|
|
end
|
286 |
|
|
always @(posedge clk or negedge rst_n) begin
|
287 |
|
|
if(rst_n == 1'b0) tlbcheck_done <= 1'd0;
|
288 |
|
|
else tlbcheck_done <= tlbcheck_done_to_reg;
|
289 |
|
|
end
|
290 |
|
|
always @(posedge clk or negedge rst_n) begin
|
291 |
|
|
if(rst_n == 1'b0) tlb_write_pf_cr2 <= 32'd0;
|
292 |
|
|
else tlb_write_pf_cr2 <= tlb_write_pf_cr2_to_reg;
|
293 |
|
|
end
|
294 |
|
|
always @(posedge clk or negedge rst_n) begin
|
295 |
|
|
if(rst_n == 1'b0) pte <= 32'd0;
|
296 |
|
|
else pte <= pte_to_reg;
|
297 |
|
|
end
|
298 |
|
|
always @(posedge clk or negedge rst_n) begin
|
299 |
|
|
if(rst_n == 1'b0) tlb_check_pf_cr2 <= 32'd0;
|
300 |
|
|
else tlb_check_pf_cr2 <= tlb_check_pf_cr2_to_reg;
|
301 |
|
|
end
|
302 |
|
|
always @(posedge clk or negedge rst_n) begin
|
303 |
|
|
if(rst_n == 1'b0) tlb_read_pf_error_code <= 16'd0;
|
304 |
|
|
else tlb_read_pf_error_code <= tlb_read_pf_error_code_to_reg;
|
305 |
|
|
end
|
306 |
|
|
always @(posedge clk or negedge rst_n) begin
|
307 |
|
|
if(rst_n == 1'b0) write_double_state <= 2'd0;
|
308 |
|
|
else write_double_state <= write_double_state_to_reg;
|
309 |
|
|
end
|
310 |
|
|
always @(posedge clk or negedge rst_n) begin
|
311 |
|
|
if(rst_n == 1'b0) tlbcode_physical <= 32'd0;
|
312 |
|
|
else tlbcode_physical <= tlbcode_physical_to_reg;
|
313 |
|
|
end
|
314 |
|
|
always @(posedge clk or negedge rst_n) begin
|
315 |
|
|
if(rst_n == 1'b0) rw <= 1'd0;
|
316 |
|
|
else rw <= rw_to_reg;
|
317 |
|
|
end
|
318 |
|
|
//======================================================== sets
|
319 |
|
|
assign dcachewrite_do =
|
320 |
|
|
(cond_19 && cond_17 && ~cond_18 && ~cond_20)? (`TRUE) :
|
321 |
|
|
(cond_35 && cond_36)? (`TRUE) :
|
322 |
|
|
(cond_35 && ~cond_36 && cond_37)? (`TRUE) :
|
323 |
|
|
(cond_35 && ~cond_36 && ~cond_37 && ~cond_38 && cond_28)? (`TRUE) :
|
324 |
|
|
(cond_41)? (`TRUE) :
|
325 |
|
|
(cond_42 && ~cond_38)? (`TRUE) :
|
326 |
|
|
1'd0;
|
327 |
|
|
assign dcacheread_length =
|
328 |
|
|
(cond_15 && cond_17 && ~cond_18)? ( tlbread_length) :
|
329 |
|
|
(cond_15 && ~cond_17)? ( 4'd4) :
|
330 |
|
|
(cond_19 && ~cond_17)? ( 4'd4) :
|
331 |
|
|
(cond_21 && ~cond_17)? ( 4'd4) :
|
332 |
|
|
(cond_22 && ~cond_23 && ~cond_17)? ( 4'd4) :
|
333 |
|
|
(cond_30)? ( 4'd4) :
|
334 |
|
|
(cond_39)? ( tlbread_length) :
|
335 |
|
|
(cond_40 && cond_12 && ~cond_37 && ~cond_28 && cond_29)? ( tlbread_length) :
|
336 |
|
|
(cond_43 && cond_12 && ~cond_28 && cond_29)? ( tlbread_length) :
|
337 |
|
|
4'd0;
|
338 |
|
|
assign tlbregs_tlbflushall_do =
|
339 |
|
|
(cond_0 && ~cond_1 && cond_2)? (`TRUE) :
|
340 |
|
|
1'd0;
|
341 |
|
|
assign dcachewrite_length =
|
342 |
|
|
(cond_19 && cond_17 && ~cond_18 && ~cond_20)? ( tlbwrite_length) :
|
343 |
|
|
(cond_35 && cond_36)? ( 3'd4) :
|
344 |
|
|
(cond_35 && ~cond_36 && cond_37)? ( 3'd4) :
|
345 |
|
|
(cond_35 && ~cond_36 && ~cond_37 && ~cond_38 && cond_28)? ( tlbwrite_length) :
|
346 |
|
|
(cond_41)? ( 3'd4) :
|
347 |
|
|
(cond_42 && ~cond_38)? ( tlbwrite_length) :
|
348 |
|
|
3'd0;
|
349 |
|
|
assign tlbregs_write_combined_rw =
|
350 |
|
|
(cond_35)? ( rw_entry) :
|
351 |
|
|
1'd0;
|
352 |
|
|
assign tlbregs_write_pcd =
|
353 |
|
|
(cond_35)? ( pte[4]) :
|
354 |
|
|
1'd0;
|
355 |
|
|
assign tlbwrite_done =
|
356 |
|
|
(cond_11 && cond_12)? (`TRUE) :
|
357 |
|
|
1'd0;
|
358 |
|
|
assign tlbread_retry =
|
359 |
|
|
(cond_31)? ( current_type == TYPE_READ) :
|
360 |
|
|
1'd0;
|
361 |
|
|
assign dcachewrite_address =
|
362 |
|
|
(cond_19 && cond_17 && ~cond_18 && ~cond_20)? ( memtype_physical) :
|
363 |
|
|
(cond_35 && cond_36)? ( memtype_physical) :
|
364 |
|
|
(cond_35 && ~cond_36 && cond_37)? ( memtype_physical) :
|
365 |
|
|
(cond_35 && ~cond_36 && ~cond_37 && ~cond_38 && cond_28)? ( memtype_physical) :
|
366 |
|
|
(cond_41)? ( memtype_physical) :
|
367 |
|
|
(cond_42 && ~cond_38)? ( memtype_physical) :
|
368 |
|
|
32'd0;
|
369 |
|
|
assign tlbregs_write_pwt =
|
370 |
|
|
(cond_35)? ( pte[3]) :
|
371 |
|
|
1'd0;
|
372 |
|
|
assign tlbregs_write_linear =
|
373 |
|
|
(cond_35)? ( linear) :
|
374 |
|
|
32'd0;
|
375 |
|
|
assign tlbread_done =
|
376 |
|
|
(cond_13 && cond_14)? (`TRUE) :
|
377 |
|
|
1'd0;
|
378 |
|
|
assign dcachewrite_data =
|
379 |
|
|
(cond_19 && cond_17 && ~cond_18 && ~cond_20)? ( tlbwrite_data) :
|
380 |
|
|
(cond_35 && cond_36)? ( pde | 32'h00000020) :
|
381 |
|
|
(cond_35 && ~cond_36 && cond_37)? ( pte[31:0] | 32'h00000020 | ((pte[6] == `FALSE && rw)? 32'h00000040 : 32'h00000000)) :
|
382 |
|
|
(cond_35 && ~cond_36 && ~cond_37 && ~cond_38 && cond_28)? ( tlbwrite_data) :
|
383 |
|
|
(cond_41)? ( pte[31:0] | 32'h00000020 | ((pte[6] == `FALSE && rw)? 32'h00000040 : 32'h00000000)) :
|
384 |
|
|
(cond_42 && ~cond_38)? ( tlbwrite_data) :
|
385 |
|
|
32'd0;
|
386 |
|
|
assign tlbregs_tlbflushsingle_do =
|
387 |
|
|
(cond_0 && cond_1)? (`TRUE) :
|
388 |
|
|
1'd0;
|
389 |
|
|
assign translate_do =
|
390 |
|
|
(cond_15 && cond_16)? (`TRUE) :
|
391 |
|
|
(cond_19 && cond_16)? (`TRUE) :
|
392 |
|
|
(cond_21 && cond_16)? (`TRUE) :
|
393 |
|
|
(cond_22 && cond_16)? (`TRUE) :
|
394 |
|
|
1'd0;
|
395 |
|
|
assign tlbregs_write_physical =
|
396 |
|
|
(cond_35)? ( { pte[31:12], linear[11:0] }) :
|
397 |
|
|
32'd0;
|
398 |
|
|
assign tlbregs_write_do =
|
399 |
|
|
(cond_35)? (`TRUE) :
|
400 |
|
|
1'd0;
|
401 |
|
|
assign tlbflushsingle_done =
|
402 |
|
|
(cond_0 && cond_1)? (`TRUE) :
|
403 |
|
|
1'd0;
|
404 |
|
|
assign dcachewrite_write_through =
|
405 |
|
|
(cond_19 && cond_17 && ~cond_18 && ~cond_20)? ( cr0_nw || translate_pwt || memtype_write_transparent) :
|
406 |
|
|
(cond_35 && cond_36)? ( cr0_nw || cr3_pwt || memtype_write_transparent) :
|
407 |
|
|
(cond_35 && ~cond_36 && cond_37)? ( cr0_nw || pde[3] || memtype_write_transparent) :
|
408 |
|
|
(cond_35 && ~cond_36 && ~cond_37 && ~cond_38 && cond_28)? ( cr0_nw || pte[3] || memtype_write_transparent) :
|
409 |
|
|
(cond_41)? ( cr0_nw || pde[3] || memtype_write_transparent) :
|
410 |
|
|
(cond_42 && ~cond_38)? ( cr0_nw || pte[3] || memtype_write_transparent) :
|
411 |
|
|
1'd0;
|
412 |
|
|
assign dcacheread_address =
|
413 |
|
|
(cond_15 && cond_17 && ~cond_18)? ( memtype_physical) :
|
414 |
|
|
(cond_15 && ~cond_17)? ( memtype_physical) :
|
415 |
|
|
(cond_19 && ~cond_17)? ( memtype_physical) :
|
416 |
|
|
(cond_21 && ~cond_17)? ( memtype_physical) :
|
417 |
|
|
(cond_22 && ~cond_23 && ~cond_17)? ( memtype_physical) :
|
418 |
|
|
(cond_30)? ( memtype_physical) :
|
419 |
|
|
(cond_39)? ( memtype_physical) :
|
420 |
|
|
(cond_40 && cond_12 && ~cond_37 && ~cond_28 && cond_29)? ( memtype_physical) :
|
421 |
|
|
(cond_43 && cond_12 && ~cond_28 && cond_29)? ( memtype_physical) :
|
422 |
|
|
32'd0;
|
423 |
|
|
assign dcachewrite_cache_disable =
|
424 |
|
|
(cond_19 && cond_17 && ~cond_18 && ~cond_20)? ( cr0_cd || translate_pcd || memtype_cache_disable) :
|
425 |
|
|
(cond_35 && cond_36)? ( cr0_cd || cr3_pcd || memtype_cache_disable) :
|
426 |
|
|
(cond_35 && ~cond_36 && cond_37)? ( cr0_cd || pde[4] || memtype_cache_disable) :
|
427 |
|
|
(cond_35 && ~cond_36 && ~cond_37 && ~cond_38 && cond_28)? ( cr0_cd || pte[4] || memtype_cache_disable) :
|
428 |
|
|
(cond_41)? ( cr0_cd || pde[4] || memtype_cache_disable) :
|
429 |
|
|
(cond_42 && ~cond_38)? ( cr0_cd || pte[4] || memtype_cache_disable) :
|
430 |
|
|
1'd0;
|
431 |
|
|
assign tlbregs_write_combined_su =
|
432 |
|
|
(cond_35)? ( su_entry) :
|
433 |
|
|
1'd0;
|
434 |
|
|
assign dcacheread_do =
|
435 |
|
|
(cond_15 && cond_17 && ~cond_18)? (`TRUE) :
|
436 |
|
|
(cond_15 && ~cond_17)? (`TRUE) :
|
437 |
|
|
(cond_19 && ~cond_17)? (`TRUE) :
|
438 |
|
|
(cond_21 && ~cond_17)? (`TRUE) :
|
439 |
|
|
(cond_22 && ~cond_23 && ~cond_17)? (`TRUE) :
|
440 |
|
|
(cond_30)? (`TRUE) :
|
441 |
|
|
(cond_39)? (`TRUE) :
|
442 |
|
|
(cond_40 && cond_12 && ~cond_37 && ~cond_28 && cond_29)? (`TRUE) :
|
443 |
|
|
(cond_43 && cond_12 && ~cond_28 && cond_29)? (`TRUE) :
|
444 |
|
|
1'd0;
|
445 |
|
|
assign memtype_physical =
|
446 |
|
|
(cond_15 && cond_17 && ~cond_18)? ( translate_physical) :
|
447 |
|
|
(cond_15 && ~cond_17)? ( { cr3_base[31:12], linear[31:22], 2'd0 }) :
|
448 |
|
|
(cond_19 && cond_17 && ~cond_18 && ~cond_20)? ( translate_physical) :
|
449 |
|
|
(cond_19 && ~cond_17)? ( { cr3_base[31:12], linear[31:22], 2'd0 }) :
|
450 |
|
|
(cond_21 && ~cond_17)? ( { cr3_base[31:12], linear[31:22], 2'd0 }) :
|
451 |
|
|
(cond_22 && ~cond_23 && cond_17 && ~cond_18)? ( translate_physical) :
|
452 |
|
|
(cond_22 && ~cond_23 && ~cond_17)? ( { cr3_base[31:12], linear[31:22], 2'd0 }) :
|
453 |
|
|
(cond_30)? ( { pde[31:12], linear[21:12], 2'd0 }) :
|
454 |
|
|
(cond_35 && cond_36)? ( { cr3_base[31:12], linear[31:22], 2'd0 }) :
|
455 |
|
|
(cond_35 && ~cond_36 && cond_37)? ( { pde[31:12], linear[21:12], 2'b00 }) :
|
456 |
|
|
(cond_35 && ~cond_36 && ~cond_37 && ~cond_38 && cond_28)? ( { pte[31:12], linear[11:0] }) :
|
457 |
|
|
(cond_39)? ( { pte[31:12], linear[11:0] }) :
|
458 |
|
|
(cond_40 && cond_12 && ~cond_37 && ~cond_28 && cond_29)? ( { pte[31:12], linear[11:0] }) :
|
459 |
|
|
(cond_41)? ( { pde[31:12], linear[21:12], 2'b00 }) :
|
460 |
|
|
(cond_42 && ~cond_38)? ( { pte[31:12], linear[11:0] }) :
|
461 |
|
|
(cond_43 && cond_12 && ~cond_28 && cond_29)? ( { pte[31:12], linear[11:0] }) :
|
462 |
|
|
32'd0;
|
463 |
|
|
assign prefetchfifo_signal_pf_do =
|
464 |
|
|
(cond_22 && ~cond_23 && cond_17 && cond_18)? (`TRUE) :
|
465 |
|
|
(cond_24 && cond_14 && cond_25 && cond_26)? (`TRUE) :
|
466 |
|
|
(cond_32 && cond_14 && cond_33 && cond_26)? (`TRUE) :
|
467 |
|
|
1'd0;
|
468 |
|
|
assign dcacheread_cache_disable =
|
469 |
|
|
(cond_15 && cond_17 && ~cond_18)? ( cr0_cd || translate_pcd || memtype_cache_disable) :
|
470 |
|
|
(cond_15 && ~cond_17)? ( cr0_cd || cr3_pcd || memtype_cache_disable) :
|
471 |
|
|
(cond_19 && ~cond_17)? ( cr0_cd || cr3_pcd || memtype_cache_disable) :
|
472 |
|
|
(cond_21 && ~cond_17)? ( cr0_cd || cr3_pcd || memtype_cache_disable) :
|
473 |
|
|
(cond_22 && ~cond_23 && ~cond_17)? ( cr0_cd || cr3_pcd || memtype_cache_disable) :
|
474 |
|
|
(cond_30)? ( cr0_cd || pde[4] || memtype_cache_disable) :
|
475 |
|
|
(cond_39)? ( cr0_cd || pte[4] || memtype_cache_disable) :
|
476 |
|
|
(cond_40 && cond_12 && ~cond_37 && ~cond_28 && cond_29)? ( cr0_cd || pte[4] || memtype_cache_disable) :
|
477 |
|
|
(cond_43 && cond_12 && ~cond_28 && cond_29)? ( cr0_cd || pte[4] || memtype_cache_disable) :
|
478 |
|
|
1'd0;
|