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[/] [ao486/] [trunk/] [rtl/] [ao486/] [autogen/] [tlb.v] - Blame information for rev 7

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Line No. Rev Author Line
1 2 alfik
//======================================================== conditions
2
wire cond_0 = state == STATE_IDLE;
3
wire cond_1 = tlbflushsingle_do;
4
wire cond_2 = tlbflushall_do || tlbflushall_do_waiting;
5
wire cond_3 = ~(wr_reset) && tlbwrite_do && ~(write_ac) && cr0_am && acflag && tlbwrite_cpl == 2'd3 &&
6
             ( (tlbwrite_length_full == 3'd2 && tlbwrite_address[0] != 1'b0) || (tlbwrite_length_full == 3'd4 && tlbwrite_address[1:0] != 2'b00) )
7
    ;
8
wire cond_4 = ~(wr_reset) && tlbwrite_do && ~(write_pf) && ~(write_ac);
9
wire cond_5 = ~(exe_reset) && tlbcheck_do && ~(tlbcheck_done) && ~(check_pf);
10
wire cond_6 = ~(rd_reset) && tlbread_do && ~(read_ac) && cr0_am && acflag && tlbread_cpl == 2'd3 &&
11
             ( (tlbread_length_full == 4'd2 && tlbread_address[0] != 1'b0) || (tlbread_length_full == 4'd4 && tlbread_address[1:0] != 2'b00))
12
    ;
13
wire cond_7 = ~(rd_reset) && tlbread_do && ~(read_pf) && ~(read_ac);
14
wire cond_8 = ~(pr_reset) && tlbcoderequest_do && ~(code_pf) && ~(tlbcode_do);
15
wire cond_9 = state == STATE_WRITE_DOUBLE;
16
wire cond_10 = write_double_state == WRITE_DOUBLE_CHECK;
17
wire cond_11 = state == STATE_WRITE_WAIT;
18
wire cond_12 = dcachewrite_done;
19
wire cond_13 = state == STATE_READ_WAIT;
20
wire cond_14 = dcacheread_done;
21
wire cond_15 = state == STATE_READ_CHECK;
22
wire cond_16 = cr0_pg;
23
wire cond_17 = ~(cr0_pg) || translate_valid;
24
wire cond_18 = cr0_pg && fault;
25
wire cond_19 = state == STATE_WRITE_CHECK;
26
wire cond_20 = translate_valid && write_double_state != WRITE_DOUBLE_NONE;
27
wire cond_21 = state == STATE_CHECK_CHECK;
28
wire cond_22 = state == STATE_CODE_CHECK;
29
wire cond_23 = pr_reset || pr_reset_waiting;
30
wire cond_24 = state == STATE_LOAD_PDE;
31
wire cond_25 = dcacheread_data[0] == `FALSE;
32
wire cond_26 = current_type == TYPE_CODE && ~(pr_reset) && ~(pr_reset_waiting);
33
wire cond_27 = current_type == TYPE_CHECK;
34
wire cond_28 = current_type == TYPE_WRITE;
35
wire cond_29 = current_type == TYPE_READ;
36
wire cond_30 = state == STATE_LOAD_PTE_START;
37
wire cond_31 = state == STATE_RETRY;
38
wire cond_32 = state == STATE_LOAD_PTE;
39
wire cond_33 = dcacheread_data[0] == `FALSE || fault_before_pte;
40
wire cond_34 = ((current_type == TYPE_READ && ~(pipeline_after_read_empty)) || (current_type == TYPE_CODE && (~(pipeline_after_prefetch_empty) || pr_reset_waiting))) &&
41
                 (pde[5] == `FALSE || dcacheread_data[5] == `FALSE || (dcacheread_data[6] == `FALSE && rw));
42
wire cond_35 = state == STATE_LOAD_PTE_END;
43
wire cond_36 = pde[5] == `FALSE;
44
wire cond_37 = pte[5] == `FALSE || (pte[6] == `FALSE && rw);
45
wire cond_38 = current_type == TYPE_WRITE && write_double_state != WRITE_DOUBLE_NONE;
46
wire cond_39 = state == STATE_READ_WAIT_START;
47
wire cond_40 = state == STATE_SAVE_PDE;
48
wire cond_41 = state == STATE_SAVE_PTE_START;
49
wire cond_42 = state == STATE_WRITE_WAIT_START;
50
wire cond_43 = state == STATE_SAVE_PTE;
51
//======================================================== saves
52
wire [1:0] current_type_to_reg =
53
    (cond_15 && ~cond_17)? (   TYPE_READ) :
54
    (cond_19 && ~cond_17)? (   TYPE_WRITE) :
55
    (cond_21 && ~cond_17)? (   TYPE_CHECK) :
56
    (cond_22 && ~cond_23 && ~cond_17)? (   TYPE_CODE) :
57
    current_type;
58
wire  read_pf_to_reg =
59
    (cond_0)? (       `FALSE) :
60
    (cond_15 && cond_17 && cond_18)? (            `TRUE) :
61
    (cond_24 && cond_14 && cond_25 && ~cond_26 && ~cond_27 && ~cond_28 && cond_29)? (                `TRUE) :
62
    (cond_32 && cond_14 && cond_33 && ~cond_26 && ~cond_27 && ~cond_28 && cond_29)? (            `TRUE) :
63
    read_pf;
64
wire [31:0] pde_to_reg =
65
    (cond_24 && cond_14)? ( dcacheread_data[31:0]) :
66
    pde;
67
wire  write_pf_to_reg =
68
    (cond_0)? (      `FALSE) :
69
    (cond_19 && cond_17 && cond_18)? (                `TRUE) :
70
    (cond_24 && cond_14 && cond_25 && ~cond_26 && ~cond_27 && cond_28)? (               `TRUE) :
71
    (cond_32 && cond_14 && cond_33 && ~cond_26 && ~cond_27 && cond_28)? (               `TRUE) :
72
    write_pf;
73
wire [4:0] state_to_reg =
74
    (cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && cond_4)? (  STATE_WRITE_CHECK) :
75
    (cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && ~cond_4 && cond_5)? (  STATE_CHECK_CHECK) :
76
    (cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && ~cond_4 && ~cond_5 && ~cond_6 && cond_7)? (  STATE_READ_CHECK) :
77
    (cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && ~cond_4 && ~cond_5 && ~cond_6 && ~cond_7 && cond_8)? (  STATE_CODE_CHECK) :
78
    (cond_9 && cond_10)? (              STATE_WRITE_CHECK) :
79
    (cond_9 && ~cond_10)? (              STATE_WRITE_CHECK) :
80
    (cond_11 && cond_12)? ( STATE_IDLE) :
81
    (cond_13 && cond_14)? ( STATE_IDLE) :
82
    (cond_15 && cond_17 && cond_18)? ( STATE_IDLE) :
83
    (cond_15 && cond_17 && ~cond_18)? ( STATE_READ_WAIT) :
84
    (cond_15 && ~cond_17)? (          STATE_LOAD_PDE) :
85
    (cond_19 && cond_17 && cond_18)? ( STATE_IDLE) :
86
    (cond_19 && cond_17 && ~cond_18 && cond_20)? ( STATE_WRITE_DOUBLE) :
87
    (cond_19 && cond_17 && ~cond_18 && ~cond_20)? ( STATE_WRITE_WAIT) :
88
    (cond_19 && ~cond_17)? (          STATE_LOAD_PDE) :
89
    (cond_21 && cond_17)? ( STATE_IDLE) :
90
    (cond_21 && ~cond_17)? (          STATE_LOAD_PDE) :
91
    (cond_22 && cond_23)? ( STATE_IDLE) :
92
    (cond_22 && ~cond_23 && cond_17)? ( STATE_IDLE) :
93
    (cond_22 && ~cond_23 && ~cond_17)? (          STATE_LOAD_PDE) :
94
    (cond_24 && cond_14 && cond_25)? ( STATE_IDLE) :
95
    (cond_24 && cond_14 && ~cond_25)? ( STATE_LOAD_PTE_START) :
96
    (cond_30)? ( STATE_LOAD_PTE) :
97
    (cond_31)? ( STATE_IDLE) :
98
    (cond_32 && cond_14 && cond_33)? ( STATE_IDLE) :
99
    (cond_32 && cond_14 && ~cond_33 && cond_34)? ( STATE_RETRY) :
100
    (cond_32 && cond_14 && ~cond_33 && ~cond_34)? ( STATE_LOAD_PTE_END) :
101
    (cond_35 && cond_36)? ( STATE_SAVE_PDE) :
102
    (cond_35 && ~cond_36 && cond_37)? ( STATE_SAVE_PTE) :
103
    (cond_35 && ~cond_36 && ~cond_37 && cond_38)? ( STATE_WRITE_DOUBLE) :
104
    (cond_35 && ~cond_36 && ~cond_37 && ~cond_38 && cond_28)? ( STATE_WRITE_WAIT) :
105
    (cond_35 && ~cond_36 && ~cond_37 && ~cond_38 && ~cond_28 && cond_29)? ( STATE_READ_WAIT_START) :
106
    (cond_35 && ~cond_36 && ~cond_37 && ~cond_38 && ~cond_28 && ~cond_29)? ( STATE_IDLE) :
107
    (cond_39)? ( STATE_READ_WAIT) :
108
    (cond_40 && cond_12 && cond_37)? ( STATE_SAVE_PTE_START) :
109
    (cond_40 && cond_12 && ~cond_37 && cond_28)? ( STATE_WRITE_WAIT_START) :
110
    (cond_40 && cond_12 && ~cond_37 && ~cond_28 && cond_29)? ( STATE_READ_WAIT) :
111
    (cond_40 && cond_12 && ~cond_37 && ~cond_28 && ~cond_29)? ( STATE_IDLE) :
112
    (cond_41)? ( STATE_SAVE_PTE) :
113
    (cond_42 && cond_38)? ( STATE_WRITE_DOUBLE) :
114
    (cond_42 && ~cond_38)? ( STATE_WRITE_WAIT) :
115
    (cond_43 && cond_12 && cond_28)? ( STATE_WRITE_WAIT_START) :
116
    (cond_43 && cond_12 && ~cond_28 && cond_29)? ( STATE_READ_WAIT) :
117
    (cond_43 && cond_12 && ~cond_28 && ~cond_29)? ( STATE_IDLE) :
118
    state;
119
wire [31:0] tlb_read_pf_cr2_to_reg =
120
    (cond_15 && cond_17 && cond_18)? (        linear) :
121
    (cond_24 && cond_14 && cond_25 && ~cond_26 && ~cond_27 && ~cond_28 && cond_29)? (        linear) :
122
    (cond_32 && cond_14 && cond_33 && ~cond_26 && ~cond_27 && ~cond_28 && cond_29)? (        linear) :
123
    tlb_read_pf_cr2;
124
wire [31:0] tlb_code_pf_cr2_to_reg =
125
    (cond_22 && ~cond_23 && cond_17 && cond_18)? (       linear) :
126
    (cond_24 && cond_14 && cond_25 && cond_26)? (        linear) :
127
    (cond_32 && cond_14 && cond_33 && cond_26)? (        linear) :
128
    tlb_code_pf_cr2;
129
wire  check_pf_to_reg =
130
    (cond_21 && cond_17 && cond_18)? (               `TRUE) :
131
    (cond_24 && cond_14 && cond_25 && ~cond_26 && cond_27)? (               `TRUE) :
132
    (cond_32 && cond_14 && cond_33 && ~cond_26 && cond_27)? (               `TRUE) :
133
    check_pf;
134
wire  su_to_reg =
135
    (cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && cond_4)? (             tlbwrite_cpl == 2'd3) :
136
    (cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && ~cond_4 && cond_5)? (             `FALSE) :
137
    (cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && ~cond_4 && ~cond_5 && ~cond_6 && cond_7)? (             tlbread_cpl == 2'd3) :
138
    (cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && ~cond_4 && ~cond_5 && ~cond_6 && ~cond_7 && cond_8)? (             tlbcoderequest_su) :
139
    su;
140
wire [15:0] tlb_check_pf_error_code_to_reg =
141
    (cond_21 && cond_17 && cond_18)? ({ 13'd0, su, rw, `TRUE }) :
142
    (cond_24 && cond_14 && cond_25 && ~cond_26 && cond_27)? ({ 13'd0, su, rw, `FALSE }) :
143
    (cond_32 && cond_14 && cond_33 && ~cond_26 && cond_27)? ({ 13'd0, su, rw, dcacheread_data[0] }) :
144
    tlb_check_pf_error_code;
145
wire [15:0] tlb_write_pf_error_code_to_reg =
146
    (cond_19 && cond_17 && cond_18)? ( { 13'd0, su, rw, `TRUE }) :
147
    (cond_24 && cond_14 && cond_25 && ~cond_26 && ~cond_27 && cond_28)? ({ 13'd0, su, rw, `FALSE }) :
148
    (cond_32 && cond_14 && cond_33 && ~cond_26 && ~cond_27 && cond_28)? ({ 13'd0, su, rw, dcacheread_data[0] }) :
149
    tlb_write_pf_error_code;
150
wire [31:0] write_double_linear_to_reg =
151
    (cond_9 && cond_10)? ( linear) :
152
    write_double_linear;
153
wire  tlbcode_cache_disable_to_reg =
154
    (cond_22 && ~cond_23 && cond_17 && ~cond_18)? (   cr0_cd || translate_pcd || memtype_cache_disable) :
155
    tlbcode_cache_disable;
156
wire [31:0] linear_to_reg =
157
    (cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && cond_4)? ( tlbwrite_address) :
158
    (cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && ~cond_4 && cond_5)? ( tlbcheck_address) :
159
    (cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && ~cond_4 && ~cond_5 && ~cond_6 && cond_7)? ( tlbread_address) :
160
    (cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && ~cond_4 && ~cond_5 && ~cond_6 && ~cond_7 && cond_8)? ( tlbcoderequest_address) :
161
    (cond_9 && cond_10)? ( { linear[31:12], 12'd0 } + 32'h00001000) :
162
    (cond_9 && ~cond_10)? ( write_double_linear) :
163
    linear;
164
wire [15:0] tlb_code_pf_error_code_to_reg =
165
    (cond_22 && ~cond_23 && cond_17 && cond_18)? ({ 13'd0, su, rw, `TRUE }) :
166
    (cond_24 && cond_14 && cond_25 && cond_26)? ( { 13'd0, su, rw, `FALSE }) :
167
    (cond_32 && cond_14 && cond_33 && cond_26)? ( { 13'd0, su, rw, dcacheread_data[0] }) :
168
    tlb_code_pf_error_code;
169
wire  tlbcode_do_to_reg =
170
    (cond_0)? (    `FALSE) :
171
    (cond_22 && ~cond_23 && cond_17 && ~cond_18)? ( `TRUE) :
172
    tlbcode_do;
173
wire  wp_to_reg =
174
    (cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && cond_4)? (             cr0_wp) :
175
    (cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && ~cond_4 && cond_5)? (             cr0_wp) :
176
    (cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && ~cond_4 && ~cond_5 && ~cond_6 && cond_7)? (             cr0_wp) :
177
    (cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && ~cond_4 && ~cond_5 && ~cond_6 && ~cond_7 && cond_8)? (             cr0_wp) :
178
    wp;
179
wire  tlbcheck_done_to_reg =
180
    (cond_0)? ( `FALSE) :
181
    (cond_21 && cond_17 && ~cond_18)? ( `TRUE) :
182
    tlbcheck_done;
183
wire [31:0] tlb_write_pf_cr2_to_reg =
184
    (cond_19 && cond_17 && cond_18)? (        linear) :
185
    (cond_24 && cond_14 && cond_25 && ~cond_26 && ~cond_27 && cond_28)? (       linear) :
186
    (cond_32 && cond_14 && cond_33 && ~cond_26 && ~cond_27 && cond_28)? (       linear) :
187
    tlb_write_pf_cr2;
188
wire  read_ac_to_reg =
189
    (cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && ~cond_4 && ~cond_5 && cond_6)? ( `TRUE) :
190
    read_ac;
191
wire [31:0] pte_to_reg =
192
    (cond_32 && cond_14)? ( dcacheread_data[31:0]) :
193
    pte;
194
wire [31:0] tlb_check_pf_cr2_to_reg =
195
    (cond_21 && cond_17 && cond_18)? (       linear) :
196
    (cond_24 && cond_14 && cond_25 && ~cond_26 && cond_27)? (       linear) :
197
    (cond_32 && cond_14 && cond_33 && ~cond_26 && cond_27)? (       linear) :
198
    tlb_check_pf_cr2;
199
wire [15:0] tlb_read_pf_error_code_to_reg =
200
    (cond_15 && cond_17 && cond_18)? ( { 13'd0, su, rw, `TRUE }) :
201
    (cond_24 && cond_14 && cond_25 && ~cond_26 && ~cond_27 && ~cond_28 && cond_29)? ( { 13'd0, su, rw, `FALSE }) :
202
    (cond_32 && cond_14 && cond_33 && ~cond_26 && ~cond_27 && ~cond_28 && cond_29)? ( { 13'd0, su, rw, dcacheread_data[0] }) :
203
    tlb_read_pf_error_code;
204
wire [1:0] write_double_state_to_reg =
205
    (cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && cond_4)? ( (cr0_pg && tlbwrite_length != tlbwrite_length_full && { 1'b0, tlbwrite_address[11:0] } + { 10'd0, tlbwrite_length_full } >= 13'h1000)? WRITE_DOUBLE_CHECK : WRITE_DOUBLE_NONE) :
206
    (cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && ~cond_4 && cond_5)? ( WRITE_DOUBLE_NONE) :
207
    (cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && ~cond_4 && ~cond_5 && ~cond_6 && cond_7)? ( WRITE_DOUBLE_NONE) :
208
    (cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && ~cond_4 && ~cond_5 && ~cond_6 && ~cond_7 && cond_8)? ( WRITE_DOUBLE_NONE) :
209
    (cond_9 && cond_10)? ( WRITE_DOUBLE_RESTART) :
210
    (cond_9 && ~cond_10)? ( WRITE_DOUBLE_NONE) :
211
    write_double_state;
212
wire  write_ac_to_reg =
213
    (cond_0 && ~cond_1 && ~cond_2 && cond_3)? ( `TRUE) :
214
    write_ac;
215
wire [31:0] tlbcode_physical_to_reg =
216
    (cond_22 && ~cond_23 && cond_17 && ~cond_18)? (        memtype_physical) :
217
    tlbcode_physical;
218
wire  rw_to_reg =
219
    (cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && cond_4)? (             `TRUE) :
220
    (cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && ~cond_4 && cond_5)? (             tlbcheck_rw) :
221
    (cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && ~cond_4 && ~cond_5 && ~cond_6 && cond_7)? (             tlbread_rmw) :
222
    (cond_0 && ~cond_1 && ~cond_2 && ~cond_3 && ~cond_4 && ~cond_5 && ~cond_6 && ~cond_7 && cond_8)? (             `FALSE) :
223
    rw;
224
wire  code_pf_to_reg =
225
    (cond_22 && ~cond_23 && cond_17 && cond_18)? (                `TRUE) :
226
    (cond_24 && cond_14 && cond_25 && cond_26)? (                `TRUE) :
227
    (cond_32 && cond_14 && cond_33 && cond_26)? (                `TRUE) :
228
    code_pf;
229
//======================================================== always
230
always @(posedge clk or negedge rst_n) begin
231
    if(rst_n == 1'b0) current_type <= 2'd0;
232
    else              current_type <= current_type_to_reg;
233
end
234
always @(posedge clk or negedge rst_n) begin
235
    if(rst_n == 1'b0) pde <= 32'd0;
236
    else              pde <= pde_to_reg;
237
end
238
always @(posedge clk or negedge rst_n) begin
239
    if(rst_n == 1'b0) state <= 5'd0;
240
    else              state <= state_to_reg;
241
end
242
always @(posedge clk or negedge rst_n) begin
243
    if(rst_n == 1'b0) tlb_read_pf_cr2 <= 32'd0;
244
    else              tlb_read_pf_cr2 <= tlb_read_pf_cr2_to_reg;
245
end
246
always @(posedge clk or negedge rst_n) begin
247
    if(rst_n == 1'b0) tlb_code_pf_cr2 <= 32'd0;
248
    else              tlb_code_pf_cr2 <= tlb_code_pf_cr2_to_reg;
249
end
250
always @(posedge clk or negedge rst_n) begin
251
    if(rst_n == 1'b0) su <= 1'd0;
252
    else              su <= su_to_reg;
253
end
254
always @(posedge clk or negedge rst_n) begin
255
    if(rst_n == 1'b0) tlb_check_pf_error_code <= 16'd0;
256
    else              tlb_check_pf_error_code <= tlb_check_pf_error_code_to_reg;
257
end
258
always @(posedge clk or negedge rst_n) begin
259
    if(rst_n == 1'b0) tlb_write_pf_error_code <= 16'd0;
260
    else              tlb_write_pf_error_code <= tlb_write_pf_error_code_to_reg;
261
end
262
always @(posedge clk or negedge rst_n) begin
263
    if(rst_n == 1'b0) write_double_linear <= 32'd0;
264
    else              write_double_linear <= write_double_linear_to_reg;
265
end
266
always @(posedge clk or negedge rst_n) begin
267
    if(rst_n == 1'b0) tlbcode_cache_disable <= 1'd0;
268
    else              tlbcode_cache_disable <= tlbcode_cache_disable_to_reg;
269
end
270
always @(posedge clk or negedge rst_n) begin
271
    if(rst_n == 1'b0) linear <= 32'd0;
272
    else              linear <= linear_to_reg;
273
end
274
always @(posedge clk or negedge rst_n) begin
275
    if(rst_n == 1'b0) tlb_code_pf_error_code <= 16'd0;
276
    else              tlb_code_pf_error_code <= tlb_code_pf_error_code_to_reg;
277
end
278
always @(posedge clk or negedge rst_n) begin
279
    if(rst_n == 1'b0) tlbcode_do <= 1'd0;
280
    else              tlbcode_do <= tlbcode_do_to_reg;
281
end
282
always @(posedge clk or negedge rst_n) begin
283
    if(rst_n == 1'b0) wp <= 1'd0;
284
    else              wp <= wp_to_reg;
285
end
286
always @(posedge clk or negedge rst_n) begin
287
    if(rst_n == 1'b0) tlbcheck_done <= 1'd0;
288
    else              tlbcheck_done <= tlbcheck_done_to_reg;
289
end
290
always @(posedge clk or negedge rst_n) begin
291
    if(rst_n == 1'b0) tlb_write_pf_cr2 <= 32'd0;
292
    else              tlb_write_pf_cr2 <= tlb_write_pf_cr2_to_reg;
293
end
294
always @(posedge clk or negedge rst_n) begin
295
    if(rst_n == 1'b0) pte <= 32'd0;
296
    else              pte <= pte_to_reg;
297
end
298
always @(posedge clk or negedge rst_n) begin
299
    if(rst_n == 1'b0) tlb_check_pf_cr2 <= 32'd0;
300
    else              tlb_check_pf_cr2 <= tlb_check_pf_cr2_to_reg;
301
end
302
always @(posedge clk or negedge rst_n) begin
303
    if(rst_n == 1'b0) tlb_read_pf_error_code <= 16'd0;
304
    else              tlb_read_pf_error_code <= tlb_read_pf_error_code_to_reg;
305
end
306
always @(posedge clk or negedge rst_n) begin
307
    if(rst_n == 1'b0) write_double_state <= 2'd0;
308
    else              write_double_state <= write_double_state_to_reg;
309
end
310
always @(posedge clk or negedge rst_n) begin
311
    if(rst_n == 1'b0) tlbcode_physical <= 32'd0;
312
    else              tlbcode_physical <= tlbcode_physical_to_reg;
313
end
314
always @(posedge clk or negedge rst_n) begin
315
    if(rst_n == 1'b0) rw <= 1'd0;
316
    else              rw <= rw_to_reg;
317
end
318
//======================================================== sets
319
assign dcachewrite_do =
320
    (cond_19 && cond_17 && ~cond_18 && ~cond_20)? (`TRUE) :
321
    (cond_35 && cond_36)? (`TRUE) :
322
    (cond_35 && ~cond_36 && cond_37)? (`TRUE) :
323
    (cond_35 && ~cond_36 && ~cond_37 && ~cond_38 && cond_28)? (`TRUE) :
324
    (cond_41)? (`TRUE) :
325
    (cond_42 && ~cond_38)? (`TRUE) :
326
    1'd0;
327
assign dcacheread_length =
328
    (cond_15 && cond_17 && ~cond_18)? (           tlbread_length) :
329
    (cond_15 && ~cond_17)? (           4'd4) :
330
    (cond_19 && ~cond_17)? (           4'd4) :
331
    (cond_21 && ~cond_17)? (           4'd4) :
332
    (cond_22 && ~cond_23 && ~cond_17)? (           4'd4) :
333
    (cond_30)? (           4'd4) :
334
    (cond_39)? (           tlbread_length) :
335
    (cond_40 && cond_12 && ~cond_37 && ~cond_28 && cond_29)? (           tlbread_length) :
336
    (cond_43 && cond_12 && ~cond_28 && cond_29)? (           tlbread_length) :
337
    4'd0;
338
assign tlbregs_tlbflushall_do =
339
    (cond_0 && ~cond_1 && cond_2)? (`TRUE) :
340
    1'd0;
341
assign dcachewrite_length =
342
    (cond_19 && cond_17 && ~cond_18 && ~cond_20)? (          tlbwrite_length) :
343
    (cond_35 && cond_36)? (          3'd4) :
344
    (cond_35 && ~cond_36 && cond_37)? (          3'd4) :
345
    (cond_35 && ~cond_36 && ~cond_37 && ~cond_38 && cond_28)? (          tlbwrite_length) :
346
    (cond_41)? (          3'd4) :
347
    (cond_42 && ~cond_38)? (          tlbwrite_length) :
348
    3'd0;
349
assign tlbregs_write_combined_rw =
350
    (cond_35)? (   rw_entry) :
351
    1'd0;
352
assign tlbregs_write_pcd =
353
    (cond_35)? (           pte[4]) :
354
    1'd0;
355
assign tlbwrite_done =
356
    (cond_11 && cond_12)? (`TRUE) :
357
    1'd0;
358
assign tlbread_retry =
359
    (cond_31)? ( current_type == TYPE_READ) :
360
    1'd0;
361
assign dcachewrite_address =
362
    (cond_19 && cond_17 && ~cond_18 && ~cond_20)? (         memtype_physical) :
363
    (cond_35 && cond_36)? (         memtype_physical) :
364
    (cond_35 && ~cond_36 && cond_37)? (         memtype_physical) :
365
    (cond_35 && ~cond_36 && ~cond_37 && ~cond_38 && cond_28)? (         memtype_physical) :
366
    (cond_41)? (         memtype_physical) :
367
    (cond_42 && ~cond_38)? (         memtype_physical) :
368
    32'd0;
369
assign tlbregs_write_pwt =
370
    (cond_35)? (           pte[3]) :
371
    1'd0;
372
assign tlbregs_write_linear =
373
    (cond_35)? (        linear) :
374
    32'd0;
375
assign tlbread_done =
376
    (cond_13 && cond_14)? (`TRUE) :
377
    1'd0;
378
assign dcachewrite_data =
379
    (cond_19 && cond_17 && ~cond_18 && ~cond_20)? (            tlbwrite_data) :
380
    (cond_35 && cond_36)? (            pde | 32'h00000020) :
381
    (cond_35 && ~cond_36 && cond_37)? (            pte[31:0] | 32'h00000020 | ((pte[6] == `FALSE && rw)? 32'h00000040 : 32'h00000000)) :
382
    (cond_35 && ~cond_36 && ~cond_37 && ~cond_38 && cond_28)? (            tlbwrite_data) :
383
    (cond_41)? (            pte[31:0] | 32'h00000020 | ((pte[6] == `FALSE && rw)? 32'h00000040 : 32'h00000000)) :
384
    (cond_42 && ~cond_38)? (            tlbwrite_data) :
385
    32'd0;
386
assign tlbregs_tlbflushsingle_do =
387
    (cond_0 && cond_1)? (`TRUE) :
388
    1'd0;
389
assign translate_do =
390
    (cond_15 && cond_16)? (`TRUE) :
391
    (cond_19 && cond_16)? (`TRUE) :
392
    (cond_21 && cond_16)? (`TRUE) :
393
    (cond_22 && cond_16)? (`TRUE) :
394
    1'd0;
395
assign tlbregs_write_physical =
396
    (cond_35)? (      { pte[31:12], linear[11:0] }) :
397
    32'd0;
398
assign tlbregs_write_do =
399
    (cond_35)? (`TRUE) :
400
    1'd0;
401
assign tlbflushsingle_done =
402
    (cond_0 && cond_1)? (`TRUE) :
403
    1'd0;
404
assign dcachewrite_write_through =
405
    (cond_19 && cond_17 && ~cond_18 && ~cond_20)? (   cr0_nw || translate_pwt || memtype_write_transparent) :
406
    (cond_35 && cond_36)? (   cr0_nw || cr3_pwt || memtype_write_transparent) :
407
    (cond_35 && ~cond_36 && cond_37)? (   cr0_nw || pde[3] || memtype_write_transparent) :
408
    (cond_35 && ~cond_36 && ~cond_37 && ~cond_38 && cond_28)? (   cr0_nw || pte[3] || memtype_write_transparent) :
409
    (cond_41)? (   cr0_nw || pde[3] || memtype_write_transparent) :
410
    (cond_42 && ~cond_38)? (   cr0_nw || pte[3] || memtype_write_transparent) :
411
    1'd0;
412
assign dcacheread_address =
413
    (cond_15 && cond_17 && ~cond_18)? (          memtype_physical) :
414
    (cond_15 && ~cond_17)? (          memtype_physical) :
415
    (cond_19 && ~cond_17)? (          memtype_physical) :
416
    (cond_21 && ~cond_17)? (          memtype_physical) :
417
    (cond_22 && ~cond_23 && ~cond_17)? (          memtype_physical) :
418
    (cond_30)? (          memtype_physical) :
419
    (cond_39)? (          memtype_physical) :
420
    (cond_40 && cond_12 && ~cond_37 && ~cond_28 && cond_29)? (          memtype_physical) :
421
    (cond_43 && cond_12 && ~cond_28 && cond_29)? (          memtype_physical) :
422
    32'd0;
423
assign dcachewrite_cache_disable =
424
    (cond_19 && cond_17 && ~cond_18 && ~cond_20)? (   cr0_cd || translate_pcd || memtype_cache_disable) :
425
    (cond_35 && cond_36)? (   cr0_cd || cr3_pcd || memtype_cache_disable) :
426
    (cond_35 && ~cond_36 && cond_37)? (   cr0_cd || pde[4] || memtype_cache_disable) :
427
    (cond_35 && ~cond_36 && ~cond_37 && ~cond_38 && cond_28)? (   cr0_cd || pte[4] || memtype_cache_disable) :
428
    (cond_41)? (   cr0_cd || pde[4] || memtype_cache_disable) :
429
    (cond_42 && ~cond_38)? (   cr0_cd || pte[4] || memtype_cache_disable) :
430
    1'd0;
431
assign tlbregs_write_combined_su =
432
    (cond_35)? (   su_entry) :
433
    1'd0;
434
assign dcacheread_do =
435
    (cond_15 && cond_17 && ~cond_18)? (`TRUE) :
436
    (cond_15 && ~cond_17)? (`TRUE) :
437
    (cond_19 && ~cond_17)? (`TRUE) :
438
    (cond_21 && ~cond_17)? (`TRUE) :
439
    (cond_22 && ~cond_23 && ~cond_17)? (`TRUE) :
440
    (cond_30)? (`TRUE) :
441
    (cond_39)? (`TRUE) :
442
    (cond_40 && cond_12 && ~cond_37 && ~cond_28 && cond_29)? (`TRUE) :
443
    (cond_43 && cond_12 && ~cond_28 && cond_29)? (`TRUE) :
444
    1'd0;
445
assign memtype_physical =
446
    (cond_15 && cond_17 && ~cond_18)? ( translate_physical) :
447
    (cond_15 && ~cond_17)? ( { cr3_base[31:12], linear[31:22], 2'd0 }) :
448
    (cond_19 && cond_17 && ~cond_18 && ~cond_20)? ( translate_physical) :
449
    (cond_19 && ~cond_17)? ( { cr3_base[31:12], linear[31:22], 2'd0 }) :
450
    (cond_21 && ~cond_17)? ( { cr3_base[31:12], linear[31:22], 2'd0 }) :
451
    (cond_22 && ~cond_23 && cond_17 && ~cond_18)? ( translate_physical) :
452
    (cond_22 && ~cond_23 && ~cond_17)? ( { cr3_base[31:12], linear[31:22], 2'd0 }) :
453
    (cond_30)? ( { pde[31:12], linear[21:12], 2'd0 }) :
454
    (cond_35 && cond_36)? ( { cr3_base[31:12], linear[31:22], 2'd0 }) :
455
    (cond_35 && ~cond_36 && cond_37)? ( { pde[31:12], linear[21:12], 2'b00 }) :
456
    (cond_35 && ~cond_36 && ~cond_37 && ~cond_38 && cond_28)? ( { pte[31:12], linear[11:0] }) :
457
    (cond_39)? ( { pte[31:12], linear[11:0] }) :
458
    (cond_40 && cond_12 && ~cond_37 && ~cond_28 && cond_29)? ( { pte[31:12], linear[11:0] }) :
459
    (cond_41)? ( { pde[31:12], linear[21:12], 2'b00 }) :
460
    (cond_42 && ~cond_38)? ( { pte[31:12], linear[11:0] }) :
461
    (cond_43 && cond_12 && ~cond_28 && cond_29)? ( { pte[31:12], linear[11:0] }) :
462
    32'd0;
463
assign prefetchfifo_signal_pf_do =
464
    (cond_22 && ~cond_23 && cond_17 && cond_18)? (`TRUE) :
465
    (cond_24 && cond_14 && cond_25 && cond_26)? (`TRUE) :
466
    (cond_32 && cond_14 && cond_33 && cond_26)? (`TRUE) :
467
    1'd0;
468
assign dcacheread_cache_disable =
469
    (cond_15 && cond_17 && ~cond_18)? (    cr0_cd || translate_pcd || memtype_cache_disable) :
470
    (cond_15 && ~cond_17)? (    cr0_cd || cr3_pcd || memtype_cache_disable) :
471
    (cond_19 && ~cond_17)? (    cr0_cd || cr3_pcd || memtype_cache_disable) :
472
    (cond_21 && ~cond_17)? (    cr0_cd || cr3_pcd || memtype_cache_disable) :
473
    (cond_22 && ~cond_23 && ~cond_17)? (    cr0_cd || cr3_pcd || memtype_cache_disable) :
474
    (cond_30)? (    cr0_cd || pde[4] || memtype_cache_disable) :
475
    (cond_39)? (    cr0_cd || pte[4] || memtype_cache_disable) :
476
    (cond_40 && cond_12 && ~cond_37 && ~cond_28 && cond_29)? (    cr0_cd || pte[4] || memtype_cache_disable) :
477
    (cond_43 && cond_12 && ~cond_28 && cond_29)? (    cr0_cd || pte[4] || memtype_cache_disable) :
478
    1'd0;

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