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`define CMD_INVLPG          #AUTOGEN_NEXT_CMD

// wait for seg_linear to be ok

`define CMDEX_INVLPG_STEP_0     4'd0

// invalidate

`define CMDEX_INVLPG_STEP_1     4'd1

// stop next commands

`define CMDEX_INVLPG_STEP_2     4'd2

dec_ready_2byte_modregrm && decoder[7:0] == 8'h01 && decoder[13:11] == 3'd7

prefix_group_1_lock || `DEC_MODREGRM_IS_MOD_11

`CMD_INVLPG

SET(dec_cmdex, `CMDEX_INVLPG_STEP_0);

SET(consume_modregrm_one);

SET(dec_is_complex);

`CMDEX_INVLPG_STEP_0

`CMDEX_INVLPG_STEP_1

LOOP(`CMDEX_INVLPG_STEP_2);

IF(rd_cmd == `CMD_INVLPG && rd_cmdex == `CMDEX_INVLPG_STEP_1);

    IF(~(rd_address_effective_ready)); SET(rd_waiting); ENDIF();

ENDIF();

IF(exe_cmd == `CMD_INVLPG && exe_cmdex == `CMDEX_INVLPG_STEP_0);

    IF(cpl > 2'd0);

        SET(exe_waiting);

        SET(exe_trigger_gp_fault); //exception GP(0)

    ENDIF();

ENDIF();

IF(exe_cmd == `CMD_INVLPG && exe_cmdex == `CMDEX_INVLPG_STEP_1);

    SET(tlbflushsingle_do);

    SET(tlbflushsingle_address, exe_linear);

    IF(~(tlbflushsingle_done)); SET(exe_waiting); ENDIF();

ENDIF();

IF(wr_cmd == `CMD_INVLPG && wr_cmdex == `CMDEX_INVLPG_STEP_0);

    SET(wr_not_finished);

ENDIF();

IF(wr_cmd == `CMD_INVLPG && wr_cmdex == `CMDEX_INVLPG_STEP_1);

    // reset part of pipeline

    SET(wr_req_reset_micro);

    SET(wr_req_reset_rd);

    SET(wr_req_reset_exe);

ENDIF();