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[/] [ao486/] [trunk/] [rtl/] [ao486/] [commands/] [CMD_LxS.txt] - Blame information for rev 2

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`define CMD_LxS         #AUTOGEN_NEXT_CMD
// glob_param_2        --> new reg value
 
`define CMDEX_LxS_STEP_1        4'd0
`define CMDEX_LxS_STEP_2        4'd1
`define CMDEX_LxS_STEP_3        4'd2
`define CMDEX_LxS_STEP_LAST     4'd3

 

(dec_ready_modregrm_one && (decoder[7:0] == 8'hC4 || decoder[7:0] == 8'hC5)) || (dec_ready_2byte_modregrm && (decoder[7:0] == 8'hB2 || decoder[7:0] == 8'hB4 || decoder[7:0] == 8'hB5))
prefix_group_1_lock || `DEC_MODREGRM_IS_MOD_11
`CMD_LxS
SET(dec_cmdex, `CMDEX_LxS_STEP_1);
SET(consume_modregrm_one);
SET(dec_is_complex);

 

`CMDEX_LxS_STEP_1
`CMDEX_LxS_STEP_2
`CMDEX_LxS_STEP_3
CALL(`CMDEX_load_seg_STEP_1);
LOOP(`CMDEX_LxS_STEP_LAST);

 

IF(rd_cmd == `CMD_LxS && rd_cmdex == `CMDEX_LxS_STEP_1);
 
    IF(~(rd_address_effective_ready) || rd_mutex_busy_memory); SET(rd_waiting);
    ELSE();
 
        IF(rd_operand_16bit);
            SET(rd_glob_param_2_set);
            SET(rd_glob_param_2_value, read_4);
 
            SET(read_virtual);
 
            IF(~(read_for_rd_ready)); SET(rd_waiting); ENDIF();
        ENDIF();
    ENDIF();
ENDIF();

 

IF(rd_cmd == `CMD_LxS && rd_cmdex == `CMDEX_LxS_STEP_2);
 
    SET(address_ea_buffer);
 
    IF(rd_operand_32bit);
 
        SET(read_length_word);
 
        SET(rd_glob_param_1_set);
        SET(rd_glob_param_1_value, { 13'd0, rd_decoder[4] & rd_decoder[2], (rd_decoder[6] & rd_decoder[0]) | rd_decoder[1], rd_decoder[0], read_4[15:0] });
 
        SET(read_virtual);
 
        IF(~(read_for_rd_ready)); SET(rd_waiting); ENDIF();
 
    ENDIF();
ENDIF();

 
 

IF(rd_cmd == `CMD_LxS && rd_cmdex == `CMDEX_LxS_STEP_3);
 
    IF(rd_operand_16bit);
        SET(address_ea_buffer);
 
        SET(rd_glob_param_1_set);
        SET(rd_glob_param_1_value, { 13'd0, rd_decoder[4] & rd_decoder[2], (rd_decoder[6] & rd_decoder[0]) | rd_decoder[1], rd_decoder[0], read_4[15:0] });
    ELSE();
        SET(rd_glob_param_2_set);
        SET(rd_glob_param_2_value, read_4);
    ENDIF();
 
    SET(read_virtual);
 
    IF(~(read_for_rd_ready)); SET(rd_waiting); ENDIF();
ENDIF();

 

IF(rd_cmd == `CMD_LxS && rd_cmdex == `CMDEX_LxS_STEP_LAST);
    SET(rd_dst_is_reg);
 
    SET(rd_req_reg);
ENDIF();

 

IF(exe_cmd == `CMD_LxS);
    SET(exe_result, glob_param_2);
ENDIF();

 

IF(wr_cmd == `CMD_LxS && wr_cmdex != `CMDEX_LxS_STEP_LAST);
    SET(wr_not_finished);
ENDIF();

 

IF(wr_cmd == `CMD_LxS && wr_cmdex == `CMDEX_LxS_STEP_LAST);
 
    SET(write_regrm);
 
    // clear pipeline
    SET(wr_req_reset_micro);
    SET(wr_req_reset_rd);
    SET(wr_req_reset_exe);
ENDIF();

 

Line No.	Rev	Author	Line
1	2	alfik
2
3			`define CMD_LxS #AUTOGEN_NEXT_CMD
4			`// glob_param_2 --> new reg value`
5
6			`define CMDEX_LxS_STEP_1 4'd0
7			`define CMDEX_LxS_STEP_2 4'd1
8			`define CMDEX_LxS_STEP_3 4'd2
9			`define CMDEX_LxS_STEP_LAST 4'd3
10
11
12
13			`(dec_ready_modregrm_one && (decoder[7:0] == 8'hC4 \|\| decoder[7:0] == 8'hC5)) \|\| (dec_ready_2byte_modregrm && (decoder[7:0] == 8'hB2 \|\| decoder[7:0] == 8'hB4 \|\| decoder[7:0] == 8'hB5))`
14			prefix_group_1_lock \|\| `DEC_MODREGRM_IS_MOD_11
15			`CMD_LxS
16			SET(dec_cmdex, `CMDEX_LxS_STEP_1);
17			`SET(consume_modregrm_one);`
18			`SET(dec_is_complex);`
19
20
21
22			`CMDEX_LxS_STEP_1
23			`CMDEX_LxS_STEP_2
24			`CMDEX_LxS_STEP_3
25			CALL(`CMDEX_load_seg_STEP_1);
26			LOOP(`CMDEX_LxS_STEP_LAST);
27
28
29
30			IF(rd_cmd == `CMD_LxS && rd_cmdex == `CMDEX_LxS_STEP_1);
31
32			`IF(~(rd_address_effective_ready) \|\| rd_mutex_busy_memory); SET(rd_waiting);`
33			`ELSE();`
34
35			`IF(rd_operand_16bit);`
36			`SET(rd_glob_param_2_set);`
37			`SET(rd_glob_param_2_value, read_4);`
38
39			`SET(read_virtual);`
40
41			`IF(~(read_for_rd_ready)); SET(rd_waiting); ENDIF();`
42			`ENDIF();`
43			`ENDIF();`
44			`ENDIF();`
45
46
47
48			IF(rd_cmd == `CMD_LxS && rd_cmdex == `CMDEX_LxS_STEP_2);
49
50			`SET(address_ea_buffer);`
51
52			`IF(rd_operand_32bit);`
53
54			`SET(read_length_word);`
55
56			`SET(rd_glob_param_1_set);`
57			`SET(rd_glob_param_1_value, { 13'd0, rd_decoder[4] & rd_decoder[2], (rd_decoder[6] & rd_decoder[0]) \| rd_decoder[1], rd_decoder[0], read_4[15:0] });`
58
59			`SET(read_virtual);`
60
61			`IF(~(read_for_rd_ready)); SET(rd_waiting); ENDIF();`
62
63			`ENDIF();`
64			`ENDIF();`
65
66
67
68
69			IF(rd_cmd == `CMD_LxS && rd_cmdex == `CMDEX_LxS_STEP_3);
70
71			`IF(rd_operand_16bit);`
72			`SET(address_ea_buffer);`
73
74			`SET(rd_glob_param_1_set);`
75			`SET(rd_glob_param_1_value, { 13'd0, rd_decoder[4] & rd_decoder[2], (rd_decoder[6] & rd_decoder[0]) \| rd_decoder[1], rd_decoder[0], read_4[15:0] });`
76			`ELSE();`
77			`SET(rd_glob_param_2_set);`
78			`SET(rd_glob_param_2_value, read_4);`
79			`ENDIF();`
80
81			`SET(read_virtual);`
82
83			`IF(~(read_for_rd_ready)); SET(rd_waiting); ENDIF();`
84			`ENDIF();`
85
86
87
88			IF(rd_cmd == `CMD_LxS && rd_cmdex == `CMDEX_LxS_STEP_LAST);
89			`SET(rd_dst_is_reg);`
90
91			`SET(rd_req_reg);`
92			`ENDIF();`
93
94
95
96			IF(exe_cmd == `CMD_LxS);
97			`SET(exe_result, glob_param_2);`
98			`ENDIF();`
99
100
101
102			IF(wr_cmd == `CMD_LxS && wr_cmdex != `CMDEX_LxS_STEP_LAST);
103			`SET(wr_not_finished);`
104			`ENDIF();`
105
106
107
108			IF(wr_cmd == `CMD_LxS && wr_cmdex == `CMDEX_LxS_STEP_LAST);
109
110			`SET(write_regrm);`
111
112			`// clear pipeline`
113			`SET(wr_req_reset_micro);`
114			`SET(wr_req_reset_rd);`
115			`SET(wr_req_reset_exe);`
116			`ENDIF();`
117
118

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[/] [ao486/] [trunk/] [rtl/] [ao486/] [commands/] [CMD_LxS.txt] - Blame information for rev 2