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[/] [ao486/] [trunk/] [rtl/] [ao486/] [commands/] [CMD_MOV.txt] - Blame information for rev 2

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`define CMD_MOV         #AUTOGEN_NEXT_CMD
 
`define CMDEX_MOV_immediate         4'd0
`define CMDEX_MOV_modregrm          4'd1
`define CMDEX_MOV_modregrm_imm      4'd2
`define CMDEX_MOV_memoffset         4'd3

 

dec_ready_mem_offset && { decoder[7:2], 2'b0 } == 8'hA0
`CMD_MOV
SET(dec_cmdex, `CMDEX_MOV_memoffset);
IF(decoder[0] == 1'b0); SET(dec_is_8bit); ENDIF();
SET(consume_mem_offset);

 

dec_ready_one_imm && decoder[7:4] == 4'hB
`CMD_MOV
SET(dec_cmdex, `CMDEX_MOV_immediate);
IF(decoder[3] == 1'b0); SET(dec_is_8bit); ENDIF();
SET(consume_one_imm);

 

dec_ready_modregrm_one && { decoder[7:2], 2'b0 } == 8'h88
`CMD_MOV
SET(dec_cmdex, `CMDEX_MOV_modregrm);
IF(decoder[0] == 1'b0); SET(dec_is_8bit); ENDIF();
SET(consume_modregrm_one);

 

dec_ready_modregrm_imm && { decoder[7:1], 1'b0 } == 8'hC6 && decoder[13:11] == 3'd0
`CMD_MOV
SET(dec_cmdex, `CMDEX_MOV_modregrm_imm);
IF(decoder[0] == 1'b0); SET(dec_is_8bit); ENDIF();
SET(consume_modregrm_imm);

 

IF(rd_cmd == `CMD_MOV && rd_cmdex == `CMDEX_MOV_memoffset);
 
    SET(address_memoffset);
 
    // dst: eAX, src: mem
    IF(~(rd_decoder[1]));
 
        SET(rd_src_is_memory);
        SET(rd_dst_is_eax);
 
        SET(rd_req_eax);
 
        IF(rd_mutex_busy_memory); SET(rd_waiting);
        ELSE();
            SET(read_virtual);
 
            IF(~(read_for_rd_ready)); SET(rd_waiting); ENDIF();
        ENDIF();
 
    // dst: mem, src: eAX
    ELSE();
        SET(rd_src_is_eax);
        SET(rd_dst_is_memory);
 
        SET(rd_req_memory);
 
        SET(write_virtual_check);
 
        IF(rd_mutex_busy_eax || ~(write_virtual_check_ready)); SET(rd_waiting); ENDIF();
    ENDIF();
ENDIF();

 

IF(rd_cmd == `CMD_MOV && rd_cmdex == `CMDEX_MOV_modregrm && rd_decoder[1]);
 
    SET(rd_dst_is_reg);
 
    SET(rd_req_reg);
 
    // dst: reg, src: reg
    IF(rd_modregrm_mod == 2'b11);
 
        SET(rd_src_is_rm);
 
        IF(rd_mutex_busy_modregrm_rm); SET(rd_waiting); ENDIF();
    ENDIF();
 
    // dst: reg, src: memory
    IF(rd_modregrm_mod != 2'b11);
 
        SET(rd_src_is_memory);
 
        IF(rd_mutex_busy_memory); SET(rd_waiting);
        ELSE();
            SET(read_virtual);
 
            IF(~(read_for_rd_ready)); SET(rd_waiting); ENDIF();
        ENDIF();
    ENDIF();
ENDIF();

 

IF(rd_cmd == `CMD_MOV && rd_cmdex == `CMDEX_MOV_modregrm && ~(rd_decoder[1]));
 
    SET(rd_src_is_reg);
 
    // dst: reg, src: reg
    IF(rd_modregrm_mod == 2'b11);
        SET(rd_dst_is_rm);
 
        SET(rd_req_rm);
 
        IF(rd_mutex_busy_modregrm_reg); SET(rd_waiting); ENDIF();
    ENDIF();
 
    // dst: memory, src: reg
    IF(rd_modregrm_mod != 2'b11);
 
        SET(rd_dst_is_memory);
 
        SET(rd_req_memory);
 
        IF(rd_mutex_busy_modregrm_reg); SET(rd_waiting);
        ELSE();
            SET(write_virtual_check);
 
            IF(~(write_virtual_check_ready)); SET(rd_waiting); ENDIF();
        ENDIF();
    ENDIF();
ENDIF();

 

IF(rd_cmd == `CMD_MOV && rd_cmdex == `CMDEX_MOV_modregrm_imm);
 
    SET(rd_src_is_modregrm_imm);
 
    // dst: reg, src: imm
    IF(rd_modregrm_mod == 2'b11);
 
        SET(rd_dst_is_rm);
 
        SET(rd_req_rm);
 
        IF(rd_mutex_busy_modregrm_reg); SET(rd_waiting); ENDIF();
    ENDIF();
 
    // dst: memory, src: imm
    IF(rd_modregrm_mod != 2'b11);
 
        SET(rd_dst_is_memory);
 
        SET(rd_req_memory);
 
        IF(rd_mutex_busy_modregrm_reg); SET(rd_waiting);
        ELSE();
            SET(write_virtual_check);
 
            IF(~(write_virtual_check_ready)); SET(rd_waiting); ENDIF();
        ENDIF();
    ENDIF();
ENDIF();

 

IF(rd_cmd == `CMD_MOV && rd_cmdex == `CMDEX_MOV_immediate);
 
    SET(rd_src_is_imm);
    SET(rd_dst_is_implicit_reg);
 
    SET(rd_req_implicit_reg);
 
ENDIF();

 

IF(exe_cmd == `CMD_MOV); // `CMDEX_MEMOFFSET || `CMDEX_MODREGRM || `CMDEX_MODREGRM_IMM || `CMDEX_IMPLICIT
 
    SET(exe_result,  src);
    SET(exe_result2, dst);
 
ENDIF();

 

IF(wr_cmd == `CMD_MOV);
    IF(wr_dst_is_memory && ~(write_for_wr_ready)); SET(wr_waiting); ENDIF();
 
    SET(write_eax,      wr_dst_is_eax);
    SET(write_virtual,  wr_dst_is_memory);
    SET(write_regrm,    wr_dst_is_reg || wr_dst_is_rm || wr_dst_is_implicit_reg);
ENDIF();

 
 

Line No.	Rev	Author	Line
1	2	alfik
2
3			`define CMD_MOV #AUTOGEN_NEXT_CMD
4
5			`define CMDEX_MOV_immediate 4'd0
6			`define CMDEX_MOV_modregrm 4'd1
7			`define CMDEX_MOV_modregrm_imm 4'd2
8			`define CMDEX_MOV_memoffset 4'd3
9
10
11
12			`dec_ready_mem_offset && { decoder[7:2], 2'b0 } == 8'hA0`
13			`CMD_MOV
14			SET(dec_cmdex, `CMDEX_MOV_memoffset);
15			`IF(decoder[0] == 1'b0); SET(dec_is_8bit); ENDIF();`
16			`SET(consume_mem_offset);`
17
18
19
20			`dec_ready_one_imm && decoder[7:4] == 4'hB`
21			`CMD_MOV
22			SET(dec_cmdex, `CMDEX_MOV_immediate);
23			`IF(decoder[3] == 1'b0); SET(dec_is_8bit); ENDIF();`
24			`SET(consume_one_imm);`
25
26
27
28			`dec_ready_modregrm_one && { decoder[7:2], 2'b0 } == 8'h88`
29			`CMD_MOV
30			SET(dec_cmdex, `CMDEX_MOV_modregrm);
31			`IF(decoder[0] == 1'b0); SET(dec_is_8bit); ENDIF();`
32			`SET(consume_modregrm_one);`
33
34
35
36			`dec_ready_modregrm_imm && { decoder[7:1], 1'b0 } == 8'hC6 && decoder[13:11] == 3'd0`
37			`CMD_MOV
38			SET(dec_cmdex, `CMDEX_MOV_modregrm_imm);
39			`IF(decoder[0] == 1'b0); SET(dec_is_8bit); ENDIF();`
40			`SET(consume_modregrm_imm);`
41
42
43
44			IF(rd_cmd == `CMD_MOV && rd_cmdex == `CMDEX_MOV_memoffset);
45
46			`SET(address_memoffset);`
47
48			`// dst: eAX, src: mem`
49			`IF(~(rd_decoder[1]));`
50
51			`SET(rd_src_is_memory);`
52			`SET(rd_dst_is_eax);`
53
54			`SET(rd_req_eax);`
55
56			`IF(rd_mutex_busy_memory); SET(rd_waiting);`
57			`ELSE();`
58			`SET(read_virtual);`
59
60			`IF(~(read_for_rd_ready)); SET(rd_waiting); ENDIF();`
61			`ENDIF();`
62
63			`// dst: mem, src: eAX`
64			`ELSE();`
65			`SET(rd_src_is_eax);`
66			`SET(rd_dst_is_memory);`
67
68			`SET(rd_req_memory);`
69
70			`SET(write_virtual_check);`
71
72			`IF(rd_mutex_busy_eax \|\| ~(write_virtual_check_ready)); SET(rd_waiting); ENDIF();`
73			`ENDIF();`
74			`ENDIF();`
75
76
77
78			IF(rd_cmd == `CMD_MOV && rd_cmdex == `CMDEX_MOV_modregrm && rd_decoder[1]);
79
80			`SET(rd_dst_is_reg);`
81
82			`SET(rd_req_reg);`
83
84			`// dst: reg, src: reg`
85			`IF(rd_modregrm_mod == 2'b11);`
86
87			`SET(rd_src_is_rm);`
88
89			`IF(rd_mutex_busy_modregrm_rm); SET(rd_waiting); ENDIF();`
90			`ENDIF();`
91
92			`// dst: reg, src: memory`
93			`IF(rd_modregrm_mod != 2'b11);`
94
95			`SET(rd_src_is_memory);`
96
97			`IF(rd_mutex_busy_memory); SET(rd_waiting);`
98			`ELSE();`
99			`SET(read_virtual);`
100
101			`IF(~(read_for_rd_ready)); SET(rd_waiting); ENDIF();`
102			`ENDIF();`
103			`ENDIF();`
104			`ENDIF();`
105
106
107
108			IF(rd_cmd == `CMD_MOV && rd_cmdex == `CMDEX_MOV_modregrm && ~(rd_decoder[1]));
109
110			`SET(rd_src_is_reg);`
111
112			`// dst: reg, src: reg`
113			`IF(rd_modregrm_mod == 2'b11);`
114			`SET(rd_dst_is_rm);`
115
116			`SET(rd_req_rm);`
117
118			`IF(rd_mutex_busy_modregrm_reg); SET(rd_waiting); ENDIF();`
119			`ENDIF();`
120
121			`// dst: memory, src: reg`
122			`IF(rd_modregrm_mod != 2'b11);`
123
124			`SET(rd_dst_is_memory);`
125
126			`SET(rd_req_memory);`
127
128			`IF(rd_mutex_busy_modregrm_reg); SET(rd_waiting);`
129			`ELSE();`
130			`SET(write_virtual_check);`
131
132			`IF(~(write_virtual_check_ready)); SET(rd_waiting); ENDIF();`
133			`ENDIF();`
134			`ENDIF();`
135			`ENDIF();`
136
137
138
139			IF(rd_cmd == `CMD_MOV && rd_cmdex == `CMDEX_MOV_modregrm_imm);
140
141			`SET(rd_src_is_modregrm_imm);`
142
143			`// dst: reg, src: imm`
144			`IF(rd_modregrm_mod == 2'b11);`
145
146			`SET(rd_dst_is_rm);`
147
148			`SET(rd_req_rm);`
149
150			`IF(rd_mutex_busy_modregrm_reg); SET(rd_waiting); ENDIF();`
151			`ENDIF();`
152
153			`// dst: memory, src: imm`
154			`IF(rd_modregrm_mod != 2'b11);`
155
156			`SET(rd_dst_is_memory);`
157
158			`SET(rd_req_memory);`
159
160			`IF(rd_mutex_busy_modregrm_reg); SET(rd_waiting);`
161			`ELSE();`
162			`SET(write_virtual_check);`
163
164			`IF(~(write_virtual_check_ready)); SET(rd_waiting); ENDIF();`
165			`ENDIF();`
166			`ENDIF();`
167			`ENDIF();`
168
169
170
171			IF(rd_cmd == `CMD_MOV && rd_cmdex == `CMDEX_MOV_immediate);
172
173			`SET(rd_src_is_imm);`
174			`SET(rd_dst_is_implicit_reg);`
175
176			`SET(rd_req_implicit_reg);`
177
178			`ENDIF();`
179
180
181
182			IF(exe_cmd == `CMD_MOV); // `CMDEX_MEMOFFSET \|\| `CMDEX_MODREGRM \|\| `CMDEX_MODREGRM_IMM \|\| `CMDEX_IMPLICIT
183
184			`SET(exe_result, src);`
185			`SET(exe_result2, dst);`
186
187			`ENDIF();`
188
189
190
191			IF(wr_cmd == `CMD_MOV);
192			`IF(wr_dst_is_memory && ~(write_for_wr_ready)); SET(wr_waiting); ENDIF();`
193
194			`SET(write_eax, wr_dst_is_eax);`
195			`SET(write_virtual, wr_dst_is_memory);`
196			`SET(write_regrm, wr_dst_is_reg \|\| wr_dst_is_rm \|\| wr_dst_is_implicit_reg);`
197			`ENDIF();`
198
199
200

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[/] [ao486/] [trunk/] [rtl/] [ao486/] [commands/] [CMD_MOV.txt] - Blame information for rev 2