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[/] [ao486/] [trunk/] [rtl/] [ao486/] [commands/] [CMD_RET_far.txt] - Blame information for rev 6

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Line No. Rev Author Line
1 2 alfik
 
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`define CMD_RET_far     #AUTOGEN_NEXT_CMD
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// glob_param_1[15:0]  --> new cs selector
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// glob_param_1[18:16] --> cs segment: 1
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// glob_param_2[31:0]  --> eip
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// glob_param_3 --> backup mc_param_1
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// glob_param_4 --> esp
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`define CMDEX_RET_far_STEP_1        4'd1
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`define CMDEX_RET_far_STEP_2        4'd2
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`define CMDEX_RET_far_real_STEP_3   4'd3
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`define CMDEX_RET_far_same_STEP_3   4'd4
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`define CMDEX_RET_far_same_STEP_4   4'd5
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`define CMDEX_RET_far_outer_STEP_3  4'd6
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`define CMDEX_RET_far_outer_STEP_4  4'd7
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`define CMDEX_RET_far_outer_STEP_5  4'd8
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`define CMDEX_RET_far_outer_STEP_6  4'd9
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`define CMDEX_RET_far_outer_STEP_7  4'd10
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(dec_ready_one && decoder[7:0] == 8'hCB) || (dec_ready_one_two && decoder[7:0] == 8'hCA)
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`CMD_RET_far
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SET(dec_cmdex, `CMDEX_RET_far_STEP_1);
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IF(decoder[0] == 1'b0); SET(consume_one_two); ELSE(); SET(consume_one); ENDIF();
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SET(dec_is_complex);
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`CMDEX_RET_far_STEP_1
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`CMDEX_RET_far_STEP_2
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CALL(`CMDEX_load_seg_STEP_1);
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DIRECT(`CMD_RET_far, (real_mode || v8086_mode)? `CMDEX_RET_far_real_STEP_3 : (glob_param_1[`SELECTOR_BITS_RPL] == cpl)? `CMDEX_RET_far_same_STEP_3 : `CMDEX_RET_far_outer_STEP_3);
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IF(`CMDEX_RET_far_real_STEP_3);
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    LOOP(`CMDEX_RET_far_real_STEP_3);
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ENDIF();
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IF(`CMDEX_RET_far_same_STEP_3);
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    LOOP(`CMDEX_RET_far_same_STEP_4);
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ENDIF();
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IF(`CMDEX_RET_far_outer_STEP_3);
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    `CMDEX_RET_far_outer_STEP_4
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    CALL(`CMDEX_load_seg_STEP_1);
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    `CMDEX_RET_far_outer_STEP_5
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    `CMDEX_RET_far_outer_STEP_6
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    LOOP(`CMDEX_RET_far_outer_STEP_7);
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ENDIF();
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IF(rd_cmd == `CMD_RET_far && rd_cmdex == `CMDEX_RET_far_outer_STEP_3);
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    SET(address_stack_pop_next);
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    SET(address_stack_pop_esp_prev);
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    SET(rd_glob_param_1_set, rd_ready);
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    SET(rd_glob_param_1_value, { `MC_PARAM_1_FLAG_CPL_FROM_PARAM_3, `SEGMENT_SS, read_4[15:0] }); // read ss
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    SET(rd_glob_param_3_set);
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    SET(rd_glob_param_3_value, glob_param_1);
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    SET(rd_glob_descriptor_2_set);
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    SET(rd_glob_descriptor_2_value, glob_descriptor);
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    SET(read_length_word);
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    SET(read_virtual);
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    IF(~(read_for_rd_ready)); SET(rd_waiting); ENDIF();
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ENDIF();
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IF(rd_cmd == `CMD_RET_far && rd_cmdex == `CMDEX_RET_far_STEP_1);
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    SET(address_stack_pop,       real_mode || v8086_mode);
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    SET(address_stack_pop_next,  protected_mode);
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    SET(address_stack_save);
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    SET(address_stack_for_ret_first);
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    IF(rd_mutex_busy_memory); SET(rd_waiting); // waiting for esp in 'address_waiting'
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    ELSE();
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        IF(real_mode || v8086_mode);
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            SET(rd_glob_param_2_set);
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            SET(rd_glob_param_2_value, (rd_operand_16bit)? { 16'd0, read_4[15:0] } : read_4); // read eip
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        ENDIF();
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        IF(protected_mode);
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            SET(rd_glob_param_1_set);
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            SET(rd_glob_param_1_value, { `MC_PARAM_1_FLAG_NO_WRITE, `SEGMENT_CS, read_4[15:0] }); // read cs
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        ENDIF();
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        SET(read_virtual);
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        IF(~(read_for_rd_ready)); SET(rd_waiting); ENDIF();
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    ENDIF();
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ENDIF();
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IF(rd_cmd == `CMD_RET_far && rd_cmdex == `CMDEX_RET_far_STEP_2);
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    SET(address_stack_pop_speedup,  real_mode || v8086_mode);
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    SET(address_stack_pop,          real_mode || v8086_mode);
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    SET(address_stack_pop_next,     protected_mode);
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    IF(rd_mutex_busy_memory); SET(rd_waiting); // waiting for esp in 'address_waiting'
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    ELSE();
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        IF(real_mode || v8086_mode);
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            SET(rd_glob_param_1_set);
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            SET(rd_glob_param_1_value, { `MC_PARAM_1_FLAG_NO_WRITE, `SEGMENT_CS, read_4[15:0] }); // read cs
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        ENDIF();
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        IF(protected_mode);
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            SET(rd_glob_param_2_set);
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            SET(rd_glob_param_2_value, (rd_operand_16bit)? { 16'd0, read_4[15:0] } : read_4); // read eip
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        ENDIF();
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        SET(read_virtual);
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        IF(~(read_for_rd_ready)); SET(rd_waiting); ENDIF();
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    ENDIF();
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ENDIF();
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IF(rd_cmd == `CMD_RET_far && rd_cmdex == `CMDEX_RET_far_outer_STEP_3);
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    SET(address_stack_save);
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    SET(address_stack_for_ret_second);
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ENDIF();
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IF(rd_cmd == `CMD_RET_far && rd_cmdex == `CMDEX_RET_far_outer_STEP_4);
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    SET(address_stack_pop_next);
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    SET(rd_glob_param_4_set);
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    SET(rd_glob_param_4_value, (rd_operand_16bit)? { 16'd0, read_4[15:0] } : read_4); // read esp
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    SET(read_virtual);
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    IF(~(read_for_rd_ready)); SET(rd_waiting); ENDIF();
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ENDIF();
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IF(exe_cmd == `CMD_RET_far  && exe_cmdex == `CMDEX_RET_far_STEP_1);
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    SET(offset_pop);
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ENDIF();
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IF(exe_cmd == `CMD_RET_far && exe_cmdex == `CMDEX_RET_far_STEP_2);
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    IF((v8086_mode || real_mode) && glob_param_2 > cs_limit); // protected cs null check in load_seg
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        SET(exe_waiting);
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        SET(exe_trigger_gp_fault); //exception GP(val)
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    ENDIF();
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ENDIF();
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IF(exe_cmd == `CMD_RET_far && exe_cmdex == `CMDEX_RET_far_same_STEP_3);
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    SET(offset_pop, exe_decoder[0] == 1'b1);
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    SET(offset_ret, exe_decoder[0] == 1'b0);
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    IF(glob_param_2 > glob_desc_limit);
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        SET(exe_waiting);
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        SET(exe_trigger_gp_fault); //exception GP(0)
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    ENDIF();
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ENDIF();
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IF(exe_cmd == `CMD_RET_far && exe_cmdex == `CMDEX_RET_far_outer_STEP_5);
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    IF(glob_param_2 > glob_desc_2_limit);
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        SET(exe_waiting);
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        SET(exe_trigger_gp_fault); //exception GP(0)
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    ELSE();
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        SET(exe_glob_descriptor_set);
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        SET(exe_glob_descriptor_value, glob_descriptor_2);
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        SET(exe_glob_descriptor_2_set);
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        SET(exe_glob_descriptor_2_value, glob_descriptor);
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        SET(exe_glob_param_1_set);
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        SET(exe_glob_param_1_value, glob_param_3);
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        SET(exe_glob_param_3_set);
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        SET(exe_glob_param_3_value, glob_param_1);
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    ENDIF();
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ENDIF();
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IF(exe_cmd == `CMD_RET_far && exe_cmdex == `CMDEX_RET_far_outer_STEP_6);
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    SET(exe_glob_descriptor_set, exe_ready);
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    SET(exe_glob_descriptor_value, glob_descriptor_2);
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    SET(exe_glob_descriptor_2_set, exe_ready);
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    SET(exe_glob_descriptor_2_value, glob_descriptor);
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    SET(exe_glob_param_1_set, exe_ready);
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    SET(exe_glob_param_1_value, glob_param_3);
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    SET(exe_glob_param_3_set, exe_ready);
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    SET(exe_glob_param_3_value, glob_param_1);
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ENDIF();
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IF(exe_cmd == `CMD_RET_far && exe_cmdex == `CMDEX_RET_far_outer_STEP_7);
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    SET(offset_iret_glob_param_4,   exe_decoder[0] == 1'b1);
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    SET(offset_ret_imm,             exe_decoder[0] == 1'b0);
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    SET(exe_eip_from_glob_param_2);
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    IF(exe_mutex_current[`MUTEX_ACTIVE_BIT]); SET(exe_waiting); ENDIF(); // wait for ss write
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ENDIF();
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IF(exe_cmd == `CMD_RET_far && (exe_cmdex == `CMDEX_RET_far_real_STEP_3 || exe_cmdex == `CMDEX_RET_far_same_STEP_4));
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    IF(exe_cmdex == `CMDEX_RET_far_real_STEP_3);
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        SET(offset_pop, exe_decoder[0] == 1'b1); // RET far without imm
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        SET(offset_ret, exe_decoder[0] == 1'b0); // RET far with imm
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        SET(offset_ret_far_se);
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    ENDIF();
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    SET(exe_eip_from_glob_param_2);
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ENDIF();
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IF(wr_cmd == `CMD_RET_far && wr_cmdex == `CMDEX_RET_far_STEP_1);
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    SET(wr_make_esp_speculative);
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    SAVE(esp, wr_stack_esp);
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    SET(wr_not_finished);
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ENDIF();
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IF(wr_cmd == `CMD_RET_far && wr_cmdex == `CMDEX_RET_far_STEP_2);
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    SET(wr_not_finished);
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ENDIF();
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IF(wr_cmd == `CMD_RET_far && wr_cmdex == `CMDEX_RET_far_real_STEP_3);
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    SAVE(esp, wr_stack_esp);
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    SET(wr_make_esp_commit);
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    // clear pipeline
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    SET(wr_req_reset_pr);
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    SET(wr_req_reset_dec);
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    SET(wr_req_reset_micro);
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    SET(wr_req_reset_rd);
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    SET(wr_req_reset_exe);
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ENDIF();
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IF(wr_cmd == `CMD_RET_far && wr_cmdex == `CMDEX_RET_far_outer_STEP_3);
284
    SET(wr_not_finished);
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ENDIF();
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IF(wr_cmd == `CMD_RET_far && wr_cmdex == `CMDEX_RET_far_outer_STEP_4);
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    SET(wr_not_finished);
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ENDIF();
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