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alfik |
/*
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* Copyright (c) 2014, Aleksander Osman
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* * Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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`include "defines.v"
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//PARSED_COMMENTS: this file contains parsed script comments
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module avalon_mem(
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// global
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input clk,
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input rst_n,
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//RESP:
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input writeburst_do,
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output writeburst_done,
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input [31:0] writeburst_address,
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input [1:0] writeburst_dword_length,
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input [3:0] writeburst_byteenable_0,
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input [3:0] writeburst_byteenable_1,
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input [55:0] writeburst_data,
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//END
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//RESP:
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input writeline_do,
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output writeline_done,
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input [31:0] writeline_address,
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input [127:0] writeline_line,
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//END
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//RESP:
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input readburst_do,
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output readburst_done,
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input [31:0] readburst_address,
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input [1:0] readburst_dword_length,
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input [3:0] readburst_byte_length,
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output [95:0] readburst_data,
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//END
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//RESP:
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input readline_do,
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output readline_done,
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input [31:0] readline_address,
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output [127:0] readline_line,
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//END
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//RESP:
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input readcode_do,
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output readcode_done,
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input [31:0] readcode_address,
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output [127:0] readcode_line,
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output [31:0] readcode_partial,
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output readcode_partial_done,
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//END
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// avalon master
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output reg [31:0] avm_address,
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output reg [31:0] avm_writedata,
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output reg [3:0] avm_byteenable,
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output reg [2:0] avm_burstcount,
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output reg avm_write,
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output reg avm_read,
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input avm_waitrequest,
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input avm_readdatavalid,
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input [31:0] avm_readdata
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);
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//------------------------------------------------------------------------------
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reg [31:0] bus_0;
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reg [31:0] bus_1;
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reg [31:0] bus_2;
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reg [31:0] bus_3;
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reg [3:0] byteenable_next;
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reg [1:0] counter;
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reg [1:0] state;
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reg read_burst_done_trigger;
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reg read_line_done_trigger;
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reg read_code_done_trigger;
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reg [31:0] bus_code_partial;
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//------------------------------------------------------------------------------
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localparam [1:0] STATE_IDLE = 2'd0;
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localparam [1:0] STATE_WRITE = 2'd1;
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localparam [1:0] STATE_READ = 2'd2;
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localparam [1:0] STATE_READ_CODE = 2'd3;
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//------------------------------------------------------------------------------
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assign readburst_data = { bus_2, bus_1, bus_0 };
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assign readline_line = { bus_3, bus_2, bus_1, bus_0 };
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assign readcode_line = { bus_3, bus_2, bus_1, bus_0 };
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assign readcode_partial = bus_code_partial;
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//------------------------------------------------------------------------------
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// synthesis translate_off
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wire _unused_ok = &{ 1'b0, writeburst_address[1:0], writeline_address[3:0], readline_address[3:0], readcode_address[1:0], 1'b0 };
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// synthesis translate_on
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//------------------------------------------------------------------------------
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wire [3:0] read_burst_byteenable =
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(readburst_byte_length == 4'd1 && readburst_address[1:0] == 2'd0)? 4'b0001 :
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(readburst_byte_length == 4'd1 && readburst_address[1:0] == 2'd1)? 4'b0010 :
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(readburst_byte_length == 4'd1 && readburst_address[1:0] == 2'd2)? 4'b0100 :
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(readburst_byte_length == 4'd1 && readburst_address[1:0] == 2'd3)? 4'b1000 :
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(readburst_byte_length == 4'd2 && readburst_address[1:0] == 2'd0)? 4'b0011 :
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(readburst_byte_length == 4'd2 && readburst_address[1:0] == 2'd1)? 4'b0110 :
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(readburst_byte_length == 4'd2 && readburst_address[1:0] == 2'd2)? 4'b1100 :
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(readburst_byte_length == 4'd3 && readburst_address[1:0] == 2'd0)? 4'b0111 :
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(readburst_byte_length == 4'd3 && readburst_address[1:0] == 2'd1)? 4'b1110 :
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4'b1111;
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//------------------------------------------------------------------------------
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/*******************************************************************************SCRIPT
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IF(state == STATE_IDLE);
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IF(read_burst_done_trigger);
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SET(readburst_done);
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SAVE(read_burst_done_trigger, `FALSE);
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ENDIF();
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IF(read_line_done_trigger);
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SET(readline_done);
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SAVE(read_line_done_trigger, `FALSE);
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ENDIF();
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IF(read_code_done_trigger);
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SET(readcode_done);
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SAVE(read_code_done_trigger, `FALSE);
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ENDIF();
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IF(writeburst_do);
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SAVE(avm_address, { writeburst_address[31:2], 2'd0 });
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SAVE(avm_byteenable, writeburst_byteenable_0);
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SAVE(byteenable_next, writeburst_byteenable_1);
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SAVE(avm_burstcount, { 1'b0, writeburst_dword_length });
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SAVE(avm_write, `TRUE);
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SAVE(avm_writedata, writeburst_data[31:0]);
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SAVE(bus_0, { 8'd0, writeburst_data[55:32] });
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SET(writeburst_done);
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SAVE(counter, writeburst_dword_length - 2'd1);
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SAVE(state, STATE_WRITE);
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ELSE_IF(writeline_do);
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SAVE(avm_address, { writeline_address[31:4], 4'd0 });
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SAVE(avm_byteenable, 4'hF);
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SAVE(byteenable_next, 4'hF);
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SAVE(avm_burstcount, 3'd4);
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SAVE(avm_write, `TRUE);
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SAVE(avm_writedata, writeline_line[31:0]);
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SAVE(bus_0, writeline_line[63:32]);
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SAVE(bus_1, writeline_line[95:64]);
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SAVE(bus_2, writeline_line[127:96]);
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SET(writeline_done);
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SAVE(counter, 2'd3);
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SAVE(state, STATE_WRITE);
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ELSE_IF(readburst_do && ~(readburst_done));
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SAVE(avm_address, { readburst_address[31:2], 2'd0 });
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SAVE(avm_byteenable, read_burst_byteenable);
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SAVE(avm_burstcount, { 1'b0, readburst_dword_length });
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SAVE(avm_read, `TRUE);
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SAVE(counter, readburst_dword_length - 2'd1);
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SAVE(state, STATE_READ);
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ELSE_IF(readline_do && ~(readline_done));
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SAVE(avm_address, { readline_address[31:4], 4'd0 });
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SAVE(avm_byteenable, 4'hF);
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SAVE(avm_burstcount, 3'd4);
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SAVE(avm_read, `TRUE);
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SAVE(counter, 2'd3);
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SAVE(state, STATE_READ);
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ELSE_IF(readcode_do && ~(readcode_done));
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SAVE(avm_address, { readcode_address[31:2], 2'd0 });
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SAVE(avm_byteenable, 4'hF);
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SAVE(avm_burstcount, 3'd4);
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SAVE(avm_read, `TRUE);
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SAVE(counter, 2'd3);
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SAVE(state, STATE_READ_CODE);
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ENDIF();
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ENDIF();
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*/
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/*******************************************************************************SCRIPT
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IF(state == STATE_WRITE);
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IF(~(avm_waitrequest) && counter == 2'd0);
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SAVE(avm_write, `FALSE);
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SAVE(state, STATE_IDLE);
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ENDIF();
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IF(~(avm_waitrequest) && counter != 2'd0);
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SAVE(avm_writedata, bus_0);
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SAVE(bus_0, bus_1);
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SAVE(bus_1, bus_2);
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SAVE(avm_byteenable, byteenable_next);
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SAVE(counter, counter - 2'd1);
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ENDIF();
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ENDIF();
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*/
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/*******************************************************************************SCRIPT
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IF(state == STATE_READ);
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IF(avm_readdatavalid);
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IF(avm_burstcount - { 1'b0, counter } == 3'd1); SAVE(bus_0, avm_readdata); ENDIF();
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IF(avm_burstcount - { 1'b0, counter } == 3'd2); SAVE(bus_1, avm_readdata); ENDIF();
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IF(avm_burstcount - { 1'b0, counter } == 3'd3); SAVE(bus_2, avm_readdata); ENDIF();
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IF(avm_burstcount - { 1'b0, counter } == 3'd4); SAVE(bus_3, avm_readdata); ENDIF();
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SAVE(counter, counter - 2'd1);
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IF(counter == 2'd0);
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IF(avm_burstcount == 3'd4); SAVE(read_line_done_trigger, `TRUE);
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ELSE(); SAVE(read_burst_done_trigger,`TRUE);
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ENDIF();
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SAVE(avm_read, `FALSE);
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SAVE(state, STATE_IDLE);
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ENDIF();
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ENDIF();
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IF(avm_waitrequest == `FALSE);
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SAVE(avm_read, `FALSE);
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ENDIF();
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ENDIF();
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*/
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/*******************************************************************************SCRIPT
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IF(state == STATE_READ_CODE);
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IF(avm_readdatavalid);
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SAVE(bus_code_partial, avm_readdata);
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IF(counter == 2'd3); SAVE(bus_0, avm_readdata); ENDIF();
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IF(counter == 2'd2); SAVE(bus_1, avm_readdata); ENDIF();
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IF(counter == 2'd1); SAVE(bus_2, avm_readdata); ENDIF();
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IF(counter == 2'd0); SAVE(bus_3, avm_readdata); ENDIF();
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SAVE(counter, counter - 2'd1);
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IF(counter < 2'd3); SET(readcode_partial_done); ENDIF();
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IF(counter == 2'd0);
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SAVE(read_code_done_trigger, `TRUE);
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SAVE(avm_read, `FALSE);
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SAVE(state, STATE_IDLE);
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ENDIF();
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ENDIF();
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IF(avm_waitrequest == `FALSE);
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SAVE(avm_read, `FALSE);
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ENDIF();
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ENDIF();
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*/
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//------------------------------------------------------------------------------
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`include "autogen/avalon_mem.v"
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endmodule
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