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alfik |
/*
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* Copyright (c) 2014, Aleksander Osman
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* * Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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`include "defines.v"
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module cache_data_ram(
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input clk,
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input rst_n,
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input [31:0] address,
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//RESP:
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input read_do,
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output [147:0] q,
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//END
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//RESP:
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input write_do,
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input [127:0] data
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//END
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);
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//------------------------------------------------------------------------------
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reg [7:0] last_address;
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//------------------------------------------------------------------------------
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) last_address <= 8'd0;
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else if(read_do) last_address <= address[11:4];
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end
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//------------------------------------------------------------------------------
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// port a: q - 20 bit tag + 128 bit data = 148 bits
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simple_ram #(
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.width (148),
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.widthad (8)
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)
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cache_data_ram_inst(
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.clk (clk), //input
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.wraddress (address[11:4]), //input [7:0]
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.wren (write_do), //input
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.data ({ address[31:12], data }), //input [147:0]
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.rdaddress ((read_do)? address[11:4] : last_address), //input [7:0]
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.q (q) //output [147:0]
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);
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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// synthesis translate_off
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wire _unused_ok = &{ 1'b0, address[3:0], 1'b0 };
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// synthesis translate_on
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//------------------------------------------------------------------------------
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endmodule
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