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[/] [ao486/] [trunk/] [rtl/] [ao486/] [memory/] [link_dcacheread.v] - Blame information for rev 2

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1 2 alfik
/*
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 * Copyright (c) 2014, Aleksander Osman
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions are met:
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 *
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 * * Redistributions of source code must retain the above copyright notice, this
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 *   list of conditions and the following disclaimer.
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 *
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 * * Redistributions in binary form must reproduce the above copyright notice,
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 *   this list of conditions and the following disclaimer in the documentation
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 *   and/or other materials provided with the distribution.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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`include "defines.v"
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//TYPE: full save
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module link_dcacheread(
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    input               clk,
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    input               rst_n,
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    // dcacheread REQ
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    input               req_dcacheread_do,
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    output              req_dcacheread_done,
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    input   [3:0]       req_dcacheread_length,
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    input               req_dcacheread_cache_disable,
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    input   [31:0]      req_dcacheread_address,
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    output  [63:0]      req_dcacheread_data,
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    // dcacheread RESP
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    output              resp_dcacheread_do,
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    input               resp_dcacheread_done,
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    output  [3:0]       resp_dcacheread_length,
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    output              resp_dcacheread_cache_disable,
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    output  [31:0]      resp_dcacheread_address,
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    input   [63:0]      resp_dcacheread_data
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);
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//------------------------------------------------------------------------------
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reg         current_do;
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reg [3:0]   length;
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reg         cache_disable;
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reg [31:0]  address;
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//------------------------------------------------------------------------------
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wire save;
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//------------------------------------------------------------------------------
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assign save  = req_dcacheread_do && ~(resp_dcacheread_done);
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//------------------------------------------------------------------------------
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always @(posedge clk or negedge rst_n) begin
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    if(rst_n == 1'b0)               current_do <= `FALSE;
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    else if(save)                   current_do <= req_dcacheread_do;
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    else if(resp_dcacheread_done)   current_do <= `FALSE;
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end
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always @(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) length        <= 4'd0;  else if(save) length        <= req_dcacheread_length;        end
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always @(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) cache_disable <= 1'b0;  else if(save) cache_disable <= req_dcacheread_cache_disable; end
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always @(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) address       <= 32'd0; else if(save) address       <= req_dcacheread_address;       end
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//------------------------------------------------------------------------------
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assign req_dcacheread_done = resp_dcacheread_done;
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assign req_dcacheread_data = resp_dcacheread_data;
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assign resp_dcacheread_do            = (req_dcacheread_do)? req_dcacheread_do            : current_do;
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assign resp_dcacheread_length        = (req_dcacheread_do)? req_dcacheread_length        : length;
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assign resp_dcacheread_cache_disable = (req_dcacheread_do)? req_dcacheread_cache_disable : cache_disable;
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assign resp_dcacheread_address       = (req_dcacheread_do)? req_dcacheread_address       : address;
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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endmodule

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