OpenCores
URL https://opencores.org/ocsvn/ao486/ao486/trunk

Subversion Repositories ao486

[/] [ao486/] [trunk/] [rtl/] [ao486/] [memory/] [prefetch_control.v] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 alfik
/*
2
 * Copyright (c) 2014, Aleksander Osman
3
 * All rights reserved.
4
 *
5
 * Redistribution and use in source and binary forms, with or without
6
 * modification, are permitted provided that the following conditions are met:
7
 *
8
 * * Redistributions of source code must retain the above copyright notice, this
9
 *   list of conditions and the following disclaimer.
10
 *
11
 * * Redistributions in binary form must reproduce the above copyright notice,
12
 *   this list of conditions and the following disclaimer in the documentation
13
 *   and/or other materials provided with the distribution.
14
 *
15
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
19
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
22
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
23
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
24
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25
 */
26
 
27
`include "defines.v"
28
 
29
//PARSED_COMMENTS: this file contains parsed script comments
30
 
31
module prefetch_control(
32
    input           clk,
33
    input           rst_n,
34
 
35
    input           pr_reset, //same as reset to icache
36
 
37
    //from prefetch
38
    input   [31:0]  prefetch_address,
39
    input   [4:0]   prefetch_length,
40
    input           prefetch_su,
41
 
42
    //from prefetchfifo
43
    input   [4:0]   prefetchfifo_used,
44
 
45
    //REQ:
46
    output          tlbcoderequest_do,
47
    output  [31:0]  tlbcoderequest_address,
48
    output          tlbcoderequest_su,
49
    //END
50
 
51
    //RESP:
52
    input           tlbcode_do,
53
    input   [31:0]  tlbcode_linear,
54
    input   [31:0]  tlbcode_physical,
55
    input           tlbcode_cache_disable,
56
    //END
57
 
58
    //REQ:
59
    output          icacheread_do,
60
    output  [31:0]  icacheread_address,
61
    output  [4:0]   icacheread_length, // takes into account: page size and cs segment limit
62
    output          icacheread_cache_disable
63
    //END
64
);
65
 
66
//------------------------------------------------------------------------------
67
 
68
reg [1:0]  state;
69
reg [31:0] linear;
70
reg [31:0] physical;
71
reg        cache_disable;
72
 
73
//------------------------------------------------------------------------------
74
 
75
localparam [1:0] STATE_TLB_REQUEST = 2'd0;
76
localparam [1:0] STATE_ICACHE      = 2'd1;
77
 
78
//------------------------------------------------------------------------------
79
 
80
wire [12:0] left_in_page;
81
wire [4:0]  length;
82
 
83
wire        offset_update;
84
wire        page_cross;
85
 
86
//------------------------------------------------------------------------------
87
 
88
assign tlbcoderequest_address = prefetch_address;
89
assign tlbcoderequest_su      = prefetch_su;
90
 
91
assign left_in_page = 13'd4096 - { 1'b0, prefetch_address[11:0] };
92
assign length       = (left_in_page < { 8'd0, prefetch_length })?  left_in_page[4:0] : prefetch_length;
93
 
94
assign offset_update = prefetch_address[31:12] == linear[31:12] && prefetch_address[11:0] != linear[11:0];
95
assign page_cross    = prefetch_address[31:12] != linear[31:12];
96
 
97
//------------------------------------------------------------------------------
98
 
99
//------------------------------------------------------------------------------
100
 
101
//------------------------------------------------------------------------------
102
 
103
//------------------------------------------------------------------------------
104
 
105
/*******************************************************************************SCRIPT
106
 
107
IF(state == STATE_TLB_REQUEST);
108
 
109
    IF(~(pr_reset) && prefetch_length > 5'd0 && prefetchfifo_used < 5'd3);
110
 
111
        SET(tlbcoderequest_do);
112
 
113
        IF(tlbcode_do);
114
 
115
            SAVE(linear,        tlbcode_linear);
116
            SAVE(physical,      tlbcode_physical);
117
            SAVE(cache_disable, tlbcode_cache_disable);
118
 
119
            SET(icacheread_do);
120
            SET(icacheread_address,       tlbcode_physical);
121
            SET(icacheread_length,        length);
122
            SET(icacheread_cache_disable, tlbcode_cache_disable);
123
 
124
            SAVE(state, STATE_ICACHE);
125
        ENDIF();
126
    ENDIF();
127
ENDIF();
128
 
129
*/
130
 
131
/*******************************************************************************SCRIPT
132
 
133
IF(state == STATE_ICACHE);
134
 
135
    IF(page_cross || pr_reset || prefetchfifo_used >= 5'd8);
136
        SAVE(state, STATE_TLB_REQUEST);
137
    ELSE();
138
        SET(icacheread_do);
139
    ENDIF();
140
 
141
    SET(icacheread_address,       (offset_update)? { physical[31:12], prefetch_address[11:0] } : physical);
142
    SET(icacheread_length,        length);
143
    SET(icacheread_cache_disable, cache_disable);
144
 
145
    IF(offset_update);
146
        SAVE(linear,   { linear[31:12],   prefetch_address[11:0] });
147
        SAVE(physical, { physical[31:12], prefetch_address[11:0] });
148
    ENDIF();
149
ENDIF();
150
*/
151
 
152
 
153
//------------------------------------------------------------------------------
154
 
155
//------------------------------------------------------------------------------
156
 
157
//------------------------------------------------------------------------------
158
 
159
`include "autogen/prefetch_control.v"
160
 
161
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.