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/*
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* Copyright (c) 2014, Aleksander Osman
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* * Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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`include "defines.v"
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//PARSED_COMMENTS: this file contains parsed script comments
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module prefetch_control(
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input clk,
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input rst_n,
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input pr_reset, //same as reset to icache
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//from prefetch
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input [31:0] prefetch_address,
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input [4:0] prefetch_length,
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input prefetch_su,
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//from prefetchfifo
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input [4:0] prefetchfifo_used,
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//REQ:
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output tlbcoderequest_do,
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output [31:0] tlbcoderequest_address,
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output tlbcoderequest_su,
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//END
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//RESP:
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input tlbcode_do,
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input [31:0] tlbcode_linear,
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input [31:0] tlbcode_physical,
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input tlbcode_cache_disable,
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//END
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//REQ:
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output icacheread_do,
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output [31:0] icacheread_address,
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output [4:0] icacheread_length, // takes into account: page size and cs segment limit
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output icacheread_cache_disable
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//END
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);
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//------------------------------------------------------------------------------
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reg [1:0] state;
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reg [31:0] linear;
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reg [31:0] physical;
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reg cache_disable;
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//------------------------------------------------------------------------------
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localparam [1:0] STATE_TLB_REQUEST = 2'd0;
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localparam [1:0] STATE_ICACHE = 2'd1;
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//------------------------------------------------------------------------------
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wire [12:0] left_in_page;
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wire [4:0] length;
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wire offset_update;
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wire page_cross;
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//------------------------------------------------------------------------------
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assign tlbcoderequest_address = prefetch_address;
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assign tlbcoderequest_su = prefetch_su;
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assign left_in_page = 13'd4096 - { 1'b0, prefetch_address[11:0] };
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assign length = (left_in_page < { 8'd0, prefetch_length })? left_in_page[4:0] : prefetch_length;
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assign offset_update = prefetch_address[31:12] == linear[31:12] && prefetch_address[11:0] != linear[11:0];
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assign page_cross = prefetch_address[31:12] != linear[31:12];
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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/*******************************************************************************SCRIPT
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IF(state == STATE_TLB_REQUEST);
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IF(~(pr_reset) && prefetch_length > 5'd0 && prefetchfifo_used < 5'd3);
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SET(tlbcoderequest_do);
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IF(tlbcode_do);
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SAVE(linear, tlbcode_linear);
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SAVE(physical, tlbcode_physical);
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SAVE(cache_disable, tlbcode_cache_disable);
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SET(icacheread_do);
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SET(icacheread_address, tlbcode_physical);
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SET(icacheread_length, length);
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SET(icacheread_cache_disable, tlbcode_cache_disable);
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SAVE(state, STATE_ICACHE);
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ENDIF();
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ENDIF();
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ENDIF();
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*/
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/*******************************************************************************SCRIPT
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IF(state == STATE_ICACHE);
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IF(page_cross || pr_reset || prefetchfifo_used >= 5'd8);
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SAVE(state, STATE_TLB_REQUEST);
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ELSE();
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SET(icacheread_do);
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ENDIF();
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SET(icacheread_address, (offset_update)? { physical[31:12], prefetch_address[11:0] } : physical);
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SET(icacheread_length, length);
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SET(icacheread_cache_disable, cache_disable);
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IF(offset_update);
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SAVE(linear, { linear[31:12], prefetch_address[11:0] });
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SAVE(physical, { physical[31:12], prefetch_address[11:0] });
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ENDIF();
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ENDIF();
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*/
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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`include "autogen/prefetch_control.v"
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endmodule
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