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[/] [ao486/] [trunk/] [rtl/] [ao486/] [pipeline/] [decode_prefix.v] - Blame information for rev 2

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/*
 * Copyright (c) 2014, Aleksander Osman
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *
 * * Redistributions of source code must retain the above copyright notice, this
 *   list of conditions and the following disclaimer.
 *
 * * Redistributions in binary form must reproduce the above copyright notice,
 *   this list of conditions and the following disclaimer in the documentation
 *   and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
module decode_prefix(
    input               clk,
    input               rst_n,
 
    input       [63:0]  cs_cache,
    input               dec_is_modregrm,
    input       [95:0]  decoder,
 
    input               instr_prefix,
    input               instr_finished,
 
    output              dec_operand_32bit,
    output              dec_address_32bit,
 
    output reg  [1:0]   dec_prefix_group_1_rep,
    output              dec_prefix_group_1_lock,
    output      [2:0]   dec_prefix_group_2_seg,
 
    output reg          dec_prefix_2byte,
    output      [2:0]   dec_modregrm_len,
 
    output reg  [3:0]   prefix_count,
    output              is_prefix,
    output reg          prefix_group_1_lock
);
 
//------------------------------------------------------------------------------
 
 
reg [2:0]   prefix_group_2;
reg         prefix_group_3;
reg         prefix_group_4;
 
//------------------------------------------------------------------------------
 
wire        modregrm_ss_selected;
wire        CRx_DRx_condition;
 
wire        dec_address_16bit;
 
//------------------------------------------------------------------------------
 
/*
group 1:
1: F2H    REPNE/REPNZ prefix (used only with string instructions)
2: F3H    REP prefix (used only with string instructions)
 
group 1 lock:
1: F0H   LOCK prefix
 
group 2:
0: 26H    ES segment override prefix
1: 2EH    CS segment override prefix
2: 36H    SS segment override prefix
3: 3EH    DS segment override prefix
4: 64H    FS segment override prefix
5: 65H    GS segment override prefix
 
group 3:
1: 66H    Operand-size override
 
group 4:
1: 67H    Address-size override
*/
 
//------------------------------------------------------------------------------
 
assign dec_operand_32bit = cs_cache[`DESC_BIT_D_B] ^ prefix_group_3;
 
assign dec_address_32bit = cs_cache[`DESC_BIT_D_B] ^ prefix_group_4;
assign dec_address_16bit = ~dec_address_32bit;
 
assign dec_modregrm_len =
    (CRx_DRx_condition)?                                                                                    3'd2 :
    (dec_address_16bit && decoder[15:14] == 2'b00 && decoder[10:8] == 3'b110)?                              3'd4 :
    (dec_address_16bit && decoder[15:14] == 2'b01)?                                                         3'd3 :
    (dec_address_16bit && decoder[15:14] == 2'b10)?                                                         3'd4 :
    (dec_address_16bit)?                                                                                    3'd2 :
    (dec_address_32bit && decoder[15:14] == 2'b00 && decoder[10:8] == 3'b101)?                              3'd6 :
    (dec_address_32bit && decoder[15:14] == 2'b00 && decoder[10:8] == 3'b100 && decoder[18:16] == 3'b101)?  3'd7 :
    (dec_address_32bit && decoder[15:14] == 2'b00 && decoder[10:8] == 3'b100)?                              3'd3 :
 
    (dec_address_32bit && decoder[15:14] == 2'b01 && decoder[10:8] == 3'b100)?                              3'd4 :
    (dec_address_32bit && decoder[15:14] == 2'b01)?                                                         3'd3 :
 
    (dec_address_32bit && decoder[15:14] == 2'b10 && decoder[10:8] == 3'b100)?                              3'd7 :
    (dec_address_32bit && decoder[15:14] == 2'b10)?                                                         3'd6 :
                                                                                                            3'd2;
assign is_prefix =
    decoder[7:0] == 8'hF2 || decoder[7:0] == 8'hF3 || decoder[7:0] == 8'hF0 || decoder[7:0] == 8'h26 ||
    decoder[7:0] == 8'h2E || decoder[7:0] == 8'h36 || decoder[7:0] == 8'h3E || decoder[7:0] == 8'h64 ||
    decoder[7:0] == 8'h65 || decoder[7:0] == 8'h66 || decoder[7:0] == 8'h67 || decoder[7:0] == 8'h0F;
 
//------------------------------------------------------------------------------
 
 
always @(posedge clk or negedge rst_n) begin
    if(rst_n == 1'b0)                               dec_prefix_group_1_rep <= 2'd0;
    else if(instr_finished)                         dec_prefix_group_1_rep <= 2'd0;
    else if(instr_prefix && decoder[7:0] == 8'hF2)  dec_prefix_group_1_rep <= 2'd1;
    else if(instr_prefix && decoder[7:0] == 8'hF3)  dec_prefix_group_1_rep <= 2'd2;
end
 
always @(posedge clk or negedge rst_n) begin
    if(rst_n == 1'b0)                               prefix_group_1_lock <= 1'd0;
    else if(instr_finished)                         prefix_group_1_lock <= 1'd0;
    else if(instr_prefix && decoder[7:0] == 8'hF0)  prefix_group_1_lock <= 1'd1;
end
 
 
always @(posedge clk or negedge rst_n) begin
    if(rst_n == 1'b0)                               prefix_group_2 <= 3'd7;
    else if(instr_finished)                         prefix_group_2 <= 3'd7;
    else if(instr_prefix && decoder[7:0] == 8'h26)  prefix_group_2 <= 3'd0;
    else if(instr_prefix && decoder[7:0] == 8'h2E)  prefix_group_2 <= 3'd1;
    else if(instr_prefix && decoder[7:0] == 8'h36)  prefix_group_2 <= 3'd2;
    else if(instr_prefix && decoder[7:0] == 8'h3E)  prefix_group_2 <= 3'd3;
    else if(instr_prefix && decoder[7:0] == 8'h64)  prefix_group_2 <= 3'd4;
    else if(instr_prefix && decoder[7:0] == 8'h65)  prefix_group_2 <= 3'd5;
end
 
always @(posedge clk or negedge rst_n) begin
    if(rst_n == 1'b0)                               prefix_group_3 <= 1'd0;
    else if(instr_finished)                         prefix_group_3 <= 1'd0;
    else if(instr_prefix && decoder[7:0] == 8'h66)  prefix_group_3 <= 1'd1;
end
 
always @(posedge clk or negedge rst_n) begin
    if(rst_n == 1'b0)                               prefix_group_4 <= 1'd0;
    else if(instr_finished)                         prefix_group_4 <= 1'd0;
    else if(instr_prefix && decoder[7:0] == 8'h67)  prefix_group_4 <= 1'd1;
end
 
always @(posedge clk or negedge rst_n) begin
    if(rst_n == 1'b0)                               dec_prefix_2byte <= 1'd0;
    else if(instr_finished)                         dec_prefix_2byte <= 1'd0;
    else if(instr_prefix && decoder[7:0] == 8'h0F)  dec_prefix_2byte <= 1'd1;
end
 
always @(posedge clk or negedge rst_n) begin
    if(rst_n == 1'b0)       prefix_count <= 4'd0;
    else if(instr_finished) prefix_count <= 4'd0;
    else if(instr_prefix)   prefix_count <= prefix_count + 4'd1;
end
 
//------------------------------------------------------------------------------
 
// XCHG always has LOCK
assign dec_prefix_group_1_lock =
    prefix_group_1_lock ||
    (~(dec_prefix_2byte) && { decoder[7:1], 1'b0 } == 8'h86 && decoder[15:14] != 2'b11);
 
// mod bits are always 2'b11
assign CRx_DRx_condition = dec_prefix_2byte && { decoder[7:2], 2'b00 } == 8'h20;
 
// modregrm using esp or ebp
assign modregrm_ss_selected = dec_is_modregrm && ~(CRx_DRx_condition) &&
(   (dec_address_32bit && (decoder[15:14] == 2'b01 || decoder[15:14] == 2'b10) &&  decoder[10:8]  == 3'b101) ||
    (dec_address_32bit &&  decoder[15:14] != 2'b11 && decoder[10:8]  == 3'b100 &&  decoder[18:16] == 3'b100) ||
    (dec_address_32bit && (decoder[15:14] == 2'b01 || decoder[15:14] == 2'b10) &&  decoder[10:8]  == 3'b100 && decoder[18:16] == 3'b101) ||
    (dec_address_16bit &&  decoder[15:14] == 2'b00 && decoder[10:9]  == 2'b01) ||
    (dec_address_16bit && (decoder[15:14] == 2'b01 || decoder[15:14] == 2'b10) && (decoder[10:9]  == 2'b01 || decoder[10:8] == 3'b110))
);
 
assign dec_prefix_group_2_seg =
    (prefix_group_2 == 3'd7 && modregrm_ss_selected)?   3'd2 :
    (prefix_group_2 == 3'd7)?                           3'd3 :
                                                        prefix_group_2;
 
//------------------------------------------------------------------------------
 
// synthesis translate_off
wire _unused_ok = &{ 1'b0, cs_cache[63:55], cs_cache[53:0], decoder[95:19], decoder[13:11], 1'b0 };
// synthesis translate_on
 
//------------------------------------------------------------------------------
 
endmodule

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[/] [ao486/] [trunk/] [rtl/] [ao486/] [pipeline/] [decode_prefix.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	alfik	`/*`
2			`* Copyright (c) 2014, Aleksander Osman`
3			`* All rights reserved.`
4			`*`
5			`* Redistribution and use in source and binary forms, with or without`
6			`* modification, are permitted provided that the following conditions are met:`
7			`*`
8			`* * Redistributions of source code must retain the above copyright notice, this`
9			`* list of conditions and the following disclaimer.`
10			`*`
11			`* * Redistributions in binary form must reproduce the above copyright notice,`
12			`* this list of conditions and the following disclaimer in the documentation`
13			`* and/or other materials provided with the distribution.`
14			`*`
15			`* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"`
16			`* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE`
17			`* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE`
18			`* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE`
19			`* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL`
20			`* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR`
21			`* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER`
22			`* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,`
23			`* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE`
24			`* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.`
25			`*/`
26
27			`module decode_prefix(`
28			`input clk,`
29			`input rst_n,`
30
31			`input [63:0] cs_cache,`
32			`input dec_is_modregrm,`
33			`input [95:0] decoder,`
34
35			`input instr_prefix,`
36			`input instr_finished,`
37
38			`output dec_operand_32bit,`
39			`output dec_address_32bit,`
40
41			`output reg [1:0] dec_prefix_group_1_rep,`
42			`output dec_prefix_group_1_lock,`
43			`output [2:0] dec_prefix_group_2_seg,`
44
45			`output reg dec_prefix_2byte,`
46			`output [2:0] dec_modregrm_len,`
47
48			`output reg [3:0] prefix_count,`
49			`output is_prefix,`
50			`output reg prefix_group_1_lock`
51			`);`
52
53			`//------------------------------------------------------------------------------`
54
55
56			`reg [2:0] prefix_group_2;`
57			`reg prefix_group_3;`
58			`reg prefix_group_4;`
59
60			`//------------------------------------------------------------------------------`
61
62			`wire modregrm_ss_selected;`
63			`wire CRx_DRx_condition;`
64
65			`wire dec_address_16bit;`
66
67			`//------------------------------------------------------------------------------`
68
69			`/*`
70			`group 1:`
71			`1: F2H REPNE/REPNZ prefix (used only with string instructions)`
72			`2: F3H REP prefix (used only with string instructions)`
73
74			`group 1 lock:`
75			`1: F0H LOCK prefix`
76
77			`group 2:`
78			`0: 26H ES segment override prefix`
79			`1: 2EH CS segment override prefix`
80			`2: 36H SS segment override prefix`
81			`3: 3EH DS segment override prefix`
82			`4: 64H FS segment override prefix`
83			`5: 65H GS segment override prefix`
84
85			`group 3:`
86			`1: 66H Operand-size override`
87
88			`group 4:`
89			`1: 67H Address-size override`
90			`*/`
91
92			`//------------------------------------------------------------------------------`
93
94			assign dec_operand_32bit = cs_cache[`DESC_BIT_D_B] ^ prefix_group_3;
95
96			assign dec_address_32bit = cs_cache[`DESC_BIT_D_B] ^ prefix_group_4;
97			`assign dec_address_16bit = ~dec_address_32bit;`
98
99			`assign dec_modregrm_len =`
100			`(CRx_DRx_condition)? 3'd2 :`
101			`(dec_address_16bit && decoder[15:14] == 2'b00 && decoder[10:8] == 3'b110)? 3'd4 :`
102			`(dec_address_16bit && decoder[15:14] == 2'b01)? 3'd3 :`
103			`(dec_address_16bit && decoder[15:14] == 2'b10)? 3'd4 :`
104			`(dec_address_16bit)? 3'd2 :`
105			`(dec_address_32bit && decoder[15:14] == 2'b00 && decoder[10:8] == 3'b101)? 3'd6 :`
106			`(dec_address_32bit && decoder[15:14] == 2'b00 && decoder[10:8] == 3'b100 && decoder[18:16] == 3'b101)? 3'd7 :`
107			`(dec_address_32bit && decoder[15:14] == 2'b00 && decoder[10:8] == 3'b100)? 3'd3 :`
108
109			`(dec_address_32bit && decoder[15:14] == 2'b01 && decoder[10:8] == 3'b100)? 3'd4 :`
110			`(dec_address_32bit && decoder[15:14] == 2'b01)? 3'd3 :`
111
112			`(dec_address_32bit && decoder[15:14] == 2'b10 && decoder[10:8] == 3'b100)? 3'd7 :`
113			`(dec_address_32bit && decoder[15:14] == 2'b10)? 3'd6 :`
114			`3'd2;`
115			`assign is_prefix =`
116			`decoder[7:0] == 8'hF2 \|\| decoder[7:0] == 8'hF3 \|\| decoder[7:0] == 8'hF0 \|\| decoder[7:0] == 8'h26 \|\|`
117			`decoder[7:0] == 8'h2E \|\| decoder[7:0] == 8'h36 \|\| decoder[7:0] == 8'h3E \|\| decoder[7:0] == 8'h64 \|\|`
118			`decoder[7:0] == 8'h65 \|\| decoder[7:0] == 8'h66 \|\| decoder[7:0] == 8'h67 \|\| decoder[7:0] == 8'h0F;`
119
120			`//------------------------------------------------------------------------------`
121
122
123			`always @(posedge clk or negedge rst_n) begin`
124			`if(rst_n == 1'b0) dec_prefix_group_1_rep <= 2'd0;`
125			`else if(instr_finished) dec_prefix_group_1_rep <= 2'd0;`
126			`else if(instr_prefix && decoder[7:0] == 8'hF2) dec_prefix_group_1_rep <= 2'd1;`
127			`else if(instr_prefix && decoder[7:0] == 8'hF3) dec_prefix_group_1_rep <= 2'd2;`
128			`end`
129
130			`always @(posedge clk or negedge rst_n) begin`
131			`if(rst_n == 1'b0) prefix_group_1_lock <= 1'd0;`
132			`else if(instr_finished) prefix_group_1_lock <= 1'd0;`
133			`else if(instr_prefix && decoder[7:0] == 8'hF0) prefix_group_1_lock <= 1'd1;`
134			`end`
135
136
137			`always @(posedge clk or negedge rst_n) begin`
138			`if(rst_n == 1'b0) prefix_group_2 <= 3'd7;`
139			`else if(instr_finished) prefix_group_2 <= 3'd7;`
140			`else if(instr_prefix && decoder[7:0] == 8'h26) prefix_group_2 <= 3'd0;`
141			`else if(instr_prefix && decoder[7:0] == 8'h2E) prefix_group_2 <= 3'd1;`
142			`else if(instr_prefix && decoder[7:0] == 8'h36) prefix_group_2 <= 3'd2;`
143			`else if(instr_prefix && decoder[7:0] == 8'h3E) prefix_group_2 <= 3'd3;`
144			`else if(instr_prefix && decoder[7:0] == 8'h64) prefix_group_2 <= 3'd4;`
145			`else if(instr_prefix && decoder[7:0] == 8'h65) prefix_group_2 <= 3'd5;`
146			`end`
147
148			`always @(posedge clk or negedge rst_n) begin`
149			`if(rst_n == 1'b0) prefix_group_3 <= 1'd0;`
150			`else if(instr_finished) prefix_group_3 <= 1'd0;`
151			`else if(instr_prefix && decoder[7:0] == 8'h66) prefix_group_3 <= 1'd1;`
152			`end`
153
154			`always @(posedge clk or negedge rst_n) begin`
155			`if(rst_n == 1'b0) prefix_group_4 <= 1'd0;`
156			`else if(instr_finished) prefix_group_4 <= 1'd0;`
157			`else if(instr_prefix && decoder[7:0] == 8'h67) prefix_group_4 <= 1'd1;`
158			`end`
159
160			`always @(posedge clk or negedge rst_n) begin`
161			`if(rst_n == 1'b0) dec_prefix_2byte <= 1'd0;`
162			`else if(instr_finished) dec_prefix_2byte <= 1'd0;`
163			`else if(instr_prefix && decoder[7:0] == 8'h0F) dec_prefix_2byte <= 1'd1;`
164			`end`
165
166			`always @(posedge clk or negedge rst_n) begin`
167			`if(rst_n == 1'b0) prefix_count <= 4'd0;`
168			`else if(instr_finished) prefix_count <= 4'd0;`
169			`else if(instr_prefix) prefix_count <= prefix_count + 4'd1;`
170			`end`
171
172			`//------------------------------------------------------------------------------`
173
174			`// XCHG always has LOCK`
175			`assign dec_prefix_group_1_lock =`
176			`prefix_group_1_lock \|\|`
177			`(~(dec_prefix_2byte) && { decoder[7:1], 1'b0 } == 8'h86 && decoder[15:14] != 2'b11);`
178
179			`// mod bits are always 2'b11`
180			`assign CRx_DRx_condition = dec_prefix_2byte && { decoder[7:2], 2'b00 } == 8'h20;`
181
182			`// modregrm using esp or ebp`
183			`assign modregrm_ss_selected = dec_is_modregrm && ~(CRx_DRx_condition) &&`
184			`( (dec_address_32bit && (decoder[15:14] == 2'b01 \|\| decoder[15:14] == 2'b10) && decoder[10:8] == 3'b101) \|\|`
185			`(dec_address_32bit && decoder[15:14] != 2'b11 && decoder[10:8] == 3'b100 && decoder[18:16] == 3'b100) \|\|`
186			`(dec_address_32bit && (decoder[15:14] == 2'b01 \|\| decoder[15:14] == 2'b10) && decoder[10:8] == 3'b100 && decoder[18:16] == 3'b101) \|\|`
187			`(dec_address_16bit && decoder[15:14] == 2'b00 && decoder[10:9] == 2'b01) \|\|`
188			`(dec_address_16bit && (decoder[15:14] == 2'b01 \|\| decoder[15:14] == 2'b10) && (decoder[10:9] == 2'b01 \|\| decoder[10:8] == 3'b110))`
189			`);`
190
191			`assign dec_prefix_group_2_seg =`
192			`(prefix_group_2 == 3'd7 && modregrm_ss_selected)? 3'd2 :`
193			`(prefix_group_2 == 3'd7)? 3'd3 :`
194			`prefix_group_2;`
195
196			`//------------------------------------------------------------------------------`
197
198			`// synthesis translate_off`
199			`wire _unused_ok = &{ 1'b0, cs_cache[63:55], cs_cache[53:0], decoder[95:19], decoder[13:11], 1'b0 };`
200			`// synthesis translate_on`
201
202			`//------------------------------------------------------------------------------`
203
204			`endmodule`