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/*
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* Copyright (c) 2014, Aleksander Osman
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* * Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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`include "defines.v"
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module pipeline(
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input clk,
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input rst_n,
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//to memory
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output pr_reset,
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output rd_reset,
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output exe_reset,
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output wr_reset,
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output real_mode,
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//exception
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input exc_restore_esp,
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input exc_set_rflag,
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input exc_debug_start,
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input exc_init,
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input exc_load,
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input [31:0] exc_eip,
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input [7:0] exc_vector,
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input [15:0] exc_error_code,
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input exc_push_error,
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input exc_soft_int,
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input exc_soft_int_ib,
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input exc_pf_read,
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input exc_pf_write,
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input exc_pf_code,
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input exc_pf_check,
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//pipeline eip
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output [31:0] eip,
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output [31:0] dec_eip,
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output [31:0] rd_eip,
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output [31:0] exe_eip,
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output [31:0] wr_eip,
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output [3:0] rd_consumed,
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output [3:0] exe_consumed,
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output [3:0] wr_consumed,
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//exception reset
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input exc_dec_reset,
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input exc_micro_reset,
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input exc_rd_reset,
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input exc_exe_reset,
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input exc_wr_reset,
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//global
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input [31:0] glob_param_1,
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input [31:0] glob_param_2,
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input [31:0] glob_param_3,
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input [31:0] glob_param_4,
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input [31:0] glob_param_5,
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input [63:0] glob_descriptor,
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input [63:0] glob_descriptor_2,
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input [31:0] glob_desc_base,
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input [31:0] glob_desc_limit,
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input [31:0] glob_desc_2_limit,
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//pipeline state
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output rd_dec_is_front,
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output rd_is_front,
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output exe_is_front,
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output wr_is_front,
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output pipeline_after_read_empty,
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output pipeline_after_prefetch_empty,
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//dec exceptions
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output dec_gp_fault,
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output dec_ud_fault,
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output dec_pf_fault,
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//rd exception
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output rd_io_allow_fault,
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output rd_descriptor_gp_fault,
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output rd_seg_gp_fault,
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output rd_seg_ss_fault,
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output rd_ss_esp_from_tss_fault,
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//exe exception
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output exe_bound_fault,
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output exe_trigger_gp_fault,
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output exe_trigger_ts_fault,
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output exe_trigger_ss_fault,
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output exe_trigger_np_fault,
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output exe_trigger_pf_fault,
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output exe_trigger_db_fault,
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output exe_trigger_nm_fault,
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output exe_load_seg_gp_fault,
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output exe_load_seg_ss_fault,
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output exe_load_seg_np_fault,
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output exe_div_exception,
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//wr exception
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output wr_debug_init,
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output wr_new_push_ss_fault,
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output wr_string_es_fault,
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output wr_push_ss_fault,
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//error code
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output [15:0] rd_error_code,
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output [15:0] exe_error_code,
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output [15:0] wr_error_code,
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//glob output
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output glob_descriptor_set,
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output [63:0] glob_descriptor_value,
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output glob_descriptor_2_set,
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output [63:0] glob_descriptor_2_value,
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output glob_param_1_set,
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output [31:0] glob_param_1_value,
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output glob_param_2_set,
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output [31:0] glob_param_2_value,
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output glob_param_3_set,
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output [31:0] glob_param_3_value,
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output glob_param_4_set,
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output [31:0] glob_param_4_value,
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output glob_param_5_set,
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output [31:0] glob_param_5_value,
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// prefetch
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output [1:0] prefetch_cpl,
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output [31:0] prefetch_eip,
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output [63:0] cs_cache,
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output cr0_pg,
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output cr0_wp,
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output cr0_am,
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output cr0_cd,
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output cr0_nw,
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output acflag,
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output [31:0] cr3,
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// prefetch_fifo
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output prefetchfifo_accept_do,
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input [67:0] prefetchfifo_accept_data,
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input prefetchfifo_accept_empty,
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//io_read
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output io_read_do,
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output [15:0] io_read_address,
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output [2:0] io_read_length,
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input [31:0] io_read_data,
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input io_read_done,
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//read memory
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output read_do,
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input read_done,
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input read_page_fault,
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input read_ac_fault,
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output [1:0] read_cpl,
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output [31:0] read_address,
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output [3:0] read_length,
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output read_lock,
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output read_rmw,
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input [63:0] read_data,
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//tlbcheck
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output tlbcheck_do,
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input tlbcheck_done,
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input tlbcheck_page_fault,
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output [31:0] tlbcheck_address,
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output tlbcheck_rw,
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//tlbflushsingle
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output tlbflushsingle_do,
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input tlbflushsingle_done,
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output [31:0] tlbflushsingle_address,
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//flush tlb
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output tlbflushall_do,
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//invd
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output invdcode_do,
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input invdcode_done,
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output invddata_do,
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input invddata_done,
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output wbinvddata_do,
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input wbinvddata_done,
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//interrupt
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input interrupt_do,
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output wr_interrupt_possible,
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output wr_string_in_progress_final,
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output wr_is_esp_speculative,
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//software interrupt
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output wr_int,
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output wr_int_soft_int,
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output wr_int_soft_int_ib,
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output [7:0] wr_int_vector,
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output wr_exception_external_set,
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output wr_exception_finished,
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//memory page fault
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input [31:0] tlb_code_pf_cr2,
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input [31:0] tlb_write_pf_cr2,
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input [31:0] tlb_read_pf_cr2,
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input [31:0] tlb_check_pf_cr2,
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//memory write
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output write_do,
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input write_done,
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input write_page_fault,
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input write_ac_fault,
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output [1:0] write_cpl,
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output [31:0] write_address,
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output [2:0] write_length,
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output write_lock,
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output write_rmw,
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output [31:0] write_data,
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//io write
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output io_write_do,
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output [15:0] io_write_address,
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output [2:0] io_write_length,
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output [31:0] io_write_data,
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input io_write_done
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);
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//------------------------------------------------------------------------------
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// synthesis translate_off
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wire _unused_ok = &{ 1'b0, SW[16:7], 1'b0 };
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// synthesis translate_on
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//------------------------------------------------------------------------------
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assign prefetch_cpl = cpl;
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//------------------------------------------------------------------------------ pipeline state
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wire pipeline_dec_idle;
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reg [1:0] pipeline_dec_idle_counter;
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assign pipeline_dec_idle = rd_dec_is_front && prefetchfifo_accept_empty;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) pipeline_dec_idle_counter <= 2'd0;
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else if(pipeline_dec_idle && pipeline_dec_idle_counter < 2'd3) pipeline_dec_idle_counter <= pipeline_dec_idle_counter + 2'd1;
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else if(~(pipeline_dec_idle)) pipeline_dec_idle_counter <= 2'd0;
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end
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assign pipeline_after_read_empty = rd_is_front;
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assign pipeline_after_prefetch_empty = pipeline_dec_idle && pipeline_dec_idle_counter == 2'd3;
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//------------------------------------------------------------------------------
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wire rd_glob_descriptor_set;
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wire [63:0] rd_glob_descriptor_value;
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wire rd_glob_descriptor_2_set;
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wire [63:0] rd_glob_descriptor_2_value;
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wire rd_glob_param_1_set;
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wire [31:0] rd_glob_param_1_value;
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wire rd_glob_param_2_set;
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wire [31:0] rd_glob_param_2_value;
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wire rd_glob_param_3_set;
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wire [31:0] rd_glob_param_3_value;
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wire rd_glob_param_4_set;
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wire [31:0] rd_glob_param_4_value;
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wire rd_glob_param_5_set;
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wire [31:0] rd_glob_param_5_value;
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wire exe_glob_descriptor_set;
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wire [63:0] exe_glob_descriptor_value;
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wire exe_glob_descriptor_2_set;
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wire [63:0] exe_glob_descriptor_2_value;
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wire exe_glob_param_1_set;
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wire [31:0] exe_glob_param_1_value;
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wire exe_glob_param_2_set;
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wire [31:0] exe_glob_param_2_value;
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wire exe_glob_param_3_set;
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wire [31:0] exe_glob_param_3_value;
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wire wr_glob_param_1_set;
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wire [31:0] wr_glob_param_1_value;
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wire wr_glob_param_3_set;
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wire [31:0] wr_glob_param_3_value;
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wire wr_glob_param_4_set;
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wire [31:0] wr_glob_param_4_value;
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assign glob_descriptor_set = rd_glob_descriptor_set | exe_glob_descriptor_set;
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assign glob_descriptor_value = (rd_glob_descriptor_set)? rd_glob_descriptor_value : exe_glob_descriptor_value;
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assign glob_descriptor_2_set = rd_glob_descriptor_2_set | exe_glob_descriptor_2_set;
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assign glob_descriptor_2_value = (rd_glob_descriptor_2_set)? rd_glob_descriptor_2_value : exe_glob_descriptor_2_value;
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assign glob_param_1_set = rd_glob_param_1_set | exe_glob_param_1_set | wr_glob_param_1_set;
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assign glob_param_1_value = (rd_glob_param_1_set)? rd_glob_param_1_value : (exe_glob_param_1_set)? exe_glob_param_1_value : wr_glob_param_1_value;
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assign glob_param_2_set = rd_glob_param_2_set | exe_glob_param_2_set;
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assign glob_param_2_value = (rd_glob_param_2_set)? rd_glob_param_2_value : exe_glob_param_2_value;
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assign glob_param_3_set = rd_glob_param_3_set | exe_glob_param_3_set | wr_glob_param_3_set;
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assign glob_param_3_value = (rd_glob_param_3_set)? rd_glob_param_3_value : (exe_glob_param_3_set)? exe_glob_param_3_value : wr_glob_param_3_value;
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assign glob_param_4_set = rd_glob_param_4_set | wr_glob_param_4_set;
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assign glob_param_4_value = (rd_glob_param_4_set)? rd_glob_param_4_value : wr_glob_param_4_value;
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assign glob_param_5_set = rd_glob_param_5_set;
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assign glob_param_5_value = rd_glob_param_5_value;
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//------------------------------------------------------------------------------
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352 |
|
|
|
353 |
|
|
wire wr_req_reset_pr;
|
354 |
|
|
wire wr_req_reset_dec;
|
355 |
|
|
wire wr_req_reset_micro;
|
356 |
|
|
wire wr_req_reset_rd;
|
357 |
|
|
wire wr_req_reset_exe;
|
358 |
|
|
|
359 |
|
|
wire dec_reset;
|
360 |
|
|
wire micro_reset;
|
361 |
|
|
|
362 |
|
|
assign pr_reset = wr_req_reset_pr;
|
363 |
|
|
assign dec_reset = exc_dec_reset | wr_req_reset_dec;
|
364 |
|
|
assign micro_reset = exc_micro_reset | wr_req_reset_micro;
|
365 |
|
|
assign rd_reset = exc_rd_reset | wr_req_reset_rd;
|
366 |
|
|
assign exe_reset = exc_exe_reset | wr_req_reset_exe;
|
367 |
|
|
assign wr_reset = exc_wr_reset;
|
368 |
|
|
|
369 |
|
|
//------------------------------------------------------------------------------
|
370 |
|
|
|
371 |
|
|
wire [1:0] cpl;
|
372 |
|
|
|
373 |
|
|
wire [31:0] gdtr_base;
|
374 |
|
|
wire [15:0] gdtr_limit;
|
375 |
|
|
|
376 |
|
|
wire [31:0] idtr_base;
|
377 |
|
|
wire [15:0] idtr_limit;
|
378 |
|
|
|
379 |
|
|
wire es_cache_valid;
|
380 |
|
|
wire [63:0] es_cache;
|
381 |
|
|
wire cs_cache_valid;
|
382 |
|
|
wire ss_cache_valid;
|
383 |
|
|
wire [63:0] ss_cache;
|
384 |
|
|
wire ds_cache_valid;
|
385 |
|
|
wire [63:0] ds_cache;
|
386 |
|
|
wire fs_cache_valid;
|
387 |
|
|
wire [63:0] fs_cache;
|
388 |
|
|
wire gs_cache_valid;
|
389 |
|
|
wire [63:0] gs_cache;
|
390 |
|
|
wire tr_cache_valid;
|
391 |
|
|
wire [63:0] tr_cache;
|
392 |
|
|
wire ldtr_cache_valid;
|
393 |
|
|
wire [63:0] ldtr_cache;
|
394 |
|
|
|
395 |
|
|
wire idflag;
|
396 |
|
|
wire vmflag;
|
397 |
|
|
wire rflag;
|
398 |
|
|
wire ntflag;
|
399 |
|
|
wire [1:0] iopl;
|
400 |
|
|
wire oflag;
|
401 |
|
|
wire dflag;
|
402 |
|
|
wire iflag;
|
403 |
|
|
wire tflag;
|
404 |
|
|
wire sflag;
|
405 |
|
|
wire zflag;
|
406 |
|
|
wire aflag;
|
407 |
|
|
wire pflag;
|
408 |
|
|
wire cflag;
|
409 |
|
|
|
410 |
|
|
wire cr0_ne;
|
411 |
|
|
wire cr0_ts;
|
412 |
|
|
wire cr0_em;
|
413 |
|
|
wire cr0_mp;
|
414 |
|
|
wire cr0_pe;
|
415 |
|
|
|
416 |
|
|
wire [31:0] cr2;
|
417 |
|
|
|
418 |
|
|
wire [31:0] eax;
|
419 |
|
|
wire [31:0] ebx;
|
420 |
|
|
wire [31:0] ecx;
|
421 |
|
|
wire [31:0] edx;
|
422 |
|
|
wire [31:0] esp;
|
423 |
|
|
wire [31:0] ebp;
|
424 |
|
|
wire [31:0] esi;
|
425 |
|
|
wire [31:0] edi;
|
426 |
|
|
|
427 |
|
|
wire [15:0] es;
|
428 |
|
|
wire [15:0] cs;
|
429 |
|
|
wire [15:0] ss;
|
430 |
|
|
wire [15:0] ds;
|
431 |
|
|
wire [15:0] fs;
|
432 |
|
|
wire [15:0] gs;
|
433 |
|
|
wire [15:0] ldtr;
|
434 |
|
|
wire [15:0] tr;
|
435 |
|
|
|
436 |
|
|
wire [31:0] dr0;
|
437 |
|
|
wire [31:0] dr1;
|
438 |
|
|
wire [31:0] dr2;
|
439 |
|
|
wire [31:0] dr3;
|
440 |
|
|
wire dr6_bt;
|
441 |
|
|
wire dr6_bs;
|
442 |
|
|
wire dr6_bd;
|
443 |
|
|
wire dr6_b12;
|
444 |
|
|
wire [3:0] dr6_breakpoints;
|
445 |
|
|
wire [31:0] dr7;
|
446 |
|
|
|
447 |
|
|
|
448 |
|
|
|
449 |
|
|
//------------------------------------------------------------------------------
|
450 |
|
|
|
451 |
|
|
wire [3:0] fetch_valid;
|
452 |
|
|
wire [63:0] fetch;
|
453 |
|
|
wire fetch_limit;
|
454 |
|
|
wire fetch_page_fault;
|
455 |
|
|
|
456 |
|
|
wire [3:0] dec_acceptable;
|
457 |
|
|
|
458 |
|
|
fetch fetch_inst(
|
459 |
|
|
.clk (clk),
|
460 |
|
|
.rst_n (rst_n),
|
461 |
|
|
|
462 |
|
|
.pr_reset (pr_reset),
|
463 |
|
|
|
464 |
|
|
// get prefetch_eip
|
465 |
|
|
.wr_eip (wr_eip), //input [31:0]
|
466 |
|
|
|
467 |
|
|
.prefetch_eip (prefetch_eip), //output [31:0]
|
468 |
|
|
|
469 |
|
|
// prefetch_fifo
|
470 |
|
|
.prefetchfifo_accept_do (prefetchfifo_accept_do), //output
|
471 |
|
|
.prefetchfifo_accept_data (prefetchfifo_accept_data), //input [67:0]
|
472 |
|
|
.prefetchfifo_accept_empty (prefetchfifo_accept_empty), //input
|
473 |
|
|
|
474 |
|
|
// fetch interface to decode
|
475 |
|
|
.fetch_valid (fetch_valid), //output [3:0]
|
476 |
|
|
.fetch (fetch), //output [63:0]
|
477 |
|
|
.fetch_limit (fetch_limit), //output
|
478 |
|
|
.fetch_page_fault (fetch_page_fault), //output
|
479 |
|
|
|
480 |
|
|
// feedback from decode
|
481 |
|
|
.dec_acceptable (dec_acceptable) //input [3:0]
|
482 |
|
|
);
|
483 |
|
|
|
484 |
|
|
//------------------------------------------------------------------------------
|
485 |
|
|
|
486 |
|
|
wire v8086_mode;
|
487 |
|
|
wire protected_mode;
|
488 |
|
|
|
489 |
|
|
wire micro_busy;
|
490 |
|
|
wire dec_ready;
|
491 |
|
|
|
492 |
|
|
wire [95:0] decoder;
|
493 |
|
|
wire dec_operand_32bit;
|
494 |
|
|
wire dec_address_32bit;
|
495 |
|
|
wire [1:0] dec_prefix_group_1_rep;
|
496 |
|
|
wire dec_prefix_group_1_lock;
|
497 |
|
|
wire [2:0] dec_prefix_group_2_seg;
|
498 |
|
|
wire dec_prefix_2byte;
|
499 |
|
|
wire [3:0] dec_consumed;
|
500 |
|
|
wire [2:0] dec_modregrm_len;
|
501 |
|
|
wire dec_is_8bit;
|
502 |
|
|
wire [6:0] dec_cmd;
|
503 |
|
|
wire [3:0] dec_cmdex;
|
504 |
|
|
wire dec_is_complex;
|
505 |
|
|
|
506 |
|
|
wire [6:0] micro_cmd;
|
507 |
|
|
wire [6:0] rd_cmd;
|
508 |
|
|
|
509 |
|
|
decode decode_inst(
|
510 |
|
|
.clk (clk),
|
511 |
|
|
.rst_n (rst_n),
|
512 |
|
|
|
513 |
|
|
.dec_reset (dec_reset), //input
|
514 |
|
|
|
515 |
|
|
//global input
|
516 |
|
|
.cs_cache (cs_cache), //input [63:0]
|
517 |
|
|
|
518 |
|
|
.protected_mode (protected_mode), //input
|
519 |
|
|
|
520 |
|
|
//eip
|
521 |
|
|
.pr_reset (pr_reset), //input
|
522 |
|
|
.prefetch_eip (prefetch_eip), //input [31:0]
|
523 |
|
|
.eip (eip), //output [31:0]
|
524 |
|
|
|
525 |
|
|
//fetch interface
|
526 |
|
|
.fetch_valid (fetch_valid), //input [3:0]
|
527 |
|
|
.fetch (fetch), //input [63:0]
|
528 |
|
|
.fetch_limit (fetch_limit), //input
|
529 |
|
|
.fetch_page_fault (fetch_page_fault), //input
|
530 |
|
|
|
531 |
|
|
.dec_acceptable (dec_acceptable), //output [3:0]
|
532 |
|
|
|
533 |
|
|
//exceptions
|
534 |
|
|
.dec_gp_fault (dec_gp_fault), //output
|
535 |
|
|
.dec_ud_fault (dec_ud_fault), //output
|
536 |
|
|
.dec_pf_fault (dec_pf_fault), //output
|
537 |
|
|
|
538 |
|
|
//pipeline
|
539 |
|
|
.micro_busy (micro_busy), //input
|
540 |
|
|
.dec_ready (dec_ready), //output
|
541 |
|
|
|
542 |
|
|
.decoder (decoder), //output [95:0]
|
543 |
|
|
.dec_eip (dec_eip), //output [31:0]
|
544 |
|
|
.dec_operand_32bit (dec_operand_32bit), //output
|
545 |
|
|
.dec_address_32bit (dec_address_32bit), //output
|
546 |
|
|
.dec_prefix_group_1_rep (dec_prefix_group_1_rep), //output [1:0]
|
547 |
|
|
.dec_prefix_group_1_lock (dec_prefix_group_1_lock), //output
|
548 |
|
|
.dec_prefix_group_2_seg (dec_prefix_group_2_seg), //output [2:0]
|
549 |
|
|
.dec_prefix_2byte (dec_prefix_2byte), //output
|
550 |
|
|
.dec_consumed (dec_consumed), //output [3:0]
|
551 |
|
|
.dec_modregrm_len (dec_modregrm_len), //output [2:0]
|
552 |
|
|
.dec_is_8bit (dec_is_8bit), //output
|
553 |
|
|
.dec_cmd (dec_cmd), //output [6:0]
|
554 |
|
|
.dec_cmdex (dec_cmdex), //output [3:0]
|
555 |
|
|
.dec_is_complex (dec_is_complex) //output
|
556 |
|
|
);
|
557 |
|
|
|
558 |
|
|
//------------------------------------------------------------------------------
|
559 |
|
|
|
560 |
|
|
wire [31:0] task_eip;
|
561 |
|
|
|
562 |
|
|
wire io_allow_check_needed;
|
563 |
|
|
|
564 |
|
|
wire rd_busy;
|
565 |
|
|
wire micro_ready;
|
566 |
|
|
wire [87:0] micro_decoder;
|
567 |
|
|
wire [31:0] micro_eip;
|
568 |
|
|
wire micro_operand_32bit;
|
569 |
|
|
wire micro_address_32bit;
|
570 |
|
|
wire [1:0] micro_prefix_group_1_rep;
|
571 |
|
|
wire micro_prefix_group_1_lock;
|
572 |
|
|
wire [2:0] micro_prefix_group_2_seg;
|
573 |
|
|
wire micro_prefix_2byte;
|
574 |
|
|
wire [3:0] micro_consumed;
|
575 |
|
|
wire [2:0] micro_modregrm_len;
|
576 |
|
|
wire micro_is_8bit;
|
577 |
|
|
wire [3:0] micro_cmdex;
|
578 |
|
|
|
579 |
|
|
microcode microcode_inst(
|
580 |
|
|
.clk (clk),
|
581 |
|
|
.rst_n (rst_n),
|
582 |
|
|
|
583 |
|
|
.micro_reset (micro_reset), //input
|
584 |
|
|
|
585 |
|
|
.exc_init (exc_init), //input
|
586 |
|
|
.exc_load (exc_load), //input
|
587 |
|
|
.exc_eip (exc_eip), //input [31:0]
|
588 |
|
|
|
589 |
|
|
.task_eip (task_eip), //input [31:0]
|
590 |
|
|
|
591 |
|
|
//command control
|
592 |
|
|
.real_mode (real_mode), //input
|
593 |
|
|
.v8086_mode (v8086_mode), //input
|
594 |
|
|
.protected_mode (protected_mode), //input
|
595 |
|
|
|
596 |
|
|
.io_allow_check_needed (io_allow_check_needed), //input
|
597 |
|
|
.exc_push_error (exc_push_error), //input
|
598 |
|
|
.cr0_pg (cr0_pg), //input
|
599 |
|
|
.oflag (oflag), //input
|
600 |
|
|
.ntflag (ntflag), //input
|
601 |
|
|
.cpl (cpl), //input [1:0]
|
602 |
|
|
|
603 |
|
|
.glob_param_1 (glob_param_1), //input [31:0]
|
604 |
|
|
.glob_param_3 (glob_param_3), //input [31:0]
|
605 |
|
|
.glob_descriptor (glob_descriptor), //input [63:0]
|
606 |
|
|
|
607 |
|
|
//decoder
|
608 |
|
|
.micro_busy (micro_busy), //output
|
609 |
|
|
.dec_ready (dec_ready), //input
|
610 |
|
|
|
611 |
|
|
.decoder (decoder), //input [95:0]
|
612 |
|
|
.dec_eip (dec_eip), //input [31:0]
|
613 |
|
|
.dec_operand_32bit (dec_operand_32bit), //input
|
614 |
|
|
.dec_address_32bit (dec_address_32bit), //input
|
615 |
|
|
.dec_prefix_group_1_rep (dec_prefix_group_1_rep), //input [1:0]
|
616 |
|
|
.dec_prefix_group_1_lock (dec_prefix_group_1_lock), //input
|
617 |
|
|
.dec_prefix_group_2_seg (dec_prefix_group_2_seg), //input [2:0]
|
618 |
|
|
.dec_prefix_2byte (dec_prefix_2byte), //input
|
619 |
|
|
.dec_consumed (dec_consumed), //input [3:0]
|
620 |
|
|
.dec_modregrm_len (dec_modregrm_len), //input [2:0]
|
621 |
|
|
.dec_is_8bit (dec_is_8bit), //input
|
622 |
|
|
.dec_cmd (dec_cmd), //input [6:0]
|
623 |
|
|
.dec_cmdex (dec_cmdex), //input [3:0]
|
624 |
|
|
.dec_is_complex (dec_is_complex), //input
|
625 |
|
|
|
626 |
|
|
//micro
|
627 |
|
|
.rd_busy (rd_busy), //input
|
628 |
|
|
.micro_ready (micro_ready), //output
|
629 |
|
|
|
630 |
|
|
.micro_decoder (micro_decoder), //output [87:0]
|
631 |
|
|
.micro_eip (micro_eip), //output [31:0]
|
632 |
|
|
.micro_operand_32bit (micro_operand_32bit), //output
|
633 |
|
|
.micro_address_32bit (micro_address_32bit), //output
|
634 |
|
|
.micro_prefix_group_1_rep (micro_prefix_group_1_rep), //output [1:0]
|
635 |
|
|
.micro_prefix_group_1_lock (micro_prefix_group_1_lock), //output
|
636 |
|
|
.micro_prefix_group_2_seg (micro_prefix_group_2_seg), //output [2:0]
|
637 |
|
|
.micro_prefix_2byte (micro_prefix_2byte), //output
|
638 |
|
|
.micro_consumed (micro_consumed), //output [3:0]
|
639 |
|
|
.micro_modregrm_len (micro_modregrm_len), //output [2:0]
|
640 |
|
|
.micro_is_8bit (micro_is_8bit), //output
|
641 |
|
|
.micro_cmd (micro_cmd), //output [6:0]
|
642 |
|
|
.micro_cmdex (micro_cmdex) //output [3:0]
|
643 |
|
|
);
|
644 |
|
|
|
645 |
|
|
|
646 |
|
|
//------------------------------------------------------------------------------
|
647 |
|
|
|
648 |
|
|
wire [2:0] debug_len0;
|
649 |
|
|
wire [2:0] debug_len1;
|
650 |
|
|
wire [2:0] debug_len2;
|
651 |
|
|
wire [2:0] debug_len3;
|
652 |
|
|
|
653 |
|
|
wire [10:0] exe_mutex;
|
654 |
|
|
wire [10:0] wr_mutex;
|
655 |
|
|
|
656 |
|
|
wire [31:0] wr_esp_prev;
|
657 |
|
|
|
658 |
|
|
wire exe_busy;
|
659 |
|
|
wire rd_ready;
|
660 |
|
|
wire [87:0] rd_decoder;
|
661 |
|
|
wire rd_operand_32bit;
|
662 |
|
|
wire rd_address_32bit;
|
663 |
|
|
wire [1:0] rd_prefix_group_1_rep;
|
664 |
|
|
wire rd_prefix_group_1_lock;
|
665 |
|
|
wire rd_prefix_2byte;
|
666 |
|
|
wire rd_is_8bit;
|
667 |
|
|
//wire [6:0] rd_cmd;
|
668 |
|
|
wire [3:0] rd_cmdex;
|
669 |
|
|
wire [31:0] rd_modregrm_imm;
|
670 |
|
|
wire [10:0] rd_mutex_next;
|
671 |
|
|
wire rd_dst_is_reg;
|
672 |
|
|
wire rd_dst_is_rm;
|
673 |
|
|
wire rd_dst_is_memory;
|
674 |
|
|
wire rd_dst_is_eax;
|
675 |
|
|
wire rd_dst_is_edx_eax;
|
676 |
|
|
wire rd_dst_is_implicit_reg;
|
677 |
|
|
wire [31:0] rd_extra_wire;
|
678 |
|
|
wire [31:0] rd_linear;
|
679 |
|
|
wire [3:0] rd_debug_read;
|
680 |
|
|
wire [31:0] src_wire;
|
681 |
|
|
wire [31:0] dst_wire;
|
682 |
|
|
wire [31:0] rd_address_effective;
|
683 |
|
|
|
684 |
|
|
read read_inst(
|
685 |
|
|
.clk (clk),
|
686 |
|
|
.rst_n (rst_n),
|
687 |
|
|
|
688 |
|
|
.rd_reset (rd_reset), //input
|
689 |
|
|
|
690 |
|
|
//debug input
|
691 |
|
|
.dr0 (dr0), //input [31:0]
|
692 |
|
|
.dr1 (dr1), //input [31:0]
|
693 |
|
|
.dr2 (dr2), //input [31:0]
|
694 |
|
|
.dr3 (dr3), //input [31:0]
|
695 |
|
|
.dr7 (dr7), //input [31:0]
|
696 |
|
|
|
697 |
|
|
.debug_len0 (debug_len0), //input [2:0]
|
698 |
|
|
.debug_len1 (debug_len1), //input [2:0]
|
699 |
|
|
.debug_len2 (debug_len2), //input [2:0]
|
700 |
|
|
.debug_len3 (debug_len3), //input [2:0]
|
701 |
|
|
|
702 |
|
|
//global input
|
703 |
|
|
.glob_descriptor (glob_descriptor), //input [63:0]
|
704 |
|
|
|
705 |
|
|
.glob_param_1 (glob_param_1), //input [31:0]
|
706 |
|
|
.glob_param_2 (glob_param_2), //input [31:0]
|
707 |
|
|
.glob_param_3 (glob_param_3), //input [31:0]
|
708 |
|
|
|
709 |
|
|
.glob_desc_limit (glob_desc_limit), //input [31:0]
|
710 |
|
|
.glob_desc_base (glob_desc_base), //input [31:0]
|
711 |
|
|
|
712 |
|
|
//general input
|
713 |
|
|
.gdtr_limit (gdtr_limit), //input [15:0]
|
714 |
|
|
|
715 |
|
|
.gdtr_base (gdtr_base), //input [31:0]
|
716 |
|
|
.idtr_base (idtr_base), //input [31:0]
|
717 |
|
|
|
718 |
|
|
.es_cache_valid (es_cache_valid), //input
|
719 |
|
|
.es_cache (es_cache), //input [63:0]
|
720 |
|
|
.cs_cache_valid (cs_cache_valid), //input
|
721 |
|
|
.cs_cache (cs_cache), //input [63:0]
|
722 |
|
|
.ss_cache_valid (ss_cache_valid), //input
|
723 |
|
|
.ss_cache (ss_cache), //input [63:0]
|
724 |
|
|
.ds_cache_valid (ds_cache_valid), //input
|
725 |
|
|
.ds_cache (ds_cache), //input [63:0]
|
726 |
|
|
.fs_cache_valid (fs_cache_valid), //input
|
727 |
|
|
.fs_cache (fs_cache), //input [63:0]
|
728 |
|
|
.gs_cache_valid (gs_cache_valid), //input
|
729 |
|
|
.gs_cache (gs_cache), //input [63:0]
|
730 |
|
|
.tr_cache_valid (tr_cache_valid), //input
|
731 |
|
|
.tr_cache (tr_cache), //input [63:0]
|
732 |
|
|
.tr (tr), //input [15:0]
|
733 |
|
|
.ldtr_cache_valid (ldtr_cache_valid), //input
|
734 |
|
|
.ldtr_cache (ldtr_cache), //input [63:0]
|
735 |
|
|
|
736 |
|
|
.cpl (cpl), //input [1:0]
|
737 |
|
|
|
738 |
|
|
.iopl (iopl), //input [1:0]
|
739 |
|
|
|
740 |
|
|
.cr0_pg (cr0_pg), //input
|
741 |
|
|
|
742 |
|
|
.real_mode (real_mode), //input
|
743 |
|
|
.v8086_mode (v8086_mode), //input
|
744 |
|
|
.protected_mode (protected_mode), //input
|
745 |
|
|
|
746 |
|
|
.io_allow_check_needed (io_allow_check_needed), //input
|
747 |
|
|
|
748 |
|
|
.eax (eax), //input [31:0]
|
749 |
|
|
.ebx (ebx), //input [31:0]
|
750 |
|
|
.ecx (ecx), //input [31:0]
|
751 |
|
|
.edx (edx), //input [31:0]
|
752 |
|
|
.esp (esp), //input [31:0]
|
753 |
|
|
.ebp (ebp), //input [31:0]
|
754 |
|
|
.esi (esi), //input [31:0]
|
755 |
|
|
.edi (edi), //input [31:0]
|
756 |
|
|
|
757 |
|
|
//pipeline input
|
758 |
|
|
.exe_trigger_gp_fault (exe_trigger_gp_fault), //output
|
759 |
|
|
|
760 |
|
|
.exe_mutex (exe_mutex), //input [10:0]
|
761 |
|
|
.wr_mutex (wr_mutex), //input [10:0]
|
762 |
|
|
|
763 |
|
|
.wr_esp_prev (wr_esp_prev), //input [31:0]
|
764 |
|
|
|
765 |
|
|
.exc_vector (exc_vector), //input [7:0]
|
766 |
|
|
|
767 |
|
|
//rd exception
|
768 |
|
|
.rd_io_allow_fault (rd_io_allow_fault), //output
|
769 |
|
|
.rd_error_code (rd_error_code), //output [15:0]
|
770 |
|
|
.rd_descriptor_gp_fault (rd_descriptor_gp_fault), //output
|
771 |
|
|
.rd_seg_gp_fault (rd_seg_gp_fault), //output
|
772 |
|
|
.rd_seg_ss_fault (rd_seg_ss_fault), //output
|
773 |
|
|
.rd_ss_esp_from_tss_fault (rd_ss_esp_from_tss_fault), //output
|
774 |
|
|
|
775 |
|
|
//pipeline state
|
776 |
|
|
.rd_dec_is_front (rd_dec_is_front), //output
|
777 |
|
|
.rd_is_front (rd_is_front), //output
|
778 |
|
|
|
779 |
|
|
//glob output
|
780 |
|
|
.rd_glob_descriptor_set (rd_glob_descriptor_set), //output
|
781 |
|
|
.rd_glob_descriptor_value (rd_glob_descriptor_value), //output [63:0]
|
782 |
|
|
.rd_glob_descriptor_2_set (rd_glob_descriptor_2_set), //output
|
783 |
|
|
.rd_glob_descriptor_2_value (rd_glob_descriptor_2_value), //output [63:0]
|
784 |
|
|
|
785 |
|
|
.rd_glob_param_1_set (rd_glob_param_1_set), //output
|
786 |
|
|
.rd_glob_param_1_value (rd_glob_param_1_value), //output [31:0]
|
787 |
|
|
.rd_glob_param_2_set (rd_glob_param_2_set), //output
|
788 |
|
|
.rd_glob_param_2_value (rd_glob_param_2_value), //output [31:0]
|
789 |
|
|
.rd_glob_param_3_set (rd_glob_param_3_set), //output
|
790 |
|
|
.rd_glob_param_3_value (rd_glob_param_3_value), //output [31:0]
|
791 |
|
|
.rd_glob_param_4_set (rd_glob_param_4_set), //output
|
792 |
|
|
.rd_glob_param_4_value (rd_glob_param_4_value), //output [31:0]
|
793 |
|
|
.rd_glob_param_5_set (rd_glob_param_5_set), //output
|
794 |
|
|
.rd_glob_param_5_value (rd_glob_param_5_value), //output [31:0]
|
795 |
|
|
|
796 |
|
|
//io_read
|
797 |
|
|
.io_read_do (io_read_do), //output
|
798 |
|
|
.io_read_address (io_read_address), //output [15:0]
|
799 |
|
|
.io_read_length (io_read_length), //output [2:0]
|
800 |
|
|
.io_read_data (io_read_data), //input [31:0]
|
801 |
|
|
.io_read_done (io_read_done), //input
|
802 |
|
|
|
803 |
|
|
//read memory
|
804 |
|
|
.read_do (read_do), //output
|
805 |
|
|
.read_done (read_done), //input
|
806 |
|
|
.read_page_fault (read_page_fault), //input
|
807 |
|
|
.read_ac_fault (read_ac_fault), //input
|
808 |
|
|
.read_cpl (read_cpl), //output [1:0]
|
809 |
|
|
.read_address (read_address), //output [31:0]
|
810 |
|
|
.read_length (read_length), //output [3:0]
|
811 |
|
|
.read_lock (read_lock), //output
|
812 |
|
|
.read_rmw (read_rmw), //output
|
813 |
|
|
.read_data (read_data), //input [63:0]
|
814 |
|
|
|
815 |
|
|
//micro pipeline
|
816 |
|
|
.rd_busy (rd_busy), //output
|
817 |
|
|
.micro_ready (micro_ready), //input
|
818 |
|
|
|
819 |
|
|
.micro_decoder (micro_decoder), //input [87:0]
|
820 |
|
|
.micro_eip (micro_eip), //input [31:0]
|
821 |
|
|
.micro_operand_32bit (micro_operand_32bit), //input
|
822 |
|
|
.micro_address_32bit (micro_address_32bit), //input
|
823 |
|
|
.micro_prefix_group_1_rep (micro_prefix_group_1_rep), //input [1:0]
|
824 |
|
|
.micro_prefix_group_1_lock (micro_prefix_group_1_lock), //input
|
825 |
|
|
.micro_prefix_group_2_seg (micro_prefix_group_2_seg), //input [2:0]
|
826 |
|
|
.micro_prefix_2byte (micro_prefix_2byte), //input
|
827 |
|
|
.micro_consumed (micro_consumed), //input [3:0]
|
828 |
|
|
.micro_modregrm_len (micro_modregrm_len), //input [2:0]
|
829 |
|
|
.micro_is_8bit (micro_is_8bit), //input
|
830 |
|
|
.micro_cmd (micro_cmd), //input [6:0]
|
831 |
|
|
.micro_cmdex (micro_cmdex), //input [3:0]
|
832 |
|
|
|
833 |
|
|
//rd pipeline
|
834 |
|
|
.exe_busy (exe_busy), //input
|
835 |
|
|
.rd_ready (rd_ready), //output
|
836 |
|
|
|
837 |
|
|
.rd_decoder (rd_decoder), //output [87:0]
|
838 |
|
|
.rd_eip (rd_eip), //output [31:0]
|
839 |
|
|
.rd_operand_32bit (rd_operand_32bit), //output
|
840 |
|
|
.rd_address_32bit (rd_address_32bit), //output
|
841 |
|
|
.rd_prefix_group_1_rep (rd_prefix_group_1_rep), //output [1:0]
|
842 |
|
|
.rd_prefix_group_1_lock (rd_prefix_group_1_lock), //output
|
843 |
|
|
.rd_prefix_2byte (rd_prefix_2byte), //output
|
844 |
|
|
.rd_consumed (rd_consumed), //output [3:0]
|
845 |
|
|
.rd_is_8bit (rd_is_8bit), //output
|
846 |
|
|
.rd_cmd (rd_cmd), //output [6:0]
|
847 |
|
|
.rd_cmdex (rd_cmdex), //output [3:0]
|
848 |
|
|
.rd_modregrm_imm (rd_modregrm_imm), //output [31:0]
|
849 |
|
|
.rd_mutex_next (rd_mutex_next), //output [10:0]
|
850 |
|
|
.rd_dst_is_reg (rd_dst_is_reg), //output
|
851 |
|
|
.rd_dst_is_rm (rd_dst_is_rm), //output
|
852 |
|
|
.rd_dst_is_memory (rd_dst_is_memory), //output
|
853 |
|
|
.rd_dst_is_eax (rd_dst_is_eax), //output
|
854 |
|
|
.rd_dst_is_edx_eax (rd_dst_is_edx_eax), //output
|
855 |
|
|
.rd_dst_is_implicit_reg (rd_dst_is_implicit_reg), //output
|
856 |
|
|
.rd_extra_wire (rd_extra_wire), //output [31:0]
|
857 |
|
|
.rd_linear (rd_linear), //output [31:0]
|
858 |
|
|
.rd_debug_read (rd_debug_read), //output [3:0]
|
859 |
|
|
.src_wire (src_wire), //output [31:0]
|
860 |
|
|
.dst_wire (dst_wire), //output [31:0]
|
861 |
|
|
.rd_address_effective (rd_address_effective) //output [31:0]
|
862 |
|
|
);
|
863 |
|
|
|
864 |
|
|
//------------------------------------------------------------------------------
|
865 |
|
|
|
866 |
|
|
wire [31:0] wr_stack_offset;
|
867 |
|
|
wire [1:0] wr_task_rpl;
|
868 |
|
|
|
869 |
|
|
wire dr6_bd_set;
|
870 |
|
|
|
871 |
|
|
wire [31:0] exe_buffer;
|
872 |
|
|
wire [463:0] exe_buffer_shifted;
|
873 |
|
|
|
874 |
|
|
wire wr_busy;
|
875 |
|
|
wire exe_ready;
|
876 |
|
|
wire [39:0] exe_decoder;
|
877 |
|
|
wire [31:0] exe_eip_final;
|
878 |
|
|
wire exe_operand_32bit;
|
879 |
|
|
wire exe_address_32bit;
|
880 |
|
|
wire [1:0] exe_prefix_group_1_rep;
|
881 |
|
|
wire exe_prefix_group_1_lock;
|
882 |
|
|
wire [3:0] exe_consumed_final;
|
883 |
|
|
wire exe_is_8bit_final;
|
884 |
|
|
wire [6:0] exe_cmd;
|
885 |
|
|
wire [3:0] exe_cmdex;
|
886 |
|
|
wire exe_dst_is_reg;
|
887 |
|
|
wire exe_dst_is_rm;
|
888 |
|
|
wire exe_dst_is_memory;
|
889 |
|
|
wire exe_dst_is_eax;
|
890 |
|
|
wire exe_dst_is_edx_eax;
|
891 |
|
|
wire exe_dst_is_implicit_reg;
|
892 |
|
|
wire [31:0] exe_linear;
|
893 |
|
|
wire [3:0] exe_debug_read;
|
894 |
|
|
wire [31:0] exe_result;
|
895 |
|
|
wire [31:0] exe_result2;
|
896 |
|
|
wire [31:0] exe_result_push;
|
897 |
|
|
wire [4:0] exe_result_signals;
|
898 |
|
|
wire [3:0] exe_arith_index;
|
899 |
|
|
wire exe_arith_sub_carry;
|
900 |
|
|
wire exe_arith_add_carry;
|
901 |
|
|
wire exe_arith_adc_carry;
|
902 |
|
|
wire exe_arith_sbb_carry;
|
903 |
|
|
wire [31:0] src_final;
|
904 |
|
|
wire [31:0] dst_final;
|
905 |
|
|
wire exe_mult_overflow;
|
906 |
|
|
wire [31:0] exe_stack_offset;
|
907 |
|
|
|
908 |
|
|
execute execute_inst(
|
909 |
|
|
.clk (clk),
|
910 |
|
|
.rst_n (rst_n),
|
911 |
|
|
|
912 |
|
|
.exe_reset (exe_reset), //input
|
913 |
|
|
|
914 |
|
|
//general input
|
915 |
|
|
.eax (eax), //input [31:0]
|
916 |
|
|
.ecx (ecx), //input [31:0]
|
917 |
|
|
.edx (edx), //input [31:0]
|
918 |
|
|
.ebp (ebp), //input [31:0]
|
919 |
|
|
.esp (esp), //input [31:0]
|
920 |
|
|
|
921 |
|
|
.cs_cache (cs_cache), //input [63:0]
|
922 |
|
|
.tr_cache (tr_cache), //input [63:0]
|
923 |
|
|
.ss_cache (ss_cache), //input [63:0]
|
924 |
|
|
|
925 |
|
|
.es (es), //input [15:0]
|
926 |
|
|
.cs (cs), //input [15:0]
|
927 |
|
|
.ss (ss), //input [15:0]
|
928 |
|
|
.ds (ds), //input [15:0]
|
929 |
|
|
.fs (fs), //input [15:0]
|
930 |
|
|
.gs (gs), //input [15:0]
|
931 |
|
|
.ldtr (ldtr), //input [15:0]
|
932 |
|
|
.tr (tr), //input [15:0]
|
933 |
|
|
|
934 |
|
|
.cr2 (cr2), //input [31:0]
|
935 |
|
|
.cr3 (cr3), //input [31:0]
|
936 |
|
|
|
937 |
|
|
.dr0 (dr0), //input [31:0]
|
938 |
|
|
.dr1 (dr1), //input [31:0]
|
939 |
|
|
.dr2 (dr2), //input [31:0]
|
940 |
|
|
.dr3 (dr3), //input [31:0]
|
941 |
|
|
.dr6_bt (dr6_bt), //input
|
942 |
|
|
.dr6_bs (dr6_bs), //input
|
943 |
|
|
.dr6_bd (dr6_bd), //input
|
944 |
|
|
.dr6_b12 (dr6_b12), //input
|
945 |
|
|
.dr6_breakpoints (dr6_breakpoints), //input [3:0]
|
946 |
|
|
.dr7 (dr7), //input [31:0]
|
947 |
|
|
|
948 |
|
|
.cpl (cpl), //input [1:0]
|
949 |
|
|
|
950 |
|
|
.real_mode (real_mode), //input
|
951 |
|
|
.v8086_mode (v8086_mode), //input
|
952 |
|
|
.protected_mode (protected_mode), //input
|
953 |
|
|
|
954 |
|
|
.idflag (idflag), //input
|
955 |
|
|
.acflag (acflag), //input
|
956 |
|
|
.vmflag (vmflag), //input
|
957 |
|
|
.rflag (rflag), //input
|
958 |
|
|
.ntflag (ntflag), //input
|
959 |
|
|
.iopl (iopl), //input [1:0]
|
960 |
|
|
.oflag (oflag), //input
|
961 |
|
|
.dflag (dflag), //input
|
962 |
|
|
.iflag (iflag), //input
|
963 |
|
|
.tflag (tflag), //input
|
964 |
|
|
.sflag (sflag), //input
|
965 |
|
|
.zflag (zflag), //input
|
966 |
|
|
.aflag (aflag), //input
|
967 |
|
|
.pflag (pflag), //input
|
968 |
|
|
.cflag (cflag), //input
|
969 |
|
|
|
970 |
|
|
.cr0_pg (cr0_pg), //input
|
971 |
|
|
.cr0_cd (cr0_cd), //input
|
972 |
|
|
.cr0_nw (cr0_nw), //input
|
973 |
|
|
.cr0_am (cr0_am), //input
|
974 |
|
|
.cr0_wp (cr0_wp), //input
|
975 |
|
|
.cr0_ne (cr0_ne), //input
|
976 |
|
|
.cr0_ts (cr0_ts), //input
|
977 |
|
|
.cr0_em (cr0_em), //input
|
978 |
|
|
.cr0_mp (cr0_mp), //input
|
979 |
|
|
.cr0_pe (cr0_pe), //input
|
980 |
|
|
|
981 |
|
|
.idtr_limit (idtr_limit), //input [15:0]
|
982 |
|
|
.idtr_base (idtr_base), //input [31:0]
|
983 |
|
|
.gdtr_limit (gdtr_limit), //input [15:0]
|
984 |
|
|
.gdtr_base (gdtr_base), //input [31:0]
|
985 |
|
|
|
986 |
|
|
//exception input
|
987 |
|
|
.exc_push_error (exc_push_error), //input
|
988 |
|
|
.exc_error_code (exc_error_code), //input [15:0]
|
989 |
|
|
.exc_soft_int_ib (exc_soft_int_ib), //input
|
990 |
|
|
.exc_soft_int (exc_soft_int), //input
|
991 |
|
|
.exc_vector (exc_vector), //input [7:0]
|
992 |
|
|
|
993 |
|
|
//tlbcheck
|
994 |
|
|
.tlbcheck_do (tlbcheck_do), //output
|
995 |
|
|
.tlbcheck_done (tlbcheck_done), //input
|
996 |
|
|
.tlbcheck_page_fault (tlbcheck_page_fault), //input
|
997 |
|
|
.tlbcheck_address (tlbcheck_address), //output [31:0]
|
998 |
|
|
.tlbcheck_rw (tlbcheck_rw), //output
|
999 |
|
|
|
1000 |
|
|
//tlbflushsingle
|
1001 |
|
|
.tlbflushsingle_do (tlbflushsingle_do), //output
|
1002 |
|
|
.tlbflushsingle_done (tlbflushsingle_done), //input
|
1003 |
|
|
.tlbflushsingle_address (tlbflushsingle_address), //output [31:0]
|
1004 |
|
|
|
1005 |
|
|
//invd
|
1006 |
|
|
.invdcode_do (invdcode_do), //output
|
1007 |
|
|
.invdcode_done (invdcode_done), //input
|
1008 |
|
|
|
1009 |
|
|
.invddata_do (invddata_do), //output
|
1010 |
|
|
.invddata_done (invddata_done), //input
|
1011 |
|
|
|
1012 |
|
|
.wbinvddata_do (wbinvddata_do), //output
|
1013 |
|
|
.wbinvddata_done (wbinvddata_done), //input
|
1014 |
|
|
|
1015 |
|
|
//pipeline input
|
1016 |
|
|
.wr_esp_prev (wr_esp_prev), //input [31:0]
|
1017 |
|
|
.wr_stack_offset (wr_stack_offset), //input [31:0]
|
1018 |
|
|
|
1019 |
|
|
.wr_mutex (wr_mutex), //input [10:0]
|
1020 |
|
|
|
1021 |
|
|
//pipeline output
|
1022 |
|
|
.exe_is_front (exe_is_front), //output
|
1023 |
|
|
|
1024 |
|
|
//global input
|
1025 |
|
|
.glob_descriptor (glob_descriptor), //input [63:0]
|
1026 |
|
|
.glob_descriptor_2 (glob_descriptor_2), //input [63:0]
|
1027 |
|
|
|
1028 |
|
|
.glob_param_1 (glob_param_1), //input [31:0]
|
1029 |
|
|
.glob_param_2 (glob_param_2), //input [31:0]
|
1030 |
|
|
.glob_param_3 (glob_param_3), //input [31:0]
|
1031 |
|
|
.glob_param_4 (glob_param_4), //input [31:0]
|
1032 |
|
|
.glob_param_5 (glob_param_5), //input [31:0]
|
1033 |
|
|
|
1034 |
|
|
.wr_task_rpl (wr_task_rpl), //input [1:0]
|
1035 |
|
|
|
1036 |
|
|
.glob_desc_base (glob_desc_base), //input [31:0]
|
1037 |
|
|
.glob_desc_limit (glob_desc_limit), //input [31:0]
|
1038 |
|
|
.glob_desc_2_limit (glob_desc_2_limit), //input [31:0]
|
1039 |
|
|
|
1040 |
|
|
//global set
|
1041 |
|
|
.exe_glob_descriptor_set (exe_glob_descriptor_set), //output
|
1042 |
|
|
.exe_glob_descriptor_value (exe_glob_descriptor_value), //output [63:0]
|
1043 |
|
|
|
1044 |
|
|
.exe_glob_descriptor_2_set (exe_glob_descriptor_2_set), //output
|
1045 |
|
|
.exe_glob_descriptor_2_value (exe_glob_descriptor_2_value), //output [63:0]
|
1046 |
|
|
|
1047 |
|
|
.exe_glob_param_1_set (exe_glob_param_1_set), //output
|
1048 |
|
|
.exe_glob_param_1_value (exe_glob_param_1_value), //output [31:0]
|
1049 |
|
|
.exe_glob_param_2_set (exe_glob_param_2_set), //output
|
1050 |
|
|
.exe_glob_param_2_value (exe_glob_param_2_value), //output [31:0]
|
1051 |
|
|
.exe_glob_param_3_set (exe_glob_param_3_set), //output
|
1052 |
|
|
.exe_glob_param_3_value (exe_glob_param_3_value), //output [31:0]
|
1053 |
|
|
|
1054 |
|
|
//wr set
|
1055 |
|
|
.dr6_bd_set (dr6_bd_set), //output
|
1056 |
|
|
|
1057 |
|
|
//to microcode
|
1058 |
|
|
.task_eip (task_eip), //output [31:0]
|
1059 |
|
|
//to wr
|
1060 |
|
|
.exe_buffer (exe_buffer), //output [31:0]
|
1061 |
|
|
.exe_buffer_shifted (exe_buffer_shifted), //output [463:0]
|
1062 |
|
|
|
1063 |
|
|
//exceptions
|
1064 |
|
|
.exe_bound_fault (exe_bound_fault), //output
|
1065 |
|
|
.exe_trigger_gp_fault (exe_trigger_gp_fault), //output
|
1066 |
|
|
.exe_trigger_ts_fault (exe_trigger_ts_fault), //output
|
1067 |
|
|
.exe_trigger_ss_fault (exe_trigger_ss_fault), //output
|
1068 |
|
|
.exe_trigger_np_fault (exe_trigger_np_fault), //output
|
1069 |
|
|
.exe_trigger_pf_fault (exe_trigger_pf_fault), //output
|
1070 |
|
|
.exe_trigger_db_fault (exe_trigger_db_fault), //output
|
1071 |
|
|
.exe_trigger_nm_fault (exe_trigger_nm_fault), //output
|
1072 |
|
|
.exe_load_seg_gp_fault (exe_load_seg_gp_fault), //output
|
1073 |
|
|
.exe_load_seg_ss_fault (exe_load_seg_ss_fault), //output
|
1074 |
|
|
.exe_load_seg_np_fault (exe_load_seg_np_fault), //output
|
1075 |
|
|
.exe_div_exception (exe_div_exception), //output
|
1076 |
|
|
|
1077 |
|
|
.exe_error_code (exe_error_code), //output [15:0]
|
1078 |
|
|
|
1079 |
|
|
.exe_eip (exe_eip), //output [31:0]
|
1080 |
|
|
.exe_consumed (exe_consumed), //output [3:0]
|
1081 |
|
|
|
1082 |
|
|
//rd pipeline
|
1083 |
|
|
.exe_busy (exe_busy), //output
|
1084 |
|
|
.rd_ready (rd_ready), //input
|
1085 |
|
|
.rd_decoder (rd_decoder), //input [87:0]
|
1086 |
|
|
.rd_eip (rd_eip), //input [31:0]
|
1087 |
|
|
.rd_operand_32bit (rd_operand_32bit), //input
|
1088 |
|
|
.rd_address_32bit (rd_address_32bit), //input
|
1089 |
|
|
.rd_prefix_group_1_rep (rd_prefix_group_1_rep), //input [1:0]
|
1090 |
|
|
.rd_prefix_group_1_lock (rd_prefix_group_1_lock), //input
|
1091 |
|
|
.rd_prefix_2byte (rd_prefix_2byte), //input
|
1092 |
|
|
.rd_consumed (rd_consumed), //input [3:0]
|
1093 |
|
|
.rd_is_8bit (rd_is_8bit), //input
|
1094 |
|
|
.rd_cmd (rd_cmd), //input [6:0]
|
1095 |
|
|
.rd_cmdex (rd_cmdex), //input [3:0]
|
1096 |
|
|
.rd_modregrm_imm (rd_modregrm_imm), //input [31:0]
|
1097 |
|
|
.rd_mutex_next (rd_mutex_next), //input [10:0]
|
1098 |
|
|
.rd_dst_is_reg (rd_dst_is_reg), //input
|
1099 |
|
|
.rd_dst_is_rm (rd_dst_is_rm), //input
|
1100 |
|
|
.rd_dst_is_memory (rd_dst_is_memory), //input
|
1101 |
|
|
.rd_dst_is_eax (rd_dst_is_eax), //input
|
1102 |
|
|
.rd_dst_is_edx_eax (rd_dst_is_edx_eax), //input
|
1103 |
|
|
.rd_dst_is_implicit_reg (rd_dst_is_implicit_reg), //input
|
1104 |
|
|
.rd_extra_wire (rd_extra_wire), //input [31:0]
|
1105 |
|
|
.rd_linear (rd_linear), //input [31:0]
|
1106 |
|
|
.rd_debug_read (rd_debug_read), //input [3:0]
|
1107 |
|
|
.src_wire (src_wire), //input [31:0]
|
1108 |
|
|
.dst_wire (dst_wire), //input [31:0]
|
1109 |
|
|
.rd_address_effective (rd_address_effective), //input [31:0]
|
1110 |
|
|
|
1111 |
|
|
//exe pipeline
|
1112 |
|
|
.wr_busy (wr_busy), //input
|
1113 |
|
|
.exe_ready (exe_ready), //output
|
1114 |
|
|
|
1115 |
|
|
.exe_decoder (exe_decoder), //output [39:0]
|
1116 |
|
|
.exe_eip_final (exe_eip_final), //output [31:0]
|
1117 |
|
|
.exe_operand_32bit (exe_operand_32bit), //output
|
1118 |
|
|
.exe_address_32bit (exe_address_32bit), //output
|
1119 |
|
|
.exe_prefix_group_1_rep (exe_prefix_group_1_rep), //output [1:0]
|
1120 |
|
|
.exe_prefix_group_1_lock (exe_prefix_group_1_lock), //output
|
1121 |
|
|
.exe_consumed_final (exe_consumed_final), //output [3:0]
|
1122 |
|
|
.exe_is_8bit_final (exe_is_8bit_final), //output
|
1123 |
|
|
.exe_cmd (exe_cmd), //output [6:0]
|
1124 |
|
|
.exe_cmdex (exe_cmdex), //output [3:0]
|
1125 |
|
|
.exe_mutex (exe_mutex), //output [10:0]
|
1126 |
|
|
.exe_dst_is_reg (exe_dst_is_reg), //output
|
1127 |
|
|
.exe_dst_is_rm (exe_dst_is_rm), //output
|
1128 |
|
|
.exe_dst_is_memory (exe_dst_is_memory), //output
|
1129 |
|
|
.exe_dst_is_eax (exe_dst_is_eax), //output
|
1130 |
|
|
.exe_dst_is_edx_eax (exe_dst_is_edx_eax), //output
|
1131 |
|
|
.exe_dst_is_implicit_reg (exe_dst_is_implicit_reg), //output
|
1132 |
|
|
.exe_linear (exe_linear), //output [31:0]
|
1133 |
|
|
.exe_debug_read (exe_debug_read), //output [3:0]
|
1134 |
|
|
.exe_result (exe_result), //output [31:0]
|
1135 |
|
|
.exe_result2 (exe_result2), //output [31:0]
|
1136 |
|
|
.exe_result_push (exe_result_push), //output [31:0]
|
1137 |
|
|
.exe_result_signals (exe_result_signals), //output [4:0]
|
1138 |
|
|
.exe_arith_index (exe_arith_index), //output [3:0]
|
1139 |
|
|
.exe_arith_sub_carry (exe_arith_sub_carry), //output
|
1140 |
|
|
.exe_arith_add_carry (exe_arith_add_carry), //output
|
1141 |
|
|
.exe_arith_adc_carry (exe_arith_adc_carry), //output
|
1142 |
|
|
.exe_arith_sbb_carry (exe_arith_sbb_carry), //output
|
1143 |
|
|
.src_final (src_final), //output [31:0]
|
1144 |
|
|
.dst_final (dst_final), //output [31:0]
|
1145 |
|
|
.exe_mult_overflow (exe_mult_overflow), //output
|
1146 |
|
|
.exe_stack_offset (exe_stack_offset) //output [31:0]
|
1147 |
|
|
);
|
1148 |
|
|
|
1149 |
|
|
//------------------------------------------------------------------------------
|
1150 |
|
|
|
1151 |
|
|
write write_inst(
|
1152 |
|
|
.clk (clk),
|
1153 |
|
|
.rst_n (rst_n),
|
1154 |
|
|
|
1155 |
|
|
.exe_reset (exe_reset), //input
|
1156 |
|
|
.wr_reset (wr_reset), //input
|
1157 |
|
|
|
1158 |
|
|
//global input
|
1159 |
|
|
.glob_descriptor (glob_descriptor), //input [63:0]
|
1160 |
|
|
.glob_descriptor_2 (glob_descriptor_2), //input [63:0]
|
1161 |
|
|
.glob_desc_base (glob_desc_base), //input [31:0]
|
1162 |
|
|
.glob_desc_limit (glob_desc_limit), //input [31:0]
|
1163 |
|
|
|
1164 |
|
|
.glob_param_1 (glob_param_1), //input [31:0]
|
1165 |
|
|
.glob_param_2 (glob_param_2), //input [31:0]
|
1166 |
|
|
.glob_param_3 (glob_param_3), //input [31:0]
|
1167 |
|
|
.glob_param_4 (glob_param_4), //input [31:0]
|
1168 |
|
|
.glob_param_5 (glob_param_5), //input [31:0]
|
1169 |
|
|
|
1170 |
|
|
//general input
|
1171 |
|
|
.eip (eip), //input [31:0]
|
1172 |
|
|
|
1173 |
|
|
//registers output
|
1174 |
|
|
.gdtr_base (gdtr_base), //output [31:0]
|
1175 |
|
|
.gdtr_limit (gdtr_limit), //output [15:0]
|
1176 |
|
|
|
1177 |
|
|
.idtr_base (idtr_base), //output [31:0]
|
1178 |
|
|
.idtr_limit (idtr_limit), //output [15:0]
|
1179 |
|
|
|
1180 |
|
|
//pipeline input
|
1181 |
|
|
.exe_buffer (exe_buffer), //input [31:0]
|
1182 |
|
|
.exe_buffer_shifted (exe_buffer_shifted), //input [463:0]
|
1183 |
|
|
|
1184 |
|
|
.dr6_bd_set (dr6_bd_set), //input
|
1185 |
|
|
|
1186 |
|
|
//interrupt input
|
1187 |
|
|
.interrupt_do (interrupt_do), //input
|
1188 |
|
|
|
1189 |
|
|
//exception input
|
1190 |
|
|
.exc_init (exc_init), //input
|
1191 |
|
|
.exc_set_rflag (exc_set_rflag), //input
|
1192 |
|
|
.exc_debug_start (exc_debug_start), //input
|
1193 |
|
|
.exc_pf_read (exc_pf_read), //input
|
1194 |
|
|
.exc_pf_write (exc_pf_write), //input
|
1195 |
|
|
.exc_pf_code (exc_pf_code), //input
|
1196 |
|
|
.exc_pf_check (exc_pf_check), //input
|
1197 |
|
|
.exc_restore_esp (exc_restore_esp), //input
|
1198 |
|
|
.exc_push_error (exc_push_error), //input
|
1199 |
|
|
.exc_eip (exc_eip), //input [31:0]
|
1200 |
|
|
|
1201 |
|
|
//output
|
1202 |
|
|
.real_mode (real_mode), //output
|
1203 |
|
|
.v8086_mode (v8086_mode), //output
|
1204 |
|
|
.protected_mode (protected_mode), //output
|
1205 |
|
|
|
1206 |
|
|
.cpl (cpl), //output [1:0]
|
1207 |
|
|
|
1208 |
|
|
.io_allow_check_needed (io_allow_check_needed), //output
|
1209 |
|
|
|
1210 |
|
|
.debug_len0 (debug_len0), //output [2:0]
|
1211 |
|
|
.debug_len1 (debug_len1), //output [2:0]
|
1212 |
|
|
.debug_len2 (debug_len2), //output [2:0]
|
1213 |
|
|
.debug_len3 (debug_len3), //output [2:0]
|
1214 |
|
|
|
1215 |
|
|
//wr output
|
1216 |
|
|
.wr_is_front (wr_is_front), //output
|
1217 |
|
|
|
1218 |
|
|
.wr_interrupt_possible (wr_interrupt_possible), //output
|
1219 |
|
|
.wr_string_in_progress_final (wr_string_in_progress_final), //output
|
1220 |
|
|
.wr_is_esp_speculative (wr_is_esp_speculative), //output
|
1221 |
|
|
|
1222 |
|
|
.wr_mutex (wr_mutex), //output [10:0]
|
1223 |
|
|
|
1224 |
|
|
.wr_stack_offset (wr_stack_offset), //output [31:0]
|
1225 |
|
|
.wr_esp_prev (wr_esp_prev), //output [31:0]
|
1226 |
|
|
|
1227 |
|
|
.wr_task_rpl (wr_task_rpl), //output [1:0]
|
1228 |
|
|
|
1229 |
|
|
.wr_consumed (wr_consumed), //output [3:0]
|
1230 |
|
|
|
1231 |
|
|
//software interrupt
|
1232 |
|
|
.wr_int (wr_int), //output
|
1233 |
|
|
.wr_int_soft_int (wr_int_soft_int), //output
|
1234 |
|
|
.wr_int_soft_int_ib (wr_int_soft_int_ib), //output
|
1235 |
|
|
.wr_int_vector (wr_int_vector), //output [7:0]
|
1236 |
|
|
|
1237 |
|
|
.wr_exception_external_set (wr_exception_external_set), //output
|
1238 |
|
|
.wr_exception_finished (wr_exception_finished), //output
|
1239 |
|
|
|
1240 |
|
|
.wr_error_code (wr_error_code), //output [15:0]
|
1241 |
|
|
|
1242 |
|
|
//wr exception
|
1243 |
|
|
.wr_debug_init (wr_debug_init), //output
|
1244 |
|
|
|
1245 |
|
|
.wr_new_push_ss_fault (wr_new_push_ss_fault), //output
|
1246 |
|
|
.wr_string_es_fault (wr_string_es_fault), //output
|
1247 |
|
|
.wr_push_ss_fault (wr_push_ss_fault), //output
|
1248 |
|
|
|
1249 |
|
|
//eip control
|
1250 |
|
|
.wr_eip (wr_eip), //output [31:0]
|
1251 |
|
|
|
1252 |
|
|
//reset request
|
1253 |
|
|
.wr_req_reset_pr (wr_req_reset_pr), //output
|
1254 |
|
|
.wr_req_reset_dec (wr_req_reset_dec), //output
|
1255 |
|
|
.wr_req_reset_micro (wr_req_reset_micro), //output
|
1256 |
|
|
.wr_req_reset_rd (wr_req_reset_rd), //output
|
1257 |
|
|
.wr_req_reset_exe (wr_req_reset_exe), //output
|
1258 |
|
|
|
1259 |
|
|
//memory page fault
|
1260 |
|
|
.tlb_code_pf_cr2 (tlb_code_pf_cr2), //input [31:0]
|
1261 |
|
|
.tlb_write_pf_cr2 (tlb_write_pf_cr2), //input [31:0]
|
1262 |
|
|
.tlb_read_pf_cr2 (tlb_read_pf_cr2), //input [31:0]
|
1263 |
|
|
.tlb_check_pf_cr2 (tlb_check_pf_cr2), //input [31:0]
|
1264 |
|
|
|
1265 |
|
|
//memory write
|
1266 |
|
|
.write_do (write_do), //output
|
1267 |
|
|
.write_done (write_done), //input
|
1268 |
|
|
.write_page_fault (write_page_fault), //input
|
1269 |
|
|
.write_ac_fault (write_ac_fault), //input
|
1270 |
|
|
.write_cpl (write_cpl), //output [1:0]
|
1271 |
|
|
.write_address (write_address), //output [31:0]
|
1272 |
|
|
.write_length (write_length), //output [2:0]
|
1273 |
|
|
.write_lock (write_lock), //output
|
1274 |
|
|
.write_rmw (write_rmw), //output
|
1275 |
|
|
.write_data (write_data), //output [31:0]
|
1276 |
|
|
|
1277 |
|
|
//flush tlb
|
1278 |
|
|
.tlbflushall_do (tlbflushall_do), //output
|
1279 |
|
|
|
1280 |
|
|
//io write
|
1281 |
|
|
.io_write_do (io_write_do), //output
|
1282 |
|
|
.io_write_address (io_write_address), //output [15:0]
|
1283 |
|
|
.io_write_length (io_write_length), //output [2:0]
|
1284 |
|
|
.io_write_data (io_write_data), //output [31:0]
|
1285 |
|
|
.io_write_done (io_write_done), //input
|
1286 |
|
|
|
1287 |
|
|
//global write
|
1288 |
|
|
.wr_glob_param_1_set (wr_glob_param_1_set), //output
|
1289 |
|
|
.wr_glob_param_1_value (wr_glob_param_1_value), //output [31:0]
|
1290 |
|
|
.wr_glob_param_3_set (wr_glob_param_3_set), //output
|
1291 |
|
|
.wr_glob_param_3_value (wr_glob_param_3_value), //output [31:0]
|
1292 |
|
|
.wr_glob_param_4_set (wr_glob_param_4_set), //output
|
1293 |
|
|
.wr_glob_param_4_value (wr_glob_param_4_value), //output [31:0]
|
1294 |
|
|
|
1295 |
|
|
//registers output
|
1296 |
|
|
.eax (eax), //output [31:0]
|
1297 |
|
|
.ebx (ebx), //output [31:0]
|
1298 |
|
|
.ecx (ecx), //output [31:0]
|
1299 |
|
|
.edx (edx), //output [31:0]
|
1300 |
|
|
.esi (esi), //output [31:0]
|
1301 |
|
|
.edi (edi), //output [31:0]
|
1302 |
|
|
.ebp (ebp), //output [31:0]
|
1303 |
|
|
.esp (esp), //output [31:0]
|
1304 |
|
|
|
1305 |
|
|
.cr0_pe (cr0_pe), //output
|
1306 |
|
|
.cr0_mp (cr0_mp), //output
|
1307 |
|
|
.cr0_em (cr0_em), //output
|
1308 |
|
|
.cr0_ts (cr0_ts), //output
|
1309 |
|
|
.cr0_ne (cr0_ne), //output
|
1310 |
|
|
.cr0_wp (cr0_wp), //output
|
1311 |
|
|
.cr0_am (cr0_am), //output
|
1312 |
|
|
.cr0_nw (cr0_nw), //output
|
1313 |
|
|
.cr0_cd (cr0_cd), //output
|
1314 |
|
|
.cr0_pg (cr0_pg), //output
|
1315 |
|
|
|
1316 |
|
|
.cr2 (cr2), //output [31:0]
|
1317 |
|
|
.cr3 (cr3), //output [31:0]
|
1318 |
|
|
|
1319 |
|
|
.cflag (cflag), //output
|
1320 |
|
|
.pflag (pflag), //output
|
1321 |
|
|
.aflag (aflag), //output
|
1322 |
|
|
.zflag (zflag), //output
|
1323 |
|
|
.sflag (sflag), //output
|
1324 |
|
|
.oflag (oflag), //output
|
1325 |
|
|
.tflag (tflag), //output
|
1326 |
|
|
.iflag (iflag), //output
|
1327 |
|
|
.dflag (dflag), //output
|
1328 |
|
|
.iopl (iopl), //output [1:0]
|
1329 |
|
|
.ntflag (ntflag), //output
|
1330 |
|
|
.rflag (rflag), //output
|
1331 |
|
|
.vmflag (vmflag), //output
|
1332 |
|
|
.acflag (acflag), //output
|
1333 |
|
|
.idflag (idflag), //output
|
1334 |
|
|
|
1335 |
|
|
.dr0 (dr0), //output [31:0]
|
1336 |
|
|
.dr1 (dr1), //output [31:0]
|
1337 |
|
|
.dr2 (dr2), //output [31:0]
|
1338 |
|
|
.dr3 (dr3), //output [31:0]
|
1339 |
|
|
.dr6_breakpoints (dr6_breakpoints), //output [3:0]
|
1340 |
|
|
.dr6_b12 (dr6_b12), //output
|
1341 |
|
|
.dr6_bd (dr6_bd), //output
|
1342 |
|
|
.dr6_bs (dr6_bs), //output
|
1343 |
|
|
.dr6_bt (dr6_bt), //output
|
1344 |
|
|
.dr7 (dr7), //output [31:0]
|
1345 |
|
|
|
1346 |
|
|
.es (es), //output [15:0]
|
1347 |
|
|
.ds (ds), //output [15:0]
|
1348 |
|
|
.ss (ss), //output [15:0]
|
1349 |
|
|
.fs (fs), //output [15:0]
|
1350 |
|
|
.gs (gs), //output [15:0]
|
1351 |
|
|
.cs (cs), //output [15:0]
|
1352 |
|
|
.ldtr (ldtr), //output [15:0]
|
1353 |
|
|
.tr (tr), //output [15:0]
|
1354 |
|
|
|
1355 |
|
|
.es_cache (es_cache), //output [63:0]
|
1356 |
|
|
.ds_cache (ds_cache), //output [63:0]
|
1357 |
|
|
.ss_cache (ss_cache), //output [63:0]
|
1358 |
|
|
.fs_cache (fs_cache), //output [63:0]
|
1359 |
|
|
.gs_cache (gs_cache), //output [63:0]
|
1360 |
|
|
.cs_cache (cs_cache), //output [63:0]
|
1361 |
|
|
.ldtr_cache (ldtr_cache), //output [63:0]
|
1362 |
|
|
.tr_cache (tr_cache), //output [63:0]
|
1363 |
|
|
|
1364 |
|
|
.es_cache_valid (es_cache_valid), //output
|
1365 |
|
|
.ds_cache_valid (ds_cache_valid), //output
|
1366 |
|
|
.ss_cache_valid (ss_cache_valid), //output
|
1367 |
|
|
.fs_cache_valid (fs_cache_valid), //output
|
1368 |
|
|
.gs_cache_valid (gs_cache_valid), //output
|
1369 |
|
|
.cs_cache_valid (cs_cache_valid), //output
|
1370 |
|
|
.ldtr_cache_valid (ldtr_cache_valid), //output
|
1371 |
|
|
.tr_cache_valid (tr_cache_valid), //output
|
1372 |
|
|
|
1373 |
|
|
//pipeline wr
|
1374 |
|
|
.wr_busy (wr_busy), //output
|
1375 |
|
|
.exe_ready (exe_ready), //input
|
1376 |
|
|
|
1377 |
|
|
.exe_decoder (exe_decoder), //input [39:0]
|
1378 |
|
|
.exe_eip_final (exe_eip_final), //input [31:0]
|
1379 |
|
|
.exe_operand_32bit (exe_operand_32bit), //input
|
1380 |
|
|
.exe_address_32bit (exe_address_32bit), //input
|
1381 |
|
|
.exe_prefix_group_1_rep (exe_prefix_group_1_rep), //input [1:0]
|
1382 |
|
|
.exe_prefix_group_1_lock (exe_prefix_group_1_lock), //input
|
1383 |
|
|
.exe_consumed_final (exe_consumed_final), //input [3:0]
|
1384 |
|
|
.exe_is_8bit_final (exe_is_8bit_final), //input
|
1385 |
|
|
.exe_cmd (exe_cmd), //input [6:0]
|
1386 |
|
|
.exe_cmdex (exe_cmdex), //input [3:0]
|
1387 |
|
|
.exe_mutex (exe_mutex), //input [10:0]
|
1388 |
|
|
.exe_dst_is_reg (exe_dst_is_reg), //input
|
1389 |
|
|
.exe_dst_is_rm (exe_dst_is_rm), //input
|
1390 |
|
|
.exe_dst_is_memory (exe_dst_is_memory), //input
|
1391 |
|
|
.exe_dst_is_eax (exe_dst_is_eax), //input
|
1392 |
|
|
.exe_dst_is_edx_eax (exe_dst_is_edx_eax), //input
|
1393 |
|
|
.exe_dst_is_implicit_reg (exe_dst_is_implicit_reg), //input
|
1394 |
|
|
.exe_linear (exe_linear), //input [31:0]
|
1395 |
|
|
.exe_debug_read (exe_debug_read), //input [3:0]
|
1396 |
|
|
.exe_result (exe_result), //input [31:0]
|
1397 |
|
|
.exe_result2 (exe_result2), //input [31:0]
|
1398 |
|
|
.exe_result_push (exe_result_push), //input [31:0]
|
1399 |
|
|
.exe_result_signals (exe_result_signals), //input [4:0]
|
1400 |
|
|
.exe_arith_index (exe_arith_index), //input [3:0]
|
1401 |
|
|
.exe_arith_sub_carry (exe_arith_sub_carry), //input
|
1402 |
|
|
.exe_arith_add_carry (exe_arith_add_carry), //input
|
1403 |
|
|
.exe_arith_adc_carry (exe_arith_adc_carry), //input
|
1404 |
|
|
.exe_arith_sbb_carry (exe_arith_sbb_carry), //input
|
1405 |
|
|
.src_final (src_final), //input [31:0]
|
1406 |
|
|
.dst_final (dst_final), //input [31:0]
|
1407 |
|
|
.exe_mult_overflow (exe_mult_overflow), //input
|
1408 |
|
|
.exe_stack_offset (exe_stack_offset) //input [31:0]
|
1409 |
|
|
);
|
1410 |
|
|
|
1411 |
|
|
|
1412 |
|
|
//------------------------------------------------------------------------------
|
1413 |
|
|
|
1414 |
|
|
//------------------------------------------------------------------------------
|
1415 |
|
|
|
1416 |
|
|
//------------------------------------------------------------------------------
|
1417 |
|
|
|
1418 |
|
|
|
1419 |
|
|
|
1420 |
|
|
endmodule
|