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/*
 * Copyright (c) 2014, Aleksander Osman
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *
 * * Redistributions of source code must retain the above copyright notice, this
 *   list of conditions and the following disclaimer.
 *
 * * Redistributions in binary form must reproduce the above copyright notice,
 *   this list of conditions and the following disclaimer in the documentation
 *   and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
`include "defines.v"
 
//PARSED_COMMENTS: this file contains parsed script comments
 
module write_commands(
    input               clk,
    input               rst_n,
 
    //general input
    input               real_mode,
    input               v8086_mode,
    input               protected_mode,
 
    input       [1:0]   cpl,
 
    input       [31:0]  tr_base,
 
    input       [31:0]  eip,
 
    input               io_allow_check_needed,
 
    input               exc_push_error,
    input       [31:0]  exc_eip,
 
    //global input
    input       [63:0]  glob_descriptor,
    input       [31:0]  glob_desc_base,
 
    input       [31:0]  glob_param_1,
    input       [31:0]  glob_param_2,
    input       [31:0]  glob_param_3,
    input       [31:0]  glob_param_4,
    input       [31:0]  glob_param_5,
 
    //write
    input               wr_ready,
    input       [15:0]  wr_decoder,
    input       [6:0]   wr_cmd,
    input       [3:0]   wr_cmdex,
    input               wr_is_8bit,
    input               wr_address_16bit,
    input               wr_operand_16bit,
    input               wr_operand_32bit,
    input               wr_mult_overflow,
    input       [3:0]   wr_arith_index,
    input       [1:0]   wr_modregrm_mod,
    input       [2:0]   wr_modregrm_reg,
    input       [2:0]   wr_modregrm_rm,
    input               wr_dst_is_memory,
    input               wr_dst_is_reg,
    input               wr_dst_is_rm,
    input               wr_dst_is_implicit_reg,
    input               wr_dst_is_edx_eax,
    input               wr_dst_is_eax,
 
    input               wr_arith_add_carry,
    input               wr_arith_adc_carry,
    input               wr_arith_sbb_carry,
    input               wr_arith_sub_carry,
 
    input       [31:0]  result,
    input       [31:0]  result2,
    input       [31:0]  wr_src,
    input       [31:0]  wr_dst,
    input       [4:0]   result_signals,
    input       [31:0]  result_push,
 
    input       [31:0]  exe_buffer,
    input       [463:0] exe_buffer_shifted,
 
    //global output
    output              wr_glob_param_1_set,
    output      [31:0]  wr_glob_param_1_value,
 
    output              wr_glob_param_3_set,
    output      [31:0]  wr_glob_param_3_value,
 
    output              wr_glob_param_4_set,
    output      [31:0]  wr_glob_param_4_value,
 
    //debug output
    output              wr_debug_trap_clear,
    output              wr_debug_task_trigger,
 
    //exception
    output              wr_int,
    output              wr_int_soft_int,
    output              wr_int_soft_int_ib,
    output      [7:0]   wr_int_vector,
 
    output              wr_exception_external_set,
    output              wr_exception_finished,
 
    output              wr_inhibit_interrupts,
    output              wr_inhibit_interrupts_and_debug,
 
    //memory
    input               write_for_wr_ready,
 
    output              write_rmw_virtual,
    output              write_virtual,
    output              write_rmw_system_dword,
    output              write_system_word,
    output              write_system_dword,
    output              write_system_busy_tss,
    output              write_system_touch,
 
    output              write_length_word,
    output              write_length_dword,
 
    output      [31:0]  wr_system_dword,
    output      [31:0]  wr_system_linear,
 
    //write regrm
    output              write_regrm,
    output              write_eax,
    output              wr_regrm_word,
    output              wr_regrm_dword,
 
    //write output
    output              wr_not_finished,
    output              wr_hlt_in_progress,
    output              wr_string_in_progress,
    output              wr_waiting,
 
    output              wr_req_reset_pr,
    output              wr_req_reset_dec,
    output              wr_req_reset_micro,
    output              wr_req_reset_rd,
    output              wr_req_reset_exe,
 
    output              wr_zflag_result,
 
    output reg  [1:0]   wr_task_rpl,
 
    output              wr_one_cycle_wait,
 
    //stack
    output              write_stack_virtual,
    output              write_new_stack_virtual,
 
    output              wr_push_length_word,
    output              wr_push_length_dword,
 
    input       [31:0]  wr_stack_esp,
    input       [31:0]  wr_new_stack_esp,
 
    output              wr_push_ss_fault_check,
    input               wr_push_ss_fault,
 
    output              wr_new_push_ss_fault_check,
    input               wr_new_push_ss_fault,
 
    output      [15:0]  wr_error_code,
 
    output              wr_make_esp_speculative,
    output              wr_make_esp_commit,
 
    //string
    input               wr_string_ignore,
    input       [1:0]   wr_prefix_group_1_rep,
    input               wr_string_zf_finish,
    input               wr_string_es_fault,
    input               wr_string_finish,
 
    input       [31:0]  wr_esi_final,
    input       [31:0]  wr_edi_final,
    input       [31:0]  wr_ecx_final,
 
    output              wr_string_gp_fault_check,
    output              write_string_es_virtual,
 
    //io write
    output              write_io,
    input               write_io_for_wr_ready,
 
    //segment
    output      [15:0]  wr_seg_sel,
    output              wr_seg_cache_valid,
    output      [1:0]   wr_seg_rpl,
    output      [63:0]  wr_seg_cache_mask,
 
    output              write_seg_cache,
    output              write_seg_sel,
    output              write_seg_cache_valid,
    output              write_seg_rpl,
 
    output              wr_validate_seg_regs,
 
    //flush tlb
    output              tlbflushall_do,
 
    //---------------------
 
    output      [31:0]  eax_to_reg,
    output      [31:0]  ebx_to_reg,
    output      [31:0]  ecx_to_reg,
    output      [31:0]  edx_to_reg,
    output      [31:0]  esi_to_reg,
    output      [31:0]  edi_to_reg,
    output      [31:0]  ebp_to_reg,
    output      [31:0]  esp_to_reg,
 
    output              cr0_pe_to_reg,
    output              cr0_mp_to_reg,
    output              cr0_em_to_reg,
    output              cr0_ts_to_reg,
    output              cr0_ne_to_reg,
    output              cr0_wp_to_reg,
    output              cr0_am_to_reg,
    output              cr0_nw_to_reg,
    output              cr0_cd_to_reg,
    output              cr0_pg_to_reg,
 
    output      [31:0]  cr2_to_reg,
    output      [31:0]  cr3_to_reg,
 
    output              cflag_to_reg,
    output              pflag_to_reg,
    output              aflag_to_reg,
    output              zflag_to_reg,
    output              sflag_to_reg,
    output              oflag_to_reg,
    output              tflag_to_reg,
    output              iflag_to_reg,
    output              dflag_to_reg,
    output      [1:0]   iopl_to_reg,
    output              ntflag_to_reg,
    output              rflag_to_reg,
    output              vmflag_to_reg,
    output              acflag_to_reg,
    output              idflag_to_reg,
 
    output      [31:0]  gdtr_base_to_reg,
    output      [15:0]  gdtr_limit_to_reg,
 
    output      [31:0]  idtr_base_to_reg,
    output      [15:0]  idtr_limit_to_reg,
 
    output      [31:0]  dr0_to_reg,
    output      [31:0]  dr1_to_reg,
    output      [31:0]  dr2_to_reg,
    output      [31:0]  dr3_to_reg,
    output      [3:0]   dr6_breakpoints_to_reg,
    output              dr6_b12_to_reg,
    output              dr6_bd_to_reg,
    output              dr6_bs_to_reg,
    output              dr6_bt_to_reg,
    output      [31:0]  dr7_to_reg,
 
    output      [15:0]  es_to_reg,
    output      [15:0]  ds_to_reg,
    output      [15:0]  ss_to_reg,
    output      [15:0]  fs_to_reg,
    output      [15:0]  gs_to_reg,
    output      [15:0]  cs_to_reg,
    output      [15:0]  ldtr_to_reg,
    output      [15:0]  tr_to_reg,
 
    output      [63:0]  es_cache_to_reg,
    output      [63:0]  ds_cache_to_reg,
    output      [63:0]  ss_cache_to_reg,
    output      [63:0]  fs_cache_to_reg,
    output      [63:0]  gs_cache_to_reg,
    output      [63:0]  cs_cache_to_reg,
    output      [63:0]  ldtr_cache_to_reg,
    output      [63:0]  tr_cache_to_reg,
 
    output              es_cache_valid_to_reg,
    output              ds_cache_valid_to_reg,
    output              ss_cache_valid_to_reg,
    output              fs_cache_valid_to_reg,
    output              gs_cache_valid_to_reg,
    output              cs_cache_valid_to_reg,
    output              ldtr_cache_valid_to_reg,
 
    output      [1:0]   es_rpl_to_reg,
    output      [1:0]   ds_rpl_to_reg,
    output      [1:0]   ss_rpl_to_reg,
    output      [1:0]   fs_rpl_to_reg,
    output      [1:0]   gs_rpl_to_reg,
    output      [1:0]   cs_rpl_to_reg,
    output      [1:0]   ldtr_rpl_to_reg,
    output      [1:0]   tr_rpl_to_reg,
 
    //output
    input       [31:0]  eax,
    input       [31:0]  ebx,
    input       [31:0]  ecx,
    input       [31:0]  edx,
    input       [31:0]  esi,
    input       [31:0]  edi,
    input       [31:0]  ebp,
    input       [31:0]  esp,
 
    input               cr0_pe,
    input               cr0_mp,
    input               cr0_em,
    input               cr0_ts,
    input               cr0_ne,
    input               cr0_wp,
    input               cr0_am,
    input               cr0_nw,
    input               cr0_cd,
    input               cr0_pg,
 
    input       [31:0]  cr2,
    input       [31:0]  cr3,
 
    input               cflag,
    input               pflag,
    input               aflag,
    input               zflag,
    input               sflag,
    input               oflag,
    input               tflag,
    input               iflag,
    input               dflag,
    input       [1:0]   iopl,
    input               ntflag,
    input               rflag,
    input               vmflag,
    input               acflag,
    input               idflag,
 
    input       [31:0]  gdtr_base,
    input       [15:0]  gdtr_limit,
 
    input       [31:0]  idtr_base,
    input       [15:0]  idtr_limit,
 
    input       [31:0]  dr0,
    input       [31:0]  dr1,
    input       [31:0]  dr2,
    input       [31:0]  dr3,
    input       [3:0]   dr6_breakpoints,
    input               dr6_b12,
    input               dr6_bd,
    input               dr6_bs,
    input               dr6_bt,
    input       [31:0]  dr7,
 
    input       [15:0]  es,
    input       [15:0]  ds,
    input       [15:0]  ss,
    input       [15:0]  fs,
    input       [15:0]  gs,
    input       [15:0]  cs,
    input       [15:0]  ldtr,
    input       [15:0]  tr,
 
    input       [63:0]  es_cache,
    input       [63:0]  ds_cache,
    input       [63:0]  ss_cache,
    input       [63:0]  fs_cache,
    input       [63:0]  gs_cache,
    input       [63:0]  cs_cache,
    input       [63:0]  ldtr_cache,
    input       [63:0]  tr_cache,
 
    input               es_cache_valid,
    input               ds_cache_valid,
    input               ss_cache_valid,
    input               fs_cache_valid,
    input               gs_cache_valid,
    input               cs_cache_valid,
    input               ldtr_cache_valid,
 
    input       [1:0]   es_rpl,
    input       [1:0]   ds_rpl,
    input       [1:0]   ss_rpl,
    input       [1:0]   fs_rpl,
    input       [1:0]   gs_rpl,
    input       [1:0]   cs_rpl,
    input       [1:0]   ldtr_rpl,
    input       [1:0]   tr_rpl
);
 
//------------------------------------------------------------------------------ flags
wire sflag_result;
wire zflag_result;
wire pflag_result;
 
wire w_logic_arith;
wire w_sub_arith;
 
wire aflag_arith;
wire cflag_arith;
wire oflag_arith;
 
assign sflag_result =   (wr_is_8bit)?       result[7] :
                        (wr_operand_16bit)? result[15] :
                                            result[31];
 
assign zflag_result =   (wr_is_8bit)?       result[7:0]  == 8'd0 :
                        (wr_operand_16bit)? result[15:0] == 16'd0 :
                                            result[31:0] == 32'd0;
 
assign wr_zflag_result = zflag_result;
 
assign pflag_result = ~(result[7] ^ result[6] ^ result[5] ^ result[4] ^ result[3] ^ result[2] ^ result[1] ^ result[0]);
 
assign w_logic_arith =
    ~(wr_arith_index[3]) || // logic OSZAPC: AAM,AAD,AAA,AAS,DAA,DAS, BSF,BSR, Shift
    wr_arith_index == (`ARITH_VALID | `ARITH_OR) || wr_arith_index == (`ARITH_VALID | `ARITH_AND) || wr_arith_index == (`ARITH_VALID | `ARITH_XOR);
 
assign w_sub_arith  = wr_arith_index == (`ARITH_VALID | `ARITH_SBB) || wr_arith_index == (`ARITH_VALID | `ARITH_SUB) || wr_arith_index == (`ARITH_VALID | `ARITH_CMP);
 
//-----
 
assign aflag_arith = (w_logic_arith)? 1'b0 : wr_src[4] ^ wr_dst[4] ^ result[4];
 
assign cflag_arith =
    (w_logic_arith)?                                    1'b0 :
    (wr_is_8bit)?                                       wr_src[8]  ^ wr_dst[8]  ^ result[8] :
    (wr_operand_16bit)?                                 wr_src[16] ^ wr_dst[16] ^ result[16] :
    (wr_arith_index == (`ARITH_VALID | `ARITH_ADD))?    wr_arith_add_carry :
    (wr_arith_index == (`ARITH_VALID | `ARITH_ADC))?    wr_arith_adc_carry :
    (wr_arith_index == (`ARITH_VALID | `ARITH_SBB))?    wr_arith_sbb_carry :
                                                        wr_arith_sub_carry; // `ARITH_SUB || `ARITH_CMP
assign oflag_arith =
    (w_logic_arith)?                    1'b0 :
    (w_sub_arith && wr_is_8bit)?        (wr_src[7]  == 1'b0 && wr_dst[7]  && result[7]  == 1'b0) || (wr_src[7]  && wr_dst[7]  == 1'b0 && result[7]) :
    (w_sub_arith && wr_operand_16bit)?  (wr_src[15] == 1'b0 && wr_dst[15] && result[15] == 1'b0) || (wr_src[15] && wr_dst[15] == 1'b0 && result[15]) :
    (w_sub_arith)?                      (wr_src[31] == 1'b0 && wr_dst[31] && result[31] == 1'b0) || (wr_src[31] && wr_dst[31] == 1'b0 && result[31]) :
    (wr_is_8bit)?                       (wr_src[7]  == 1'b0 && wr_dst[7]  == 1'b0 && result[7])  || (wr_src[7]  && wr_dst[7]  && result[7]  == 1'b0) :
    (wr_operand_16bit)?                 (wr_src[15] == 1'b0 && wr_dst[15] == 1'b0 && result[15]) || (wr_src[15] && wr_dst[15] && result[15] == 1'b0) :
                                        (wr_src[31] == 1'b0 && wr_dst[31] == 1'b0 && result[31]) || (wr_src[31] && wr_dst[31] && result[31] == 1'b0);
 
//------------------------------------------------------------------------------ task
 
wire [31:0] task_eflags;
wire [15:0] task_es;
wire [15:0] task_cs;
wire [15:0] task_ss;
wire [15:0] task_ds;
wire [15:0] task_fs;
wire [15:0] task_gs;
wire [15:0] task_ldtr;
wire [15:0] task_trap;
 
assign task_eflags= (glob_descriptor[`DESC_BITS_TYPE] <= 4'd3)? { 16'd0, exe_buffer_shifted[383:368] } : exe_buffer_shifted[399:368];
 
assign task_es    = exe_buffer_shifted[111:96];
assign task_cs    = exe_buffer_shifted[95:80];
assign task_ss    = exe_buffer_shifted[79:64];
assign task_ds    = exe_buffer_shifted[63:48];
 
assign task_fs    = (glob_descriptor[`DESC_BITS_TYPE] <= 4'd3)? 16'd0 : exe_buffer_shifted[47:32];
assign task_gs    = (glob_descriptor[`DESC_BITS_TYPE] <= 4'd3)? 16'd0 : exe_buffer_shifted[31:16];
 
assign task_ldtr  = (glob_descriptor[`DESC_BITS_TYPE] <= 4'd3)? exe_buffer_shifted[47:32] : exe_buffer_shifted[15:0];
 
assign task_trap  = exe_buffer[15:0];
 
/*******************************************************************************SCRIPT
 
NO_ALWAYS_BLOCK(eax);
NO_ALWAYS_BLOCK(ebx);
NO_ALWAYS_BLOCK(ecx);
NO_ALWAYS_BLOCK(edx);
NO_ALWAYS_BLOCK(esi);
NO_ALWAYS_BLOCK(edi);
NO_ALWAYS_BLOCK(ebp);
NO_ALWAYS_BLOCK(esp);
 
NO_ALWAYS_BLOCK(cr0_pe);
NO_ALWAYS_BLOCK(cr0_mp);
NO_ALWAYS_BLOCK(cr0_em);
NO_ALWAYS_BLOCK(cr0_ts);
NO_ALWAYS_BLOCK(cr0_ne);
NO_ALWAYS_BLOCK(cr0_wp);
NO_ALWAYS_BLOCK(cr0_am);
NO_ALWAYS_BLOCK(cr0_nw);
NO_ALWAYS_BLOCK(cr0_cd);
NO_ALWAYS_BLOCK(cr0_pg);
 
NO_ALWAYS_BLOCK(cr2);
NO_ALWAYS_BLOCK(cr3);
 
NO_ALWAYS_BLOCK(cflag);
NO_ALWAYS_BLOCK(pflag);
NO_ALWAYS_BLOCK(aflag);
NO_ALWAYS_BLOCK(zflag);
NO_ALWAYS_BLOCK(sflag);
NO_ALWAYS_BLOCK(oflag);
NO_ALWAYS_BLOCK(tflag);
NO_ALWAYS_BLOCK(iflag);
NO_ALWAYS_BLOCK(dflag);
NO_ALWAYS_BLOCK(iopl);
NO_ALWAYS_BLOCK(ntflag);
NO_ALWAYS_BLOCK(rflag);
NO_ALWAYS_BLOCK(vmflag);
NO_ALWAYS_BLOCK(acflag);
NO_ALWAYS_BLOCK(idflag);
 
NO_ALWAYS_BLOCK(gdtr_base);
NO_ALWAYS_BLOCK(gdtr_limit);
 
NO_ALWAYS_BLOCK(idtr_base);
NO_ALWAYS_BLOCK(idtr_limit);
 
NO_ALWAYS_BLOCK(dr0);
NO_ALWAYS_BLOCK(dr1);
NO_ALWAYS_BLOCK(dr2);
NO_ALWAYS_BLOCK(dr3);
NO_ALWAYS_BLOCK(dr6_breakpoints);
NO_ALWAYS_BLOCK(dr6_b12);
NO_ALWAYS_BLOCK(dr6_bd);
NO_ALWAYS_BLOCK(dr6_bs);
NO_ALWAYS_BLOCK(dr6_bt);
NO_ALWAYS_BLOCK(dr7);
 
NO_ALWAYS_BLOCK(es);
NO_ALWAYS_BLOCK(ds);
NO_ALWAYS_BLOCK(ss);
NO_ALWAYS_BLOCK(fs);
NO_ALWAYS_BLOCK(gs);
NO_ALWAYS_BLOCK(cs);
NO_ALWAYS_BLOCK(ldtr);
NO_ALWAYS_BLOCK(tr);
 
NO_ALWAYS_BLOCK(es_cache);
NO_ALWAYS_BLOCK(ds_cache);
NO_ALWAYS_BLOCK(ss_cache);
NO_ALWAYS_BLOCK(fs_cache);
NO_ALWAYS_BLOCK(gs_cache);
NO_ALWAYS_BLOCK(cs_cache);
NO_ALWAYS_BLOCK(ldtr_cache);
NO_ALWAYS_BLOCK(tr_cache);
 
NO_ALWAYS_BLOCK(es_cache_valid);
NO_ALWAYS_BLOCK(ds_cache_valid);
NO_ALWAYS_BLOCK(ss_cache_valid);
NO_ALWAYS_BLOCK(fs_cache_valid);
NO_ALWAYS_BLOCK(gs_cache_valid);
NO_ALWAYS_BLOCK(cs_cache_valid);
NO_ALWAYS_BLOCK(ldtr_cache_valid);
 
NO_ALWAYS_BLOCK(es_rpl);
NO_ALWAYS_BLOCK(ds_rpl);
NO_ALWAYS_BLOCK(ss_rpl);
NO_ALWAYS_BLOCK(fs_rpl);
NO_ALWAYS_BLOCK(gs_rpl);
NO_ALWAYS_BLOCK(cs_rpl);
NO_ALWAYS_BLOCK(ldtr_rpl);
NO_ALWAYS_BLOCK(tr_rpl);
*/
 
//------------------------------------------------------------------------------
 
// synthesis translate_off
wire _unused_ok = &{ 1'b0, glob_param_1[31:21], glob_param_5[31:22], glob_param_5[20:19], glob_param_5[17], glob_param_5[15], glob_param_5[5], glob_param_5[3], glob_param_5[1], wr_decoder[7:6], wr_decoder[2:0],
    wr_src[30:17], wr_src[14:9], wr_src[6:5], wr_src[3:0], wr_dst[30:17], wr_dst[14:9], wr_dst[6:5], wr_dst[3:0], exe_buffer_shifted[431:400],
    task_eflags[31:22], task_eflags[20:19], task_eflags[15], task_eflags[5], task_eflags[3], task_eflags[1], task_trap[15:1], 1'b0 };
// synthesis translate_on
 
//------------------------------------------------------------------------------
 
`include "autogen/write_commands.v"
 
//------------------------------------------------------------------------------
 
endmodule

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[/] [ao486/] [trunk/] [rtl/] [ao486/] [pipeline/] [write_commands.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	alfik	`/*`
2			`* Copyright (c) 2014, Aleksander Osman`
3			`* All rights reserved.`
4			`*`
5			`* Redistribution and use in source and binary forms, with or without`
6			`* modification, are permitted provided that the following conditions are met:`
7			`*`
8			`* * Redistributions of source code must retain the above copyright notice, this`
9			`* list of conditions and the following disclaimer.`
10			`*`
11			`* * Redistributions in binary form must reproduce the above copyright notice,`
12			`* this list of conditions and the following disclaimer in the documentation`
13			`* and/or other materials provided with the distribution.`
14			`*`
15			`* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"`
16			`* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE`
17			`* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE`
18			`* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE`
19			`* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL`
20			`* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR`
21			`* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER`
22			`* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,`
23			`* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE`
24			`* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.`
25			`*/`
26
27			`include "defines.v"
28
29			`//PARSED_COMMENTS: this file contains parsed script comments`
30
31			`module write_commands(`
32			`input clk,`
33			`input rst_n,`
34
35			`//general input`
36			`input real_mode,`
37			`input v8086_mode,`
38			`input protected_mode,`
39
40			`input [1:0] cpl,`
41
42			`input [31:0] tr_base,`
43
44			`input [31:0] eip,`
45
46			`input io_allow_check_needed,`
47
48			`input exc_push_error,`
49			`input [31:0] exc_eip,`
50
51			`//global input`
52			`input [63:0] glob_descriptor,`
53			`input [31:0] glob_desc_base,`
54
55			`input [31:0] glob_param_1,`
56			`input [31:0] glob_param_2,`
57			`input [31:0] glob_param_3,`
58			`input [31:0] glob_param_4,`
59			`input [31:0] glob_param_5,`
60
61			`//write`
62			`input wr_ready,`
63			`input [15:0] wr_decoder,`
64			`input [6:0] wr_cmd,`
65			`input [3:0] wr_cmdex,`
66			`input wr_is_8bit,`
67			`input wr_address_16bit,`
68			`input wr_operand_16bit,`
69			`input wr_operand_32bit,`
70			`input wr_mult_overflow,`
71			`input [3:0] wr_arith_index,`
72			`input [1:0] wr_modregrm_mod,`
73			`input [2:0] wr_modregrm_reg,`
74			`input [2:0] wr_modregrm_rm,`
75			`input wr_dst_is_memory,`
76			`input wr_dst_is_reg,`
77			`input wr_dst_is_rm,`
78			`input wr_dst_is_implicit_reg,`
79			`input wr_dst_is_edx_eax,`
80			`input wr_dst_is_eax,`
81
82			`input wr_arith_add_carry,`
83			`input wr_arith_adc_carry,`
84			`input wr_arith_sbb_carry,`
85			`input wr_arith_sub_carry,`
86
87			`input [31:0] result,`
88			`input [31:0] result2,`
89			`input [31:0] wr_src,`
90			`input [31:0] wr_dst,`
91			`input [4:0] result_signals,`
92			`input [31:0] result_push,`
93
94			`input [31:0] exe_buffer,`
95			`input [463:0] exe_buffer_shifted,`
96
97			`//global output`
98			`output wr_glob_param_1_set,`
99			`output [31:0] wr_glob_param_1_value,`
100
101			`output wr_glob_param_3_set,`
102			`output [31:0] wr_glob_param_3_value,`
103
104			`output wr_glob_param_4_set,`
105			`output [31:0] wr_glob_param_4_value,`
106
107			`//debug output`
108			`output wr_debug_trap_clear,`
109			`output wr_debug_task_trigger,`
110
111			`//exception`
112			`output wr_int,`
113			`output wr_int_soft_int,`
114			`output wr_int_soft_int_ib,`
115			`output [7:0] wr_int_vector,`
116
117			`output wr_exception_external_set,`
118			`output wr_exception_finished,`
119
120			`output wr_inhibit_interrupts,`
121			`output wr_inhibit_interrupts_and_debug,`
122
123			`//memory`
124			`input write_for_wr_ready,`
125
126			`output write_rmw_virtual,`
127			`output write_virtual,`
128			`output write_rmw_system_dword,`
129			`output write_system_word,`
130			`output write_system_dword,`
131			`output write_system_busy_tss,`
132			`output write_system_touch,`
133
134			`output write_length_word,`
135			`output write_length_dword,`
136
137			`output [31:0] wr_system_dword,`
138			`output [31:0] wr_system_linear,`
139
140			`//write regrm`
141			`output write_regrm,`
142			`output write_eax,`
143			`output wr_regrm_word,`
144			`output wr_regrm_dword,`
145
146			`//write output`
147			`output wr_not_finished,`
148			`output wr_hlt_in_progress,`
149			`output wr_string_in_progress,`
150			`output wr_waiting,`
151
152			`output wr_req_reset_pr,`
153			`output wr_req_reset_dec,`
154			`output wr_req_reset_micro,`
155			`output wr_req_reset_rd,`
156			`output wr_req_reset_exe,`
157
158			`output wr_zflag_result,`
159
160			`output reg [1:0] wr_task_rpl,`
161
162			`output wr_one_cycle_wait,`
163
164			`//stack`
165			`output write_stack_virtual,`
166			`output write_new_stack_virtual,`
167
168			`output wr_push_length_word,`
169			`output wr_push_length_dword,`
170
171			`input [31:0] wr_stack_esp,`
172			`input [31:0] wr_new_stack_esp,`
173
174			`output wr_push_ss_fault_check,`
175			`input wr_push_ss_fault,`
176
177			`output wr_new_push_ss_fault_check,`
178			`input wr_new_push_ss_fault,`
179
180			`output [15:0] wr_error_code,`
181
182			`output wr_make_esp_speculative,`
183			`output wr_make_esp_commit,`
184
185			`//string`
186			`input wr_string_ignore,`
187			`input [1:0] wr_prefix_group_1_rep,`
188			`input wr_string_zf_finish,`
189			`input wr_string_es_fault,`
190			`input wr_string_finish,`
191
192			`input [31:0] wr_esi_final,`
193			`input [31:0] wr_edi_final,`
194			`input [31:0] wr_ecx_final,`
195
196			`output wr_string_gp_fault_check,`
197			`output write_string_es_virtual,`
198
199			`//io write`
200			`output write_io,`
201			`input write_io_for_wr_ready,`
202
203			`//segment`
204			`output [15:0] wr_seg_sel,`
205			`output wr_seg_cache_valid,`
206			`output [1:0] wr_seg_rpl,`
207			`output [63:0] wr_seg_cache_mask,`
208
209			`output write_seg_cache,`
210			`output write_seg_sel,`
211			`output write_seg_cache_valid,`
212			`output write_seg_rpl,`
213
214			`output wr_validate_seg_regs,`
215
216			`//flush tlb`
217			`output tlbflushall_do,`
218
219			`//---------------------`
220
221			`output [31:0] eax_to_reg,`
222			`output [31:0] ebx_to_reg,`
223			`output [31:0] ecx_to_reg,`
224			`output [31:0] edx_to_reg,`
225			`output [31:0] esi_to_reg,`
226			`output [31:0] edi_to_reg,`
227			`output [31:0] ebp_to_reg,`
228			`output [31:0] esp_to_reg,`
229
230			`output cr0_pe_to_reg,`
231			`output cr0_mp_to_reg,`
232			`output cr0_em_to_reg,`
233			`output cr0_ts_to_reg,`
234			`output cr0_ne_to_reg,`
235			`output cr0_wp_to_reg,`
236			`output cr0_am_to_reg,`
237			`output cr0_nw_to_reg,`
238			`output cr0_cd_to_reg,`
239			`output cr0_pg_to_reg,`
240
241			`output [31:0] cr2_to_reg,`
242			`output [31:0] cr3_to_reg,`
243
244			`output cflag_to_reg,`
245			`output pflag_to_reg,`
246			`output aflag_to_reg,`
247			`output zflag_to_reg,`
248			`output sflag_to_reg,`
249			`output oflag_to_reg,`
250			`output tflag_to_reg,`
251			`output iflag_to_reg,`
252			`output dflag_to_reg,`
253			`output [1:0] iopl_to_reg,`
254			`output ntflag_to_reg,`
255			`output rflag_to_reg,`
256			`output vmflag_to_reg,`
257			`output acflag_to_reg,`
258			`output idflag_to_reg,`
259
260			`output [31:0] gdtr_base_to_reg,`
261			`output [15:0] gdtr_limit_to_reg,`
262
263			`output [31:0] idtr_base_to_reg,`
264			`output [15:0] idtr_limit_to_reg,`
265
266			`output [31:0] dr0_to_reg,`
267			`output [31:0] dr1_to_reg,`
268			`output [31:0] dr2_to_reg,`
269			`output [31:0] dr3_to_reg,`
270			`output [3:0] dr6_breakpoints_to_reg,`
271			`output dr6_b12_to_reg,`
272			`output dr6_bd_to_reg,`
273			`output dr6_bs_to_reg,`
274			`output dr6_bt_to_reg,`
275			`output [31:0] dr7_to_reg,`
276
277			`output [15:0] es_to_reg,`
278			`output [15:0] ds_to_reg,`
279			`output [15:0] ss_to_reg,`
280			`output [15:0] fs_to_reg,`
281			`output [15:0] gs_to_reg,`
282			`output [15:0] cs_to_reg,`
283			`output [15:0] ldtr_to_reg,`
284			`output [15:0] tr_to_reg,`
285
286			`output [63:0] es_cache_to_reg,`
287			`output [63:0] ds_cache_to_reg,`
288			`output [63:0] ss_cache_to_reg,`
289			`output [63:0] fs_cache_to_reg,`
290			`output [63:0] gs_cache_to_reg,`
291			`output [63:0] cs_cache_to_reg,`
292			`output [63:0] ldtr_cache_to_reg,`
293			`output [63:0] tr_cache_to_reg,`
294
295			`output es_cache_valid_to_reg,`
296			`output ds_cache_valid_to_reg,`
297			`output ss_cache_valid_to_reg,`
298			`output fs_cache_valid_to_reg,`
299			`output gs_cache_valid_to_reg,`
300			`output cs_cache_valid_to_reg,`
301			`output ldtr_cache_valid_to_reg,`
302
303			`output [1:0] es_rpl_to_reg,`
304			`output [1:0] ds_rpl_to_reg,`
305			`output [1:0] ss_rpl_to_reg,`
306			`output [1:0] fs_rpl_to_reg,`
307			`output [1:0] gs_rpl_to_reg,`
308			`output [1:0] cs_rpl_to_reg,`
309			`output [1:0] ldtr_rpl_to_reg,`
310			`output [1:0] tr_rpl_to_reg,`
311
312			`//output`
313			`input [31:0] eax,`
314			`input [31:0] ebx,`
315			`input [31:0] ecx,`
316			`input [31:0] edx,`
317			`input [31:0] esi,`
318			`input [31:0] edi,`
319			`input [31:0] ebp,`
320			`input [31:0] esp,`
321
322			`input cr0_pe,`
323			`input cr0_mp,`
324			`input cr0_em,`
325			`input cr0_ts,`
326			`input cr0_ne,`
327			`input cr0_wp,`
328			`input cr0_am,`
329			`input cr0_nw,`
330			`input cr0_cd,`
331			`input cr0_pg,`
332
333			`input [31:0] cr2,`
334			`input [31:0] cr3,`
335
336			`input cflag,`
337			`input pflag,`
338			`input aflag,`
339			`input zflag,`
340			`input sflag,`
341			`input oflag,`
342			`input tflag,`
343			`input iflag,`
344			`input dflag,`
345			`input [1:0] iopl,`
346			`input ntflag,`
347			`input rflag,`
348			`input vmflag,`
349			`input acflag,`
350			`input idflag,`
351
352			`input [31:0] gdtr_base,`
353			`input [15:0] gdtr_limit,`
354
355			`input [31:0] idtr_base,`
356			`input [15:0] idtr_limit,`
357
358			`input [31:0] dr0,`
359			`input [31:0] dr1,`
360			`input [31:0] dr2,`
361			`input [31:0] dr3,`
362			`input [3:0] dr6_breakpoints,`
363			`input dr6_b12,`
364			`input dr6_bd,`
365			`input dr6_bs,`
366			`input dr6_bt,`
367			`input [31:0] dr7,`
368
369			`input [15:0] es,`
370			`input [15:0] ds,`
371			`input [15:0] ss,`
372			`input [15:0] fs,`
373			`input [15:0] gs,`
374			`input [15:0] cs,`
375			`input [15:0] ldtr,`
376			`input [15:0] tr,`
377
378			`input [63:0] es_cache,`
379			`input [63:0] ds_cache,`
380			`input [63:0] ss_cache,`
381			`input [63:0] fs_cache,`
382			`input [63:0] gs_cache,`
383			`input [63:0] cs_cache,`
384			`input [63:0] ldtr_cache,`
385			`input [63:0] tr_cache,`
386
387			`input es_cache_valid,`
388			`input ds_cache_valid,`
389			`input ss_cache_valid,`
390			`input fs_cache_valid,`
391			`input gs_cache_valid,`
392			`input cs_cache_valid,`
393			`input ldtr_cache_valid,`
394
395			`input [1:0] es_rpl,`
396			`input [1:0] ds_rpl,`
397			`input [1:0] ss_rpl,`
398			`input [1:0] fs_rpl,`
399			`input [1:0] gs_rpl,`
400			`input [1:0] cs_rpl,`
401			`input [1:0] ldtr_rpl,`
402			`input [1:0] tr_rpl`
403			`);`
404
405			`//------------------------------------------------------------------------------ flags`
406			`wire sflag_result;`
407			`wire zflag_result;`
408			`wire pflag_result;`
409
410			`wire w_logic_arith;`
411			`wire w_sub_arith;`
412
413			`wire aflag_arith;`
414			`wire cflag_arith;`
415			`wire oflag_arith;`
416
417			`assign sflag_result = (wr_is_8bit)? result[7] :`
418			`(wr_operand_16bit)? result[15] :`
419			`result[31];`
420
421			`assign zflag_result = (wr_is_8bit)? result[7:0] == 8'd0 :`
422			`(wr_operand_16bit)? result[15:0] == 16'd0 :`
423			`result[31:0] == 32'd0;`
424
425			`assign wr_zflag_result = zflag_result;`
426
427			`assign pflag_result = ~(result[7] ^ result[6] ^ result[5] ^ result[4] ^ result[3] ^ result[2] ^ result[1] ^ result[0]);`
428
429			`assign w_logic_arith =`
430			`~(wr_arith_index[3]) \|\| // logic OSZAPC: AAM,AAD,AAA,AAS,DAA,DAS, BSF,BSR, Shift`
431			wr_arith_index == (`ARITH_VALID \| `ARITH_OR) \|\| wr_arith_index == (`ARITH_VALID \| `ARITH_AND) \|\| wr_arith_index == (`ARITH_VALID \| `ARITH_XOR);
432
433			assign w_sub_arith = wr_arith_index == (`ARITH_VALID \| `ARITH_SBB) \|\| wr_arith_index == (`ARITH_VALID \| `ARITH_SUB) \|\| wr_arith_index == (`ARITH_VALID \| `ARITH_CMP);
434
435			`//-----`
436
437			`assign aflag_arith = (w_logic_arith)? 1'b0 : wr_src[4] ^ wr_dst[4] ^ result[4];`
438
439			`assign cflag_arith =`
440			`(w_logic_arith)? 1'b0 :`
441			`(wr_is_8bit)? wr_src[8] ^ wr_dst[8] ^ result[8] :`
442			`(wr_operand_16bit)? wr_src[16] ^ wr_dst[16] ^ result[16] :`
443			(wr_arith_index == (`ARITH_VALID \| `ARITH_ADD))? wr_arith_add_carry :
444			(wr_arith_index == (`ARITH_VALID \| `ARITH_ADC))? wr_arith_adc_carry :
445			(wr_arith_index == (`ARITH_VALID \| `ARITH_SBB))? wr_arith_sbb_carry :
446			wr_arith_sub_carry; // `ARITH_SUB \|\| `ARITH_CMP
447			`assign oflag_arith =`
448			`(w_logic_arith)? 1'b0 :`
449			`(w_sub_arith && wr_is_8bit)? (wr_src[7] == 1'b0 && wr_dst[7] && result[7] == 1'b0) \|\| (wr_src[7] && wr_dst[7] == 1'b0 && result[7]) :`
450			`(w_sub_arith && wr_operand_16bit)? (wr_src[15] == 1'b0 && wr_dst[15] && result[15] == 1'b0) \|\| (wr_src[15] && wr_dst[15] == 1'b0 && result[15]) :`
451			`(w_sub_arith)? (wr_src[31] == 1'b0 && wr_dst[31] && result[31] == 1'b0) \|\| (wr_src[31] && wr_dst[31] == 1'b0 && result[31]) :`
452			`(wr_is_8bit)? (wr_src[7] == 1'b0 && wr_dst[7] == 1'b0 && result[7]) \|\| (wr_src[7] && wr_dst[7] && result[7] == 1'b0) :`
453			`(wr_operand_16bit)? (wr_src[15] == 1'b0 && wr_dst[15] == 1'b0 && result[15]) \|\| (wr_src[15] && wr_dst[15] && result[15] == 1'b0) :`
454			`(wr_src[31] == 1'b0 && wr_dst[31] == 1'b0 && result[31]) \|\| (wr_src[31] && wr_dst[31] && result[31] == 1'b0);`
455
456			`//------------------------------------------------------------------------------ task`
457
458			`wire [31:0] task_eflags;`
459			`wire [15:0] task_es;`
460			`wire [15:0] task_cs;`
461			`wire [15:0] task_ss;`
462			`wire [15:0] task_ds;`
463			`wire [15:0] task_fs;`
464			`wire [15:0] task_gs;`
465			`wire [15:0] task_ldtr;`
466			`wire [15:0] task_trap;`
467
468			assign task_eflags= (glob_descriptor[`DESC_BITS_TYPE] <= 4'd3)? { 16'd0, exe_buffer_shifted[383:368] } : exe_buffer_shifted[399:368];
469
470			`assign task_es = exe_buffer_shifted[111:96];`
471			`assign task_cs = exe_buffer_shifted[95:80];`
472			`assign task_ss = exe_buffer_shifted[79:64];`
473			`assign task_ds = exe_buffer_shifted[63:48];`
474
475			assign task_fs = (glob_descriptor[`DESC_BITS_TYPE] <= 4'd3)? 16'd0 : exe_buffer_shifted[47:32];
476			assign task_gs = (glob_descriptor[`DESC_BITS_TYPE] <= 4'd3)? 16'd0 : exe_buffer_shifted[31:16];
477
478			assign task_ldtr = (glob_descriptor[`DESC_BITS_TYPE] <= 4'd3)? exe_buffer_shifted[47:32] : exe_buffer_shifted[15:0];
479
480			`assign task_trap = exe_buffer[15:0];`
481
482			`/*******************************************************************************SCRIPT`
483
484			`NO_ALWAYS_BLOCK(eax);`
485			`NO_ALWAYS_BLOCK(ebx);`
486			`NO_ALWAYS_BLOCK(ecx);`
487			`NO_ALWAYS_BLOCK(edx);`
488			`NO_ALWAYS_BLOCK(esi);`
489			`NO_ALWAYS_BLOCK(edi);`
490			`NO_ALWAYS_BLOCK(ebp);`
491			`NO_ALWAYS_BLOCK(esp);`
492
493			`NO_ALWAYS_BLOCK(cr0_pe);`
494			`NO_ALWAYS_BLOCK(cr0_mp);`
495			`NO_ALWAYS_BLOCK(cr0_em);`
496			`NO_ALWAYS_BLOCK(cr0_ts);`
497			`NO_ALWAYS_BLOCK(cr0_ne);`
498			`NO_ALWAYS_BLOCK(cr0_wp);`
499			`NO_ALWAYS_BLOCK(cr0_am);`
500			`NO_ALWAYS_BLOCK(cr0_nw);`
501			`NO_ALWAYS_BLOCK(cr0_cd);`
502			`NO_ALWAYS_BLOCK(cr0_pg);`
503
504			`NO_ALWAYS_BLOCK(cr2);`
505			`NO_ALWAYS_BLOCK(cr3);`
506
507			`NO_ALWAYS_BLOCK(cflag);`
508			`NO_ALWAYS_BLOCK(pflag);`
509			`NO_ALWAYS_BLOCK(aflag);`
510			`NO_ALWAYS_BLOCK(zflag);`
511			`NO_ALWAYS_BLOCK(sflag);`
512			`NO_ALWAYS_BLOCK(oflag);`
513			`NO_ALWAYS_BLOCK(tflag);`
514			`NO_ALWAYS_BLOCK(iflag);`
515			`NO_ALWAYS_BLOCK(dflag);`
516			`NO_ALWAYS_BLOCK(iopl);`
517			`NO_ALWAYS_BLOCK(ntflag);`
518			`NO_ALWAYS_BLOCK(rflag);`
519			`NO_ALWAYS_BLOCK(vmflag);`
520			`NO_ALWAYS_BLOCK(acflag);`
521			`NO_ALWAYS_BLOCK(idflag);`
522
523			`NO_ALWAYS_BLOCK(gdtr_base);`
524			`NO_ALWAYS_BLOCK(gdtr_limit);`
525
526			`NO_ALWAYS_BLOCK(idtr_base);`
527			`NO_ALWAYS_BLOCK(idtr_limit);`
528
529			`NO_ALWAYS_BLOCK(dr0);`
530			`NO_ALWAYS_BLOCK(dr1);`
531			`NO_ALWAYS_BLOCK(dr2);`
532			`NO_ALWAYS_BLOCK(dr3);`
533			`NO_ALWAYS_BLOCK(dr6_breakpoints);`
534			`NO_ALWAYS_BLOCK(dr6_b12);`
535			`NO_ALWAYS_BLOCK(dr6_bd);`
536			`NO_ALWAYS_BLOCK(dr6_bs);`
537			`NO_ALWAYS_BLOCK(dr6_bt);`
538			`NO_ALWAYS_BLOCK(dr7);`
539
540			`NO_ALWAYS_BLOCK(es);`
541			`NO_ALWAYS_BLOCK(ds);`
542			`NO_ALWAYS_BLOCK(ss);`
543			`NO_ALWAYS_BLOCK(fs);`
544			`NO_ALWAYS_BLOCK(gs);`
545			`NO_ALWAYS_BLOCK(cs);`
546			`NO_ALWAYS_BLOCK(ldtr);`
547			`NO_ALWAYS_BLOCK(tr);`
548
549			`NO_ALWAYS_BLOCK(es_cache);`
550			`NO_ALWAYS_BLOCK(ds_cache);`
551			`NO_ALWAYS_BLOCK(ss_cache);`
552			`NO_ALWAYS_BLOCK(fs_cache);`
553			`NO_ALWAYS_BLOCK(gs_cache);`
554			`NO_ALWAYS_BLOCK(cs_cache);`
555			`NO_ALWAYS_BLOCK(ldtr_cache);`
556			`NO_ALWAYS_BLOCK(tr_cache);`
557
558			`NO_ALWAYS_BLOCK(es_cache_valid);`
559			`NO_ALWAYS_BLOCK(ds_cache_valid);`
560			`NO_ALWAYS_BLOCK(ss_cache_valid);`
561			`NO_ALWAYS_BLOCK(fs_cache_valid);`
562			`NO_ALWAYS_BLOCK(gs_cache_valid);`
563			`NO_ALWAYS_BLOCK(cs_cache_valid);`
564			`NO_ALWAYS_BLOCK(ldtr_cache_valid);`
565
566			`NO_ALWAYS_BLOCK(es_rpl);`
567			`NO_ALWAYS_BLOCK(ds_rpl);`
568			`NO_ALWAYS_BLOCK(ss_rpl);`
569			`NO_ALWAYS_BLOCK(fs_rpl);`
570			`NO_ALWAYS_BLOCK(gs_rpl);`
571			`NO_ALWAYS_BLOCK(cs_rpl);`
572			`NO_ALWAYS_BLOCK(ldtr_rpl);`
573			`NO_ALWAYS_BLOCK(tr_rpl);`
574			`*/`
575
576			`//------------------------------------------------------------------------------`
577
578			`// synthesis translate_off`
579			`wire _unused_ok = &{ 1'b0, glob_param_1[31:21], glob_param_5[31:22], glob_param_5[20:19], glob_param_5[17], glob_param_5[15], glob_param_5[5], glob_param_5[3], glob_param_5[1], wr_decoder[7:6], wr_decoder[2:0],`
580			`wr_src[30:17], wr_src[14:9], wr_src[6:5], wr_src[3:0], wr_dst[30:17], wr_dst[14:9], wr_dst[6:5], wr_dst[3:0], exe_buffer_shifted[431:400],`
581			`task_eflags[31:22], task_eflags[20:19], task_eflags[15], task_eflags[5], task_eflags[3], task_eflags[1], task_trap[15:1], 1'b0 };`
582			`// synthesis translate_on`
583
584			`//------------------------------------------------------------------------------`
585
586			`include "autogen/write_commands.v"
587
588			`//------------------------------------------------------------------------------`
589
590			`endmodule`