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/*
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* Copyright (c) 2014, Aleksander Osman
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* * Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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`include "defines.v"
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module write_stack(
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input [63:0] glob_descriptor,
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input [31:0] esp,
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input [63:0] ss_cache,
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input [31:0] ss_base,
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input [31:0] ss_limit,
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input [31:0] glob_desc_base,
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input [31:0] glob_desc_limit,
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input wr_operand_16bit,
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input [31:0] wr_stack_offset,
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input wr_new_push_ss_fault_check,
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input wr_push_length_word,
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input wr_push_length_dword,
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input wr_push_ss_fault_check,
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//output
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output [31:0] wr_stack_esp,
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output [31:0] wr_push_linear,
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output [31:0] wr_new_stack_esp,
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output [31:0] wr_new_push_linear,
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output [2:0] wr_push_length,
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output wr_push_ss_fault,
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output wr_new_push_ss_fault
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);
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//------------------------------------------------------------------------------ stack
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wire [2:0] wr_push_length_minus_1;
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assign wr_stack_esp = (ss_cache[`DESC_BIT_D_B])? wr_stack_offset : { esp[31:16], wr_stack_offset[15:0] };
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assign wr_push_linear = ss_base + wr_stack_offset;
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assign wr_push_length = (wr_push_length_word || (~(wr_push_length_dword) && wr_operand_16bit))? 3'd2 : 3'd4;
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assign wr_push_length_minus_1 = wr_push_length - 3'd1;
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//------------------------------------------------------------------------------ write_new_stack_virtual
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wire [31:0] w_new_upper_limit;
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wire w_new_push_not_fit;
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wire w_new_push_limit_overflow;
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assign wr_new_stack_esp = (glob_descriptor[`DESC_BIT_D_B])? wr_stack_offset : { esp[31:16], wr_stack_offset[15:0] };
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assign wr_new_push_linear = glob_desc_base + wr_stack_offset;
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assign w_new_upper_limit = (glob_descriptor[`DESC_BIT_D_B])? 32'hFFFFFFFF : 32'h0000FFFF; //d-b
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// (CODE or not EXPAND-DOWN)
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assign w_new_push_not_fit = (glob_descriptor[43] || ~(glob_descriptor[42]))?
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glob_desc_limit - wr_stack_offset < { 29'd0, wr_push_length_minus_1 } :
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w_new_upper_limit - wr_stack_offset < { 29'd0, wr_push_length_minus_1 };
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assign w_new_push_limit_overflow =
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((glob_descriptor[43] || !glob_descriptor[42]) && wr_stack_offset > glob_desc_limit) ||
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(!glob_descriptor[43] && glob_descriptor[42] && (wr_stack_offset <= glob_desc_limit || wr_stack_offset > w_new_upper_limit));
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// code or read-only
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assign wr_new_push_ss_fault = wr_new_push_ss_fault_check &&
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(glob_descriptor[43] || ~glob_descriptor[41] || w_new_push_not_fit || w_new_push_limit_overflow);
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//------------------------------------------------------------------------------
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wire [31:0] w_upper_limit;
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wire w_push_not_fit;
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wire w_push_limit_overflow;
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assign w_upper_limit = (ss_cache[`DESC_BIT_D_B])? 32'hFFFFFFFF : 32'h0000FFFF;
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// (CODE or not EXPAND-DOWN)
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assign w_push_not_fit = (ss_cache[43] || ~(ss_cache[42]))?
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ss_limit - wr_stack_offset < { 29'd0, wr_push_length_minus_1 } :
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w_upper_limit - wr_stack_offset < { 29'd0, wr_push_length_minus_1 };
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assign w_push_limit_overflow =
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((ss_cache[43] || !ss_cache[42]) && wr_stack_offset > ss_limit) || (!ss_cache[43] && ss_cache[42] && (wr_stack_offset <= ss_limit || wr_stack_offset > w_upper_limit));
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assign wr_push_ss_fault = wr_push_ss_fault_check && (w_push_not_fit || w_push_limit_overflow);
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//------------------------------------------------------------------------------
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// synthesis translate_off
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wire _unused_ok = &{ 1'b0, glob_descriptor[63:55], glob_descriptor[53:44], glob_descriptor[40:0], esp[15:0], ss_cache[63:55], ss_cache[53:44], ss_cache[41:0], 1'b0 };
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// synthesis translate_on
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//------------------------------------------------------------------------------
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endmodule
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