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URL https://opencores.org/ocsvn/ao486/ao486/trunk

Subversion Repositories ao486

[/] [ao486/] [trunk/] [rtl/] [soc/] [driver_sd/] [driver_sd_hw.tcl] - Blame information for rev 7

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Line No. Rev Author Line
1 7 alfik
# TCL File Generated by Component Editor 14.0
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# Mon Aug 18 20:36:09 CEST 2014
3 2 alfik
# DO NOT MODIFY
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# 
7 7 alfik
# driver_sd "driver_sd" v2.0
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#  2014.08.18.20:36:09
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# 
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# 
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# 
13 7 alfik
# request TCL package from ACDS 14.0
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# 
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package require -exact qsys 14.0
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# 
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# module driver_sd
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# 
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set_module_property DESCRIPTION ""
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set_module_property NAME driver_sd
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set_module_property VERSION 2.0
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set_module_property INTERNAL false
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set_module_property OPAQUE_ADDRESS_MAP true
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set_module_property GROUP ao486
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set_module_property AUTHOR ""
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set_module_property DISPLAY_NAME driver_sd
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set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
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set_module_property EDITABLE true
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set_module_property REPORT_TO_TALKBACK false
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set_module_property ALLOW_GREYBOX_GENERATION false
33 7 alfik
set_module_property REPORT_HIERARCHY false
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# 
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# file sets
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# 
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add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
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set_fileset_property QUARTUS_SYNTH TOP_LEVEL driver_sd
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set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
42 7 alfik
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
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add_fileset_file avalon_master.v VERILOG PATH avalon_master.v
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add_fileset_file avalon_slave.v VERILOG PATH avalon_slave.v
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add_fileset_file card_init.v VERILOG PATH card_init.v
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add_fileset_file card_read.v VERILOG PATH card_read.v
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add_fileset_file card_write.v VERILOG PATH card_write.v
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add_fileset_file cmd.v VERILOG PATH cmd.v
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add_fileset_file dat.v VERILOG PATH dat.v
50 2 alfik
add_fileset_file driver_sd.v VERILOG PATH driver_sd.v TOP_LEVEL_FILE
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# 
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# parameters
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# 
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# 
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# display items
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# 
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# 
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# connection point clock
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# 
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add_interface clock clock end
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set_interface_property clock clockRate 0
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set_interface_property clock ENABLED true
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set_interface_property clock EXPORT_OF ""
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set_interface_property clock PORT_NAME_MAP ""
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set_interface_property clock CMSIS_SVD_VARIABLES ""
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set_interface_property clock SVD_ADDRESS_GROUP ""
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add_interface_port clock clk clk Input 1
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# 
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# connection point avalon_slave_0
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# 
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add_interface avalon_slave_0 avalon end
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set_interface_property avalon_slave_0 addressUnits WORDS
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set_interface_property avalon_slave_0 associatedClock clock
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set_interface_property avalon_slave_0 associatedReset reset_sink
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set_interface_property avalon_slave_0 bitsPerSymbol 8
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set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false
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set_interface_property avalon_slave_0 burstcountUnits WORDS
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set_interface_property avalon_slave_0 explicitAddressSpan 0
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set_interface_property avalon_slave_0 holdTime 0
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set_interface_property avalon_slave_0 linewrapBursts false
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set_interface_property avalon_slave_0 maximumPendingReadTransactions 0
91 7 alfik
set_interface_property avalon_slave_0 maximumPendingWriteTransactions 0
92 2 alfik
set_interface_property avalon_slave_0 readLatency 0
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set_interface_property avalon_slave_0 readWaitTime 1
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set_interface_property avalon_slave_0 setupTime 0
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set_interface_property avalon_slave_0 timingUnits Cycles
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set_interface_property avalon_slave_0 writeWaitTime 0
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set_interface_property avalon_slave_0 ENABLED true
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set_interface_property avalon_slave_0 EXPORT_OF ""
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set_interface_property avalon_slave_0 PORT_NAME_MAP ""
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set_interface_property avalon_slave_0 CMSIS_SVD_VARIABLES ""
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set_interface_property avalon_slave_0 SVD_ADDRESS_GROUP ""
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add_interface_port avalon_slave_0 avs_address address Input 2
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add_interface_port avalon_slave_0 avs_read read Input 1
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add_interface_port avalon_slave_0 avs_readdata readdata Output 32
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add_interface_port avalon_slave_0 avs_write write Input 1
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add_interface_port avalon_slave_0 avs_writedata writedata Input 32
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set_interface_assignment avalon_slave_0 embeddedsw.configuration.isFlash 0
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set_interface_assignment avalon_slave_0 embeddedsw.configuration.isMemoryDevice 0
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set_interface_assignment avalon_slave_0 embeddedsw.configuration.isNonVolatileStorage 0
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set_interface_assignment avalon_slave_0 embeddedsw.configuration.isPrintableDevice 0
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# 
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# connection point avalon_master_0
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# 
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add_interface avalon_master_0 avalon start
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set_interface_property avalon_master_0 addressUnits SYMBOLS
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set_interface_property avalon_master_0 associatedClock clock
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set_interface_property avalon_master_0 associatedReset reset_sink
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set_interface_property avalon_master_0 bitsPerSymbol 8
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set_interface_property avalon_master_0 burstOnBurstBoundariesOnly false
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set_interface_property avalon_master_0 burstcountUnits WORDS
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set_interface_property avalon_master_0 doStreamReads false
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set_interface_property avalon_master_0 doStreamWrites false
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set_interface_property avalon_master_0 holdTime 0
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set_interface_property avalon_master_0 linewrapBursts false
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set_interface_property avalon_master_0 maximumPendingReadTransactions 0
129 7 alfik
set_interface_property avalon_master_0 maximumPendingWriteTransactions 0
130 2 alfik
set_interface_property avalon_master_0 readLatency 0
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set_interface_property avalon_master_0 readWaitTime 1
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set_interface_property avalon_master_0 setupTime 0
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set_interface_property avalon_master_0 timingUnits Cycles
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set_interface_property avalon_master_0 writeWaitTime 0
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set_interface_property avalon_master_0 ENABLED true
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set_interface_property avalon_master_0 EXPORT_OF ""
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set_interface_property avalon_master_0 PORT_NAME_MAP ""
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set_interface_property avalon_master_0 CMSIS_SVD_VARIABLES ""
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set_interface_property avalon_master_0 SVD_ADDRESS_GROUP ""
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add_interface_port avalon_master_0 avm_waitrequest waitrequest Input 1
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add_interface_port avalon_master_0 avm_read read Output 1
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add_interface_port avalon_master_0 avm_readdata readdata Input 32
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add_interface_port avalon_master_0 avm_readdatavalid readdatavalid Input 1
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add_interface_port avalon_master_0 avm_write write Output 1
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add_interface_port avalon_master_0 avm_writedata writedata Output 32
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add_interface_port avalon_master_0 avm_address address Output 32
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# 
151 7 alfik
# connection point reset_sink
152 2 alfik
# 
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add_interface reset_sink reset end
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set_interface_property reset_sink associatedClock clock
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set_interface_property reset_sink synchronousEdges DEASSERT
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set_interface_property reset_sink ENABLED true
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set_interface_property reset_sink EXPORT_OF ""
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set_interface_property reset_sink PORT_NAME_MAP ""
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set_interface_property reset_sink CMSIS_SVD_VARIABLES ""
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set_interface_property reset_sink SVD_ADDRESS_GROUP ""
161 2 alfik
 
162 7 alfik
add_interface_port reset_sink rst_n reset_n Input 1
163 2 alfik
 
164 7 alfik
 
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# 
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# connection point conduit_cmd
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# 
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add_interface conduit_cmd conduit end
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set_interface_property conduit_cmd associatedClock clock
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set_interface_property conduit_cmd associatedReset reset_sink
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set_interface_property conduit_cmd ENABLED true
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set_interface_property conduit_cmd EXPORT_OF ""
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set_interface_property conduit_cmd PORT_NAME_MAP ""
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set_interface_property conduit_cmd CMSIS_SVD_VARIABLES ""
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set_interface_property conduit_cmd SVD_ADDRESS_GROUP ""
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add_interface_port conduit_cmd sd_cmd export Bidir 1
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# 
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# connection point conduit_dat
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# 
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add_interface conduit_dat conduit end
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set_interface_property conduit_dat associatedClock clock
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set_interface_property conduit_dat associatedReset reset_sink
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set_interface_property conduit_dat ENABLED true
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set_interface_property conduit_dat EXPORT_OF ""
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set_interface_property conduit_dat PORT_NAME_MAP ""
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set_interface_property conduit_dat CMSIS_SVD_VARIABLES ""
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set_interface_property conduit_dat SVD_ADDRESS_GROUP ""
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add_interface_port conduit_dat sd_dat export Bidir 4
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# 
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# connection point conduit_clk
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# 
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add_interface conduit_clk conduit end
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set_interface_property conduit_clk associatedClock clock
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set_interface_property conduit_clk associatedReset reset_sink
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set_interface_property conduit_clk ENABLED true
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set_interface_property conduit_clk EXPORT_OF ""
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set_interface_property conduit_clk PORT_NAME_MAP ""
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set_interface_property conduit_clk CMSIS_SVD_VARIABLES ""
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set_interface_property conduit_clk SVD_ADDRESS_GROUP ""
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add_interface_port conduit_clk sd_clk export Output 1
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