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[/] [ao486/] [trunk/] [rtl/] [soc/] [pc_bus/] [pc_bus.v] - Blame information for rev 2

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/*
 * Copyright (c) 2014, Aleksander Osman
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *
 * * Redistributions of source code must retain the above copyright notice, this
 *   list of conditions and the following disclaimer.
 *
 * * Redistributions in binary form must reproduce the above copyright notice,
 *   this list of conditions and the following disclaimer in the documentation
 *   and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
module pc_bus(
    input               clk,
    input               rst_n,
 
    //control slave
    input        [1:0]  ctrl_address,
    input               ctrl_write,
    input       [31:0]  ctrl_writedata,
 
    //memory slave
    input       [29:0]  mem_address,
    input       [3:0]   mem_byteenable,
    input               mem_read,
    output      [31:0]  mem_readdata,
    input               mem_write,
    input       [31:0]  mem_writedata,
    output              mem_waitrequest,
    output              mem_readdatavalid,
    input       [2:0]   mem_burstcount,
 
    //memory master
    output      [31:0]  sdram_address,
    output      [3:0]   sdram_byteenable,
    output              sdram_read,
    input       [31:0]  sdram_readdata,
    output              sdram_write,
    output      [31:0]  sdram_writedata,
    input               sdram_waitrequest,
    input               sdram_readdatavalid,
    output      [2:0]   sdram_burstcount,
 
    //vga master
    output      [31:0]  vga_address,
    output      [3:0]   vga_byteenable,
    output              vga_read,
    input       [31:0]  vga_readdata,
    output              vga_write,
    output      [31:0]  vga_writedata,
    input               vga_waitrequest,
    input               vga_readdatavalid,
    output      [2:0]   vga_burstcount
);
 
//------------------------------------------------------------------------------ ctrl
 
reg [127:0] data_at_0xffffffff;
always @(posedge clk or negedge rst_n) begin
    if(rst_n == 1'b0)                           data_at_0xffffffff <= 128'h0000000000000000000000F000FFF0EA;
    else if(ctrl_write && ctrl_address == 2'd0) data_at_0xffffffff <= { data_at_0xffffffff[127:32], ctrl_writedata };
    else if(ctrl_write && ctrl_address == 2'd1) data_at_0xffffffff <= { data_at_0xffffffff[127:64], ctrl_writedata, data_at_0xffffffff[31:0] };
    else if(ctrl_write && ctrl_address == 2'd2) data_at_0xffffffff <= { data_at_0xffffffff[127:96], ctrl_writedata, data_at_0xffffffff[63:0] };
    else if(ctrl_write && ctrl_address == 2'd3) data_at_0xffffffff <= {                             ctrl_writedata, data_at_0xffffffff[95:0] };
end
 
//------------------------------------------------------------------------------ transaction
 
wire select_vga        = ~(slow_start) && ~(slow_in_progress) && ~(transaction_in_progress) && (mem_read || mem_write) && ({ mem_address, 2'b00 } >= 32'h000A0000 && { mem_address, 2'b00 } < 32'h000C0000);
wire select_sdram      = ~(slow_start) && ~(slow_in_progress) && ~(transaction_in_progress) && (mem_read || mem_write) && ~(select_vga);
 
wire transaction_start = ~(slow_start) && ~(slow_in_progress) && ~(transaction_in_progress) && (mem_read || (mem_write && mem_burstcount > 3'd1));
 
reg transaction_is_read;
always @(posedge clk or negedge rst_n) begin
    if(rst_n == 1'b0)           transaction_is_read <= 1'b0;
    else if(transaction_start)  transaction_is_read <= mem_read;
end
 
reg transaction_select_vga;
always @(posedge clk or negedge rst_n) begin
    if(rst_n == 1'b0)           transaction_select_vga <= 1'b0;
    else if(transaction_start)  transaction_select_vga <= select_vga;
end
 
reg transaction_was_read_accepted;
always @(posedge clk or negedge rst_n) begin
    if(rst_n == 1'b0)                                                               transaction_was_read_accepted <= 1'b1;
    else if(transaction_start && mem_read && mem_waitrequest)                       transaction_was_read_accepted <= 1'b0;
    else if(transaction_start && mem_read)                                          transaction_was_read_accepted <= 1'b1;
    else if(transaction_in_progress && transaction_is_read && ~(mem_waitrequest))   transaction_was_read_accepted <= 1'b1;
end
 
reg [2:0] transaction_burstcount;
always @(posedge clk or negedge rst_n) begin
    if(rst_n == 1'b0)                                                                                               transaction_burstcount <= 3'd0;
    else if(transaction_start && mem_write && ~(mem_waitrequest))                                                   transaction_burstcount <= mem_burstcount - 3'd1;
    else if(transaction_start && (mem_read || mem_write))                                                           transaction_burstcount <= mem_burstcount;
    else if(transaction_in_progress && mem_write         && transaction_burstcount > 3'd0 && ~(mem_waitrequest))    transaction_burstcount <= transaction_burstcount - 3'd1;
    else if(transaction_in_progress && mem_readdatavalid && transaction_burstcount > 3'd0)                          transaction_burstcount <= transaction_burstcount - 3'd1;
end
 
reg [3:0] transaction_byteenable;
always @(posedge clk or negedge rst_n) begin
    if(rst_n == 1'b0)                       transaction_byteenable <= 4'd0;
    else if(transaction_start && mem_read)  transaction_byteenable <= mem_byteenable;
end
 
reg transaction_in_progress;
always @(posedge clk or negedge rst_n) begin
    if(rst_n == 1'b0)                                                                                               transaction_in_progress <= 1'b0;
    else if(transaction_start)                                                                                      transaction_in_progress <= 1'b1;
    else if(transaction_in_progress && mem_write         && transaction_burstcount <= 3'd1 && ~(mem_waitrequest))   transaction_in_progress <= 1'b0;
    else if(transaction_in_progress && mem_readdatavalid && transaction_burstcount <= 3'd1)                         transaction_in_progress <= 1'b0;
end
 
//------------------------------------------------------------------------------ slow
 
wire slow_start = ~(slow_in_progress) && ~(transaction_in_progress) && (mem_read || mem_write) && (
    { mem_address, 2'b00 } == 32'h0009FFF4 ||
    { mem_address, 2'b00 } == 32'h0009FFF8 ||
    { mem_address, 2'b00 } == 32'h0009FFFC ||
 
    { mem_address, 2'b00 } == 32'h000BFFF4 ||
    { mem_address, 2'b00 } == 32'h000BFFF8 ||
    { mem_address, 2'b00 } == 32'h000BFFFC ||
 
    { mem_address, 2'b00 } == 32'hFFFFFFE4 ||
    { mem_address, 2'b00 } == 32'hFFFFFFE8 ||
    { mem_address, 2'b00 } == 32'hFFFFFFEC ||
    { mem_address, 2'b00 } == 32'hFFFFFFF0 ||
    { mem_address, 2'b00 } == 32'hFFFFFFF4 ||
    { mem_address, 2'b00 } == 32'hFFFFFFF8 ||
    { mem_address, 2'b00 } == 32'hFFFFFFFC
);
 
reg slow_in_progress;
always @(posedge clk or negedge rst_n) begin
    if(rst_n == 1'b0)                                                                                       slow_in_progress <= 1'b0;
    else if(slow_start)                                                                                     slow_in_progress <= 1'b1;
 
    else if(slow_write_active && slow_is_vga   && vga_waitrequest == 1'b0   && slow_burstcount <= 3'd1)     slow_in_progress <= 1'b0;
    else if(slow_write_active && slow_is_sdram && sdram_waitrequest == 1'b0 && slow_burstcount <= 3'd1)     slow_in_progress <= 1'b0;
    else if(slow_write_active && slow_is_0xff  &&                              slow_burstcount <= 3'd1)     slow_in_progress <= 1'b0;
 
    else if(slow_read_active && slow_is_vga   && vga_readdatavalid   && slow_burstcount <= 3'd1)            slow_in_progress <= 1'b0;
    else if(slow_read_active && slow_is_sdram && sdram_readdatavalid && slow_burstcount <= 3'd1)            slow_in_progress <= 1'b0;
    else if(slow_read_active && slow_is_0xff  &&                        slow_burstcount <= 3'd1)            slow_in_progress <= 1'b0;
end
 
reg [31:0] slow_address;
always @(posedge clk or negedge rst_n) begin
    if(rst_n == 1'b0)                                                           slow_address <= 32'b0;
    else if(slow_start)                                                         slow_address <= { mem_address, 2'b0 };
 
    else if(slow_write_active && slow_is_vga   && vga_waitrequest   == 1'b0)    slow_address <= slow_address + 32'd4;
    else if(slow_write_active && slow_is_sdram && sdram_waitrequest == 1'b0)    slow_address <= slow_address + 32'd4;
    else if(slow_write_active && slow_is_0xff)                                  slow_address <= slow_address + 32'd4;
 
    else if(slow_read_active && slow_is_vga   && vga_readdatavalid)             slow_address <= slow_address + 32'd4;
    else if(slow_read_active && slow_is_sdram && sdram_readdatavalid)           slow_address <= slow_address + 32'd4;
    else if(slow_read_active && slow_is_0xff)                                   slow_address <= slow_address + 32'd4;
end
 
wire slow_is_vga   = { slow_address[31:2], 2'b0 } >= 32'h000A0000 && { slow_address[31:2], 2'b00 } < 32'h000C0000;
wire slow_is_0xff  = { slow_address[31:2], 2'b0 } >= 32'hFFFFFFF0;
wire slow_is_sdram = ~(slow_is_vga) && ~(slow_is_0xff);
 
reg slow_write_active;
always @(posedge clk or negedge rst_n) begin
    if(rst_n == 1'b0)                                                                                       slow_write_active <= 1'b0;
    else if(slow_start && mem_write)                                                                        slow_write_active <= 1'b1;
 
    else if(slow_write_active && slow_is_vga   && vga_waitrequest == 1'b0   && slow_burstcount <= 3'd1)     slow_write_active <= 1'b0;
    else if(slow_write_active && slow_is_sdram && sdram_waitrequest == 1'b0 && slow_burstcount <= 3'd1)     slow_write_active <= 1'b0;
    else if(slow_write_active && slow_is_0xff  &&                              slow_burstcount <= 3'd1)     slow_write_active <= 1'b0;
end
 
reg slow_was_read_accepted;
always @(posedge clk or negedge rst_n) begin
    if(rst_n == 1'b0)                                   slow_was_read_accepted <= 1'b0;
    else if(slow_start && mem_read)                     slow_was_read_accepted <= 1'b0; //mem_waitrequest always 1'b1
    else if(slow_read_active && ~(mem_waitrequest))     slow_was_read_accepted <= 1'b1;
end
 
reg slow_read_active;
always @(posedge clk or negedge rst_n) begin
    if(rst_n == 1'b0)                                                                               slow_read_active <= 1'b0;
    else if(slow_start && mem_read)                                                                 slow_read_active <= 1'b1;
 
    else if(slow_read_active && slow_is_vga   && vga_readdatavalid   && slow_burstcount <= 3'd1)    slow_read_active <= 1'b0;
    else if(slow_read_active && slow_is_sdram && sdram_readdatavalid && slow_burstcount <= 3'd1)    slow_read_active <= 1'b0;
    else if(slow_read_active && slow_is_0xff  &&                        slow_burstcount <= 3'd1)    slow_read_active <= 1'b0;
end
 
reg [2:0] slow_read_cnt;
always @(posedge clk or negedge rst_n) begin
    if(rst_n == 1'b0)                                                                                   slow_read_cnt <= 3'd0;
    else if(slow_start && mem_read)                                                                     slow_read_cnt <= (mem_burstcount == 3'd0)? 3'd1 : mem_burstcount;
 
    else if(slow_read_active && slow_is_vga   && vga_waitrequest == 1'b0   && slow_read_cnt > 3'd0)     slow_read_cnt <= slow_read_cnt - 3'd1;
    else if(slow_read_active && slow_is_sdram && sdram_waitrequest == 1'b0 && slow_read_cnt > 3'd0)     slow_read_cnt <= slow_read_cnt - 3'd1;
    else if(slow_read_active && slow_is_0xff  &&                              slow_read_cnt > 3'd0)     slow_read_cnt <= slow_read_cnt - 3'd1;
end
 
reg [3:0] slow_byteenable;
always @(posedge clk or negedge rst_n) begin
    if(rst_n == 1'b0)                   slow_byteenable <= 4'd0;
    else if(slow_start && mem_read)     slow_byteenable <= mem_byteenable;
end
 
reg [2:0] slow_burstcount;
always @(posedge clk or negedge rst_n) begin
    if(rst_n == 1'b0)                                                                                       slow_burstcount <= 3'd0;
    else if(slow_start)                                                                                     slow_burstcount <= mem_burstcount;
 
    else if(slow_write_active && slow_is_vga   && vga_waitrequest == 1'b0   && slow_burstcount > 3'd0)      slow_burstcount <= slow_burstcount - 3'd1;
    else if(slow_write_active && slow_is_sdram && sdram_waitrequest == 1'b0 && slow_burstcount > 3'd0)      slow_burstcount <= slow_burstcount - 3'd1;
    else if(slow_write_active && slow_is_0xff  &&                              slow_burstcount > 3'd0)      slow_burstcount <= slow_burstcount - 3'd1;
 
    else if(slow_read_active && slow_is_vga   && vga_readdatavalid   && slow_burstcount > 3'd0)             slow_burstcount <= slow_burstcount - 3'd1;
    else if(slow_read_active && slow_is_sdram && sdram_readdatavalid && slow_burstcount > 3'd0)             slow_burstcount <= slow_burstcount - 3'd1;
    else if(slow_read_active && slow_is_0xff  &&                        slow_burstcount > 3'd0)             slow_burstcount <= slow_burstcount - 3'd1;
end
 
//------------------------------------------------------------------------------ sdram
 
assign sdram_address =
    (slow_in_progress && slow_address[31:27] == 5'd0)?  { 4'd0, 1'b1, slow_address[26:0] } :
    (slow_in_progress)?                                 32'hFFFFFFFC :
    (mem_address[29:25] == 5'd0)?                       { 4'd0, 1'b1, mem_address[24:0], 2'b0 } :
                                                        32'hFFFFFFFC;
 
assign sdram_byteenable =
    (slow_in_progress && slow_read_active)?             slow_byteenable :
    (transaction_in_progress && transaction_is_read)?   transaction_byteenable :
                                                        mem_byteenable;
 
assign sdram_read =
    (slow_in_progress)?                                                         slow_read_cnt > 3'd0 && slow_is_sdram :
    (select_sdram || (transaction_in_progress && ~(transaction_select_vga)))?   mem_read && ~(transaction_in_progress && ~(transaction_is_read)) :
                                                                                1'b0;
 
assign sdram_write =
    (slow_in_progress)?                                                         slow_write_active && slow_is_sdram :
    (select_sdram || (transaction_in_progress && ~(transaction_select_vga)))?   mem_write && ~(transaction_in_progress && transaction_is_read) :
                                                                                1'b0;
 
assign sdram_writedata = mem_writedata;
 
assign sdram_burstcount =
    (slow_in_progress)?     3'd1 :
                            mem_burstcount;
 
//------------------------------------------------------------------------------ vga
 
assign vga_address =
    (slow_in_progress)?     slow_address :
                            { mem_address, 2'b0 };
 
assign vga_byteenable =
    (slow_in_progress && slow_read_active)?             slow_byteenable :
    (transaction_in_progress && transaction_is_read)?   transaction_byteenable :
                                                        mem_byteenable;
 
assign vga_read =
    (slow_in_progress)?                                                     slow_read_cnt > 3'd0 && slow_is_vga :
    (select_vga || (transaction_in_progress && transaction_select_vga))?    mem_read && ~(transaction_in_progress && ~(transaction_is_read)) :
                                                                            1'b0;
 
assign vga_write =
    (slow_in_progress)?                                                     slow_write_active && slow_is_vga :
    (select_vga || (transaction_in_progress && transaction_select_vga))?    mem_write && ~(transaction_in_progress && transaction_is_read) :
                                                                            1'b0;
 
assign vga_writedata = mem_writedata;
 
assign vga_burstcount =
    (slow_in_progress)?     3'd1 :
                            mem_burstcount;
 
//------------------------------------------------------------------------------ mem
 
assign mem_readdata =
    (slow_in_progress && slow_is_vga)?                                          vga_readdata :
    (slow_in_progress && slow_is_0xff && slow_address[3:2] == 2'h0)?            data_at_0xffffffff[31:0] :
    (slow_in_progress && slow_is_0xff && slow_address[3:2] == 2'h1)?            data_at_0xffffffff[63:32] :
    (slow_in_progress && slow_is_0xff && slow_address[3:2] == 2'h2)?            data_at_0xffffffff[95:64] :
    (slow_in_progress && slow_is_0xff && slow_address[3:2] == 2'h3)?            data_at_0xffffffff[127:96] :
    (slow_in_progress)?                                                         sdram_readdata :
    (select_vga || (transaction_in_progress && transaction_select_vga))?        vga_readdata :
                                                                                sdram_readdata;
 
assign mem_readdatavalid=
    (slow_in_progress && slow_is_vga)?                                          vga_readdatavalid :
    (slow_in_progress && slow_is_0xff)?                                         1'b1 :
    (slow_in_progress)?                                                         sdram_readdatavalid :
    (select_vga || (transaction_in_progress && transaction_select_vga))?        vga_readdatavalid :
                                                                                sdram_readdatavalid;
 
assign mem_waitrequest =
    (slow_in_progress && (slow_write_active || (slow_read_active && ~(slow_was_read_accepted))) && slow_is_vga)?            vga_waitrequest :
    (slow_in_progress && (slow_write_active || (slow_read_active && ~(slow_was_read_accepted))) && slow_is_sdram)?          sdram_waitrequest :
    (slow_in_progress && slow_read_active && slow_was_read_accepted)?                                                       1'b1 :
    (transaction_in_progress && (~(transaction_is_read) || ~(transaction_was_read_accepted)) && transaction_select_vga)?    vga_waitrequest :
    (transaction_in_progress && (~(transaction_is_read) || ~(transaction_was_read_accepted)))?                              sdram_waitrequest :
    (transaction_in_progress && transaction_is_read && transaction_was_read_accepted)?                                      1'b1 :
        (select_vga && vga_waitrequest) || (select_sdram && sdram_waitrequest) || slow_start;
 
endmodule

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[/] [ao486/] [trunk/] [rtl/] [soc/] [pc_bus/] [pc_bus.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	alfik	`/*`
2			`* Copyright (c) 2014, Aleksander Osman`
3			`* All rights reserved.`
4			`*`
5			`* Redistribution and use in source and binary forms, with or without`
6			`* modification, are permitted provided that the following conditions are met:`
7			`*`
8			`* * Redistributions of source code must retain the above copyright notice, this`
9			`* list of conditions and the following disclaimer.`
10			`*`
11			`* * Redistributions in binary form must reproduce the above copyright notice,`
12			`* this list of conditions and the following disclaimer in the documentation`
13			`* and/or other materials provided with the distribution.`
14			`*`
15			`* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"`
16			`* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE`
17			`* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE`
18			`* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE`
19			`* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL`
20			`* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR`
21			`* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER`
22			`* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,`
23			`* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE`
24			`* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.`
25			`*/`
26
27			`module pc_bus(`
28			`input clk,`
29			`input rst_n,`
30
31			`//control slave`
32			`input [1:0] ctrl_address,`
33			`input ctrl_write,`
34			`input [31:0] ctrl_writedata,`
35
36			`//memory slave`
37			`input [29:0] mem_address,`
38			`input [3:0] mem_byteenable,`
39			`input mem_read,`
40			`output [31:0] mem_readdata,`
41			`input mem_write,`
42			`input [31:0] mem_writedata,`
43			`output mem_waitrequest,`
44			`output mem_readdatavalid,`
45			`input [2:0] mem_burstcount,`
46
47			`//memory master`
48			`output [31:0] sdram_address,`
49			`output [3:0] sdram_byteenable,`
50			`output sdram_read,`
51			`input [31:0] sdram_readdata,`
52			`output sdram_write,`
53			`output [31:0] sdram_writedata,`
54			`input sdram_waitrequest,`
55			`input sdram_readdatavalid,`
56			`output [2:0] sdram_burstcount,`
57
58			`//vga master`
59			`output [31:0] vga_address,`
60			`output [3:0] vga_byteenable,`
61			`output vga_read,`
62			`input [31:0] vga_readdata,`
63			`output vga_write,`
64			`output [31:0] vga_writedata,`
65			`input vga_waitrequest,`
66			`input vga_readdatavalid,`
67			`output [2:0] vga_burstcount`
68			`);`
69
70			`//------------------------------------------------------------------------------ ctrl`
71
72			`reg [127:0] data_at_0xffffffff;`
73			`always @(posedge clk or negedge rst_n) begin`
74			`if(rst_n == 1'b0) data_at_0xffffffff <= 128'h0000000000000000000000F000FFF0EA;`
75			`else if(ctrl_write && ctrl_address == 2'd0) data_at_0xffffffff <= { data_at_0xffffffff[127:32], ctrl_writedata };`
76			`else if(ctrl_write && ctrl_address == 2'd1) data_at_0xffffffff <= { data_at_0xffffffff[127:64], ctrl_writedata, data_at_0xffffffff[31:0] };`
77			`else if(ctrl_write && ctrl_address == 2'd2) data_at_0xffffffff <= { data_at_0xffffffff[127:96], ctrl_writedata, data_at_0xffffffff[63:0] };`
78			`else if(ctrl_write && ctrl_address == 2'd3) data_at_0xffffffff <= { ctrl_writedata, data_at_0xffffffff[95:0] };`
79			`end`
80
81			`//------------------------------------------------------------------------------ transaction`
82
83			`wire select_vga = ~(slow_start) && ~(slow_in_progress) && ~(transaction_in_progress) && (mem_read \|\| mem_write) && ({ mem_address, 2'b00 } >= 32'h000A0000 && { mem_address, 2'b00 } < 32'h000C0000);`
84			`wire select_sdram = ~(slow_start) && ~(slow_in_progress) && ~(transaction_in_progress) && (mem_read \|\| mem_write) && ~(select_vga);`
85
86			`wire transaction_start = ~(slow_start) && ~(slow_in_progress) && ~(transaction_in_progress) && (mem_read \|\| (mem_write && mem_burstcount > 3'd1));`
87
88			`reg transaction_is_read;`
89			`always @(posedge clk or negedge rst_n) begin`
90			`if(rst_n == 1'b0) transaction_is_read <= 1'b0;`
91			`else if(transaction_start) transaction_is_read <= mem_read;`
92			`end`
93
94			`reg transaction_select_vga;`
95			`always @(posedge clk or negedge rst_n) begin`
96			`if(rst_n == 1'b0) transaction_select_vga <= 1'b0;`
97			`else if(transaction_start) transaction_select_vga <= select_vga;`
98			`end`
99
100			`reg transaction_was_read_accepted;`
101			`always @(posedge clk or negedge rst_n) begin`
102			`if(rst_n == 1'b0) transaction_was_read_accepted <= 1'b1;`
103			`else if(transaction_start && mem_read && mem_waitrequest) transaction_was_read_accepted <= 1'b0;`
104			`else if(transaction_start && mem_read) transaction_was_read_accepted <= 1'b1;`
105			`else if(transaction_in_progress && transaction_is_read && ~(mem_waitrequest)) transaction_was_read_accepted <= 1'b1;`
106			`end`
107
108			`reg [2:0] transaction_burstcount;`
109			`always @(posedge clk or negedge rst_n) begin`
110			`if(rst_n == 1'b0) transaction_burstcount <= 3'd0;`
111			`else if(transaction_start && mem_write && ~(mem_waitrequest)) transaction_burstcount <= mem_burstcount - 3'd1;`
112			`else if(transaction_start && (mem_read \|\| mem_write)) transaction_burstcount <= mem_burstcount;`
113			`else if(transaction_in_progress && mem_write && transaction_burstcount > 3'd0 && ~(mem_waitrequest)) transaction_burstcount <= transaction_burstcount - 3'd1;`
114			`else if(transaction_in_progress && mem_readdatavalid && transaction_burstcount > 3'd0) transaction_burstcount <= transaction_burstcount - 3'd1;`
115			`end`
116
117			`reg [3:0] transaction_byteenable;`
118			`always @(posedge clk or negedge rst_n) begin`
119			`if(rst_n == 1'b0) transaction_byteenable <= 4'd0;`
120			`else if(transaction_start && mem_read) transaction_byteenable <= mem_byteenable;`
121			`end`
122
123			`reg transaction_in_progress;`
124			`always @(posedge clk or negedge rst_n) begin`
125			`if(rst_n == 1'b0) transaction_in_progress <= 1'b0;`
126			`else if(transaction_start) transaction_in_progress <= 1'b1;`
127			`else if(transaction_in_progress && mem_write && transaction_burstcount <= 3'd1 && ~(mem_waitrequest)) transaction_in_progress <= 1'b0;`
128			`else if(transaction_in_progress && mem_readdatavalid && transaction_burstcount <= 3'd1) transaction_in_progress <= 1'b0;`
129			`end`
130
131			`//------------------------------------------------------------------------------ slow`
132
133			`wire slow_start = ~(slow_in_progress) && ~(transaction_in_progress) && (mem_read \|\| mem_write) && (`
134			`{ mem_address, 2'b00 } == 32'h0009FFF4 \|\|`
135			`{ mem_address, 2'b00 } == 32'h0009FFF8 \|\|`
136			`{ mem_address, 2'b00 } == 32'h0009FFFC \|\|`
137
138			`{ mem_address, 2'b00 } == 32'h000BFFF4 \|\|`
139			`{ mem_address, 2'b00 } == 32'h000BFFF8 \|\|`
140			`{ mem_address, 2'b00 } == 32'h000BFFFC \|\|`
141
142			`{ mem_address, 2'b00 } == 32'hFFFFFFE4 \|\|`
143			`{ mem_address, 2'b00 } == 32'hFFFFFFE8 \|\|`
144			`{ mem_address, 2'b00 } == 32'hFFFFFFEC \|\|`
145			`{ mem_address, 2'b00 } == 32'hFFFFFFF0 \|\|`
146			`{ mem_address, 2'b00 } == 32'hFFFFFFF4 \|\|`
147			`{ mem_address, 2'b00 } == 32'hFFFFFFF8 \|\|`
148			`{ mem_address, 2'b00 } == 32'hFFFFFFFC`
149			`);`
150
151			`reg slow_in_progress;`
152			`always @(posedge clk or negedge rst_n) begin`
153			`if(rst_n == 1'b0) slow_in_progress <= 1'b0;`
154			`else if(slow_start) slow_in_progress <= 1'b1;`
155
156			`else if(slow_write_active && slow_is_vga && vga_waitrequest == 1'b0 && slow_burstcount <= 3'd1) slow_in_progress <= 1'b0;`
157			`else if(slow_write_active && slow_is_sdram && sdram_waitrequest == 1'b0 && slow_burstcount <= 3'd1) slow_in_progress <= 1'b0;`
158			`else if(slow_write_active && slow_is_0xff && slow_burstcount <= 3'd1) slow_in_progress <= 1'b0;`
159
160			`else if(slow_read_active && slow_is_vga && vga_readdatavalid && slow_burstcount <= 3'd1) slow_in_progress <= 1'b0;`
161			`else if(slow_read_active && slow_is_sdram && sdram_readdatavalid && slow_burstcount <= 3'd1) slow_in_progress <= 1'b0;`
162			`else if(slow_read_active && slow_is_0xff && slow_burstcount <= 3'd1) slow_in_progress <= 1'b0;`
163			`end`
164
165			`reg [31:0] slow_address;`
166			`always @(posedge clk or negedge rst_n) begin`
167			`if(rst_n == 1'b0) slow_address <= 32'b0;`
168			`else if(slow_start) slow_address <= { mem_address, 2'b0 };`
169
170			`else if(slow_write_active && slow_is_vga && vga_waitrequest == 1'b0) slow_address <= slow_address + 32'd4;`
171			`else if(slow_write_active && slow_is_sdram && sdram_waitrequest == 1'b0) slow_address <= slow_address + 32'd4;`
172			`else if(slow_write_active && slow_is_0xff) slow_address <= slow_address + 32'd4;`
173
174			`else if(slow_read_active && slow_is_vga && vga_readdatavalid) slow_address <= slow_address + 32'd4;`
175			`else if(slow_read_active && slow_is_sdram && sdram_readdatavalid) slow_address <= slow_address + 32'd4;`
176			`else if(slow_read_active && slow_is_0xff) slow_address <= slow_address + 32'd4;`
177			`end`
178
179			`wire slow_is_vga = { slow_address[31:2], 2'b0 } >= 32'h000A0000 && { slow_address[31:2], 2'b00 } < 32'h000C0000;`
180			`wire slow_is_0xff = { slow_address[31:2], 2'b0 } >= 32'hFFFFFFF0;`
181			`wire slow_is_sdram = ~(slow_is_vga) && ~(slow_is_0xff);`
182
183			`reg slow_write_active;`
184			`always @(posedge clk or negedge rst_n) begin`
185			`if(rst_n == 1'b0) slow_write_active <= 1'b0;`
186			`else if(slow_start && mem_write) slow_write_active <= 1'b1;`
187
188			`else if(slow_write_active && slow_is_vga && vga_waitrequest == 1'b0 && slow_burstcount <= 3'd1) slow_write_active <= 1'b0;`
189			`else if(slow_write_active && slow_is_sdram && sdram_waitrequest == 1'b0 && slow_burstcount <= 3'd1) slow_write_active <= 1'b0;`
190			`else if(slow_write_active && slow_is_0xff && slow_burstcount <= 3'd1) slow_write_active <= 1'b0;`
191			`end`
192
193			`reg slow_was_read_accepted;`
194			`always @(posedge clk or negedge rst_n) begin`
195			`if(rst_n == 1'b0) slow_was_read_accepted <= 1'b0;`
196			`else if(slow_start && mem_read) slow_was_read_accepted <= 1'b0; //mem_waitrequest always 1'b1`
197			`else if(slow_read_active && ~(mem_waitrequest)) slow_was_read_accepted <= 1'b1;`
198			`end`
199
200			`reg slow_read_active;`
201			`always @(posedge clk or negedge rst_n) begin`
202			`if(rst_n == 1'b0) slow_read_active <= 1'b0;`
203			`else if(slow_start && mem_read) slow_read_active <= 1'b1;`
204
205			`else if(slow_read_active && slow_is_vga && vga_readdatavalid && slow_burstcount <= 3'd1) slow_read_active <= 1'b0;`
206			`else if(slow_read_active && slow_is_sdram && sdram_readdatavalid && slow_burstcount <= 3'd1) slow_read_active <= 1'b0;`
207			`else if(slow_read_active && slow_is_0xff && slow_burstcount <= 3'd1) slow_read_active <= 1'b0;`
208			`end`
209
210			`reg [2:0] slow_read_cnt;`
211			`always @(posedge clk or negedge rst_n) begin`
212			`if(rst_n == 1'b0) slow_read_cnt <= 3'd0;`
213			`else if(slow_start && mem_read) slow_read_cnt <= (mem_burstcount == 3'd0)? 3'd1 : mem_burstcount;`
214
215			`else if(slow_read_active && slow_is_vga && vga_waitrequest == 1'b0 && slow_read_cnt > 3'd0) slow_read_cnt <= slow_read_cnt - 3'd1;`
216			`else if(slow_read_active && slow_is_sdram && sdram_waitrequest == 1'b0 && slow_read_cnt > 3'd0) slow_read_cnt <= slow_read_cnt - 3'd1;`
217			`else if(slow_read_active && slow_is_0xff && slow_read_cnt > 3'd0) slow_read_cnt <= slow_read_cnt - 3'd1;`
218			`end`
219
220			`reg [3:0] slow_byteenable;`
221			`always @(posedge clk or negedge rst_n) begin`
222			`if(rst_n == 1'b0) slow_byteenable <= 4'd0;`
223			`else if(slow_start && mem_read) slow_byteenable <= mem_byteenable;`
224			`end`
225
226			`reg [2:0] slow_burstcount;`
227			`always @(posedge clk or negedge rst_n) begin`
228			`if(rst_n == 1'b0) slow_burstcount <= 3'd0;`
229			`else if(slow_start) slow_burstcount <= mem_burstcount;`
230
231			`else if(slow_write_active && slow_is_vga && vga_waitrequest == 1'b0 && slow_burstcount > 3'd0) slow_burstcount <= slow_burstcount - 3'd1;`
232			`else if(slow_write_active && slow_is_sdram && sdram_waitrequest == 1'b0 && slow_burstcount > 3'd0) slow_burstcount <= slow_burstcount - 3'd1;`
233			`else if(slow_write_active && slow_is_0xff && slow_burstcount > 3'd0) slow_burstcount <= slow_burstcount - 3'd1;`
234
235			`else if(slow_read_active && slow_is_vga && vga_readdatavalid && slow_burstcount > 3'd0) slow_burstcount <= slow_burstcount - 3'd1;`
236			`else if(slow_read_active && slow_is_sdram && sdram_readdatavalid && slow_burstcount > 3'd0) slow_burstcount <= slow_burstcount - 3'd1;`
237			`else if(slow_read_active && slow_is_0xff && slow_burstcount > 3'd0) slow_burstcount <= slow_burstcount - 3'd1;`
238			`end`
239
240			`//------------------------------------------------------------------------------ sdram`
241
242			`assign sdram_address =`
243			`(slow_in_progress && slow_address[31:27] == 5'd0)? { 4'd0, 1'b1, slow_address[26:0] } :`
244			`(slow_in_progress)? 32'hFFFFFFFC :`
245			`(mem_address[29:25] == 5'd0)? { 4'd0, 1'b1, mem_address[24:0], 2'b0 } :`
246			`32'hFFFFFFFC;`
247
248			`assign sdram_byteenable =`
249			`(slow_in_progress && slow_read_active)? slow_byteenable :`
250			`(transaction_in_progress && transaction_is_read)? transaction_byteenable :`
251			`mem_byteenable;`
252
253			`assign sdram_read =`
254			`(slow_in_progress)? slow_read_cnt > 3'd0 && slow_is_sdram :`
255			`(select_sdram \|\| (transaction_in_progress && ~(transaction_select_vga)))? mem_read && ~(transaction_in_progress && ~(transaction_is_read)) :`
256			`1'b0;`
257
258			`assign sdram_write =`
259			`(slow_in_progress)? slow_write_active && slow_is_sdram :`
260			`(select_sdram \|\| (transaction_in_progress && ~(transaction_select_vga)))? mem_write && ~(transaction_in_progress && transaction_is_read) :`
261			`1'b0;`
262
263			`assign sdram_writedata = mem_writedata;`
264
265			`assign sdram_burstcount =`
266			`(slow_in_progress)? 3'd1 :`
267			`mem_burstcount;`
268
269			`//------------------------------------------------------------------------------ vga`
270
271			`assign vga_address =`
272			`(slow_in_progress)? slow_address :`
273			`{ mem_address, 2'b0 };`
274
275			`assign vga_byteenable =`
276			`(slow_in_progress && slow_read_active)? slow_byteenable :`
277			`(transaction_in_progress && transaction_is_read)? transaction_byteenable :`
278			`mem_byteenable;`
279
280			`assign vga_read =`
281			`(slow_in_progress)? slow_read_cnt > 3'd0 && slow_is_vga :`
282			`(select_vga \|\| (transaction_in_progress && transaction_select_vga))? mem_read && ~(transaction_in_progress && ~(transaction_is_read)) :`
283			`1'b0;`
284
285			`assign vga_write =`
286			`(slow_in_progress)? slow_write_active && slow_is_vga :`
287			`(select_vga \|\| (transaction_in_progress && transaction_select_vga))? mem_write && ~(transaction_in_progress && transaction_is_read) :`
288			`1'b0;`
289
290			`assign vga_writedata = mem_writedata;`
291
292			`assign vga_burstcount =`
293			`(slow_in_progress)? 3'd1 :`
294			`mem_burstcount;`
295
296			`//------------------------------------------------------------------------------ mem`
297
298			`assign mem_readdata =`
299			`(slow_in_progress && slow_is_vga)? vga_readdata :`
300			`(slow_in_progress && slow_is_0xff && slow_address[3:2] == 2'h0)? data_at_0xffffffff[31:0] :`
301			`(slow_in_progress && slow_is_0xff && slow_address[3:2] == 2'h1)? data_at_0xffffffff[63:32] :`
302			`(slow_in_progress && slow_is_0xff && slow_address[3:2] == 2'h2)? data_at_0xffffffff[95:64] :`
303			`(slow_in_progress && slow_is_0xff && slow_address[3:2] == 2'h3)? data_at_0xffffffff[127:96] :`
304			`(slow_in_progress)? sdram_readdata :`
305			`(select_vga \|\| (transaction_in_progress && transaction_select_vga))? vga_readdata :`
306			`sdram_readdata;`
307
308			`assign mem_readdatavalid=`
309			`(slow_in_progress && slow_is_vga)? vga_readdatavalid :`
310			`(slow_in_progress && slow_is_0xff)? 1'b1 :`
311			`(slow_in_progress)? sdram_readdatavalid :`
312			`(select_vga \|\| (transaction_in_progress && transaction_select_vga))? vga_readdatavalid :`
313			`sdram_readdatavalid;`
314
315			`assign mem_waitrequest =`
316			`(slow_in_progress && (slow_write_active \|\| (slow_read_active && ~(slow_was_read_accepted))) && slow_is_vga)? vga_waitrequest :`
317			`(slow_in_progress && (slow_write_active \|\| (slow_read_active && ~(slow_was_read_accepted))) && slow_is_sdram)? sdram_waitrequest :`
318			`(slow_in_progress && slow_read_active && slow_was_read_accepted)? 1'b1 :`
319			`(transaction_in_progress && (~(transaction_is_read) \|\| ~(transaction_was_read_accepted)) && transaction_select_vga)? vga_waitrequest :`
320			`(transaction_in_progress && (~(transaction_is_read) \|\| ~(transaction_was_read_accepted)))? sdram_waitrequest :`
321			`(transaction_in_progress && transaction_is_read && transaction_was_read_accepted)? 1'b1 :`
322			`(select_vga && vga_waitrequest) \|\| (select_sdram && sdram_waitrequest) \|\| slow_start;`
323
324			`endmodule`