Subversion Repositories ao486

# TCL File Generated by Component Editor 13.0sp1

# Mon Nov 04 20:33:38 CET 2013

# DO NOT MODIFY

# 

# pc_bus "pc_bus" v1.0

#  2013.11.04.20:33:37

# 

# 

# 

# request TCL package from ACDS 13.1

# 

package require -exact qsys 13.1

# 

# module pc_bus

# 

set_module_property DESCRIPTION ""

set_module_property NAME pc_bus

set_module_property VERSION 1.0

set_module_property INTERNAL false

set_module_property OPAQUE_ADDRESS_MAP true

set_module_property GROUP ao486

set_module_property AUTHOR ""

set_module_property DISPLAY_NAME pc_bus

set_module_property INSTANTIATE_IN_SYSTEM_MODULE true

set_module_property EDITABLE true

set_module_property ANALYZE_HDL AUTO

set_module_property REPORT_TO_TALKBACK false

set_module_property ALLOW_GREYBOX_GENERATION false

# 

# file sets

# 

add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""

set_fileset_property QUARTUS_SYNTH TOP_LEVEL pc_bus

set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false

add_fileset_file pc_bus.v VERILOG PATH pc_bus.v TOP_LEVEL_FILE

# 

# parameters

# 

# 

# display items

# 

# 

# connection point clock

# 

add_interface clock clock end

set_interface_property clock clockRate 0

set_interface_property clock ENABLED true

set_interface_property clock EXPORT_OF ""

set_interface_property clock PORT_NAME_MAP ""

set_interface_property clock SVD_ADDRESS_GROUP ""

add_interface_port clock clk clk Input 1

# 

# connection point ctrl

# 

add_interface ctrl avalon end

set_interface_property ctrl addressUnits WORDS

set_interface_property ctrl associatedClock clock

set_interface_property ctrl associatedReset reset_sink

set_interface_property ctrl bitsPerSymbol 8

set_interface_property ctrl burstOnBurstBoundariesOnly false

set_interface_property ctrl burstcountUnits WORDS

set_interface_property ctrl explicitAddressSpan 0

set_interface_property ctrl holdTime 0

set_interface_property ctrl linewrapBursts false

set_interface_property ctrl maximumPendingReadTransactions 0

set_interface_property ctrl readLatency 0

set_interface_property ctrl readWaitTime 1

set_interface_property ctrl setupTime 0

set_interface_property ctrl timingUnits Cycles

set_interface_property ctrl writeWaitTime 0

set_interface_property ctrl ENABLED true

set_interface_property ctrl EXPORT_OF ""

set_interface_property ctrl PORT_NAME_MAP ""

set_interface_property ctrl SVD_ADDRESS_GROUP ""

add_interface_port ctrl ctrl_address address Input 2

add_interface_port ctrl ctrl_write write Input 1

add_interface_port ctrl ctrl_writedata writedata Input 32

set_interface_assignment ctrl embeddedsw.configuration.isFlash 0

set_interface_assignment ctrl embeddedsw.configuration.isMemoryDevice 0

set_interface_assignment ctrl embeddedsw.configuration.isNonVolatileStorage 0

set_interface_assignment ctrl embeddedsw.configuration.isPrintableDevice 0

# 

# connection point mem

# 

add_interface mem avalon end

set_interface_property mem addressUnits WORDS

set_interface_property mem associatedClock clock

set_interface_property mem associatedReset reset_sink

set_interface_property mem bitsPerSymbol 8

set_interface_property mem burstOnBurstBoundariesOnly false

set_interface_property mem burstcountUnits WORDS

set_interface_property mem explicitAddressSpan 0

set_interface_property mem holdTime 0

set_interface_property mem linewrapBursts false

set_interface_property mem maximumPendingReadTransactions 1

set_interface_property mem readLatency 0

set_interface_property mem readWaitTime 1

set_interface_property mem setupTime 0

set_interface_property mem timingUnits Cycles

set_interface_property mem writeWaitTime 0

set_interface_property mem ENABLED true

set_interface_property mem EXPORT_OF ""

set_interface_property mem PORT_NAME_MAP ""

set_interface_property mem SVD_ADDRESS_GROUP ""

add_interface_port mem mem_address address Input 30

add_interface_port mem mem_byteenable byteenable Input 4

add_interface_port mem mem_read read Input 1

add_interface_port mem mem_readdata readdata Output 32

add_interface_port mem mem_write write Input 1

add_interface_port mem mem_writedata writedata Input 32

add_interface_port mem mem_waitrequest waitrequest Output 1

add_interface_port mem mem_readdatavalid readdatavalid Output 1

add_interface_port mem mem_burstcount burstcount Input 3

set_interface_assignment mem embeddedsw.configuration.isFlash 0

set_interface_assignment mem embeddedsw.configuration.isMemoryDevice 0

set_interface_assignment mem embeddedsw.configuration.isNonVolatileStorage 0

set_interface_assignment mem embeddedsw.configuration.isPrintableDevice 0

# 

# connection point reset_sink

# 

add_interface reset_sink reset end

set_interface_property reset_sink associatedClock clock

set_interface_property reset_sink synchronousEdges DEASSERT

set_interface_property reset_sink ENABLED true

set_interface_property reset_sink EXPORT_OF ""

set_interface_property reset_sink PORT_NAME_MAP ""

set_interface_property reset_sink SVD_ADDRESS_GROUP ""

add_interface_port reset_sink rst_n reset_n Input 1

# 

# connection point avalon_vga_master

# 

add_interface avalon_vga_master avalon start

set_interface_property avalon_vga_master addressUnits SYMBOLS

set_interface_property avalon_vga_master associatedClock clock

set_interface_property avalon_vga_master associatedReset reset_sink

set_interface_property avalon_vga_master bitsPerSymbol 8

set_interface_property avalon_vga_master burstOnBurstBoundariesOnly false

set_interface_property avalon_vga_master burstcountUnits WORDS

set_interface_property avalon_vga_master doStreamReads false

set_interface_property avalon_vga_master doStreamWrites false

set_interface_property avalon_vga_master holdTime 0

set_interface_property avalon_vga_master linewrapBursts false

set_interface_property avalon_vga_master maximumPendingReadTransactions 0

set_interface_property avalon_vga_master readLatency 0

set_interface_property avalon_vga_master readWaitTime 1

set_interface_property avalon_vga_master setupTime 0

set_interface_property avalon_vga_master timingUnits Cycles

set_interface_property avalon_vga_master writeWaitTime 0

set_interface_property avalon_vga_master ENABLED true

set_interface_property avalon_vga_master EXPORT_OF ""

set_interface_property avalon_vga_master PORT_NAME_MAP ""

set_interface_property avalon_vga_master SVD_ADDRESS_GROUP ""

add_interface_port avalon_vga_master vga_address address Output 32

add_interface_port avalon_vga_master vga_byteenable byteenable Output 4

add_interface_port avalon_vga_master vga_read read Output 1

add_interface_port avalon_vga_master vga_readdata readdata Input 32

add_interface_port avalon_vga_master vga_write write Output 1

add_interface_port avalon_vga_master vga_writedata writedata Output 32

add_interface_port avalon_vga_master vga_waitrequest waitrequest Input 1

add_interface_port avalon_vga_master vga_readdatavalid readdatavalid Input 1

add_interface_port avalon_vga_master vga_burstcount burstcount Output 3

# 

# connection point avalon_sdram_master

# 

add_interface avalon_sdram_master avalon start

set_interface_property avalon_sdram_master addressUnits SYMBOLS

set_interface_property avalon_sdram_master associatedClock clock

set_interface_property avalon_sdram_master associatedReset reset_sink

set_interface_property avalon_sdram_master bitsPerSymbol 8

set_interface_property avalon_sdram_master burstOnBurstBoundariesOnly false

set_interface_property avalon_sdram_master burstcountUnits WORDS

set_interface_property avalon_sdram_master doStreamReads false

set_interface_property avalon_sdram_master doStreamWrites false

set_interface_property avalon_sdram_master holdTime 0

set_interface_property avalon_sdram_master linewrapBursts false

set_interface_property avalon_sdram_master maximumPendingReadTransactions 0

set_interface_property avalon_sdram_master readLatency 0

set_interface_property avalon_sdram_master readWaitTime 1

set_interface_property avalon_sdram_master setupTime 0

set_interface_property avalon_sdram_master timingUnits Cycles

set_interface_property avalon_sdram_master writeWaitTime 0

set_interface_property avalon_sdram_master ENABLED true

set_interface_property avalon_sdram_master EXPORT_OF ""

set_interface_property avalon_sdram_master PORT_NAME_MAP ""

set_interface_property avalon_sdram_master SVD_ADDRESS_GROUP ""

add_interface_port avalon_sdram_master sdram_address address Output 32

add_interface_port avalon_sdram_master sdram_byteenable byteenable Output 4

add_interface_port avalon_sdram_master sdram_read read Output 1

add_interface_port avalon_sdram_master sdram_readdata readdata Input 32

add_interface_port avalon_sdram_master sdram_write write Output 1

add_interface_port avalon_sdram_master sdram_writedata writedata Output 32

add_interface_port avalon_sdram_master sdram_waitrequest waitrequest Input 1

add_interface_port avalon_sdram_master sdram_readdatavalid readdatavalid Input 1

add_interface_port avalon_sdram_master sdram_burstcount burstcount Output 3