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alfik |
# TCL File Generated by Component Editor 13.1
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# Fri Jan 17 22:12:28 CET 2014
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# DO NOT MODIFY
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#
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# pic "pic" v1.0
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# 2014.01.17.22:12:28
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#
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#
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#
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# request TCL package from ACDS 13.1
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#
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package require -exact qsys 13.1
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#
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# module pic
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#
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set_module_property DESCRIPTION ""
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set_module_property NAME pic
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set_module_property VERSION 1.0
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set_module_property INTERNAL false
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set_module_property OPAQUE_ADDRESS_MAP true
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set_module_property GROUP ao486
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set_module_property AUTHOR ""
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set_module_property DISPLAY_NAME pic
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set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
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set_module_property EDITABLE true
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set_module_property ANALYZE_HDL AUTO
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set_module_property REPORT_TO_TALKBACK false
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set_module_property ALLOW_GREYBOX_GENERATION false
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#
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# file sets
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#
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add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
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set_fileset_property QUARTUS_SYNTH TOP_LEVEL pic
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set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
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add_fileset_file pic.v VERILOG PATH pic.v TOP_LEVEL_FILE
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#
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# parameters
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#
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#
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# display items
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#
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#
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# connection point clock
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#
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add_interface clock clock end
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set_interface_property clock clockRate 0
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set_interface_property clock ENABLED true
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set_interface_property clock EXPORT_OF ""
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set_interface_property clock PORT_NAME_MAP ""
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set_interface_property clock CMSIS_SVD_VARIABLES ""
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set_interface_property clock SVD_ADDRESS_GROUP ""
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add_interface_port clock clk clk Input 1
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#
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# connection point master
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#
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add_interface master avalon end
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set_interface_property master addressUnits WORDS
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set_interface_property master associatedClock clock
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set_interface_property master associatedReset reset_sink
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set_interface_property master bitsPerSymbol 8
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set_interface_property master burstOnBurstBoundariesOnly false
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set_interface_property master burstcountUnits WORDS
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set_interface_property master explicitAddressSpan 0
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set_interface_property master holdTime 0
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set_interface_property master linewrapBursts false
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set_interface_property master maximumPendingReadTransactions 0
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set_interface_property master readLatency 0
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set_interface_property master readWaitTime 1
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set_interface_property master setupTime 0
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set_interface_property master timingUnits Cycles
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set_interface_property master writeWaitTime 0
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set_interface_property master ENABLED true
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set_interface_property master EXPORT_OF ""
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set_interface_property master PORT_NAME_MAP ""
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set_interface_property master CMSIS_SVD_VARIABLES ""
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set_interface_property master SVD_ADDRESS_GROUP ""
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add_interface_port master master_address address Input 1
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add_interface_port master master_read read Input 1
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add_interface_port master master_readdata readdata Output 8
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add_interface_port master master_write write Input 1
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add_interface_port master master_writedata writedata Input 8
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set_interface_assignment master embeddedsw.configuration.isFlash 0
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set_interface_assignment master embeddedsw.configuration.isMemoryDevice 0
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set_interface_assignment master embeddedsw.configuration.isNonVolatileStorage 0
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set_interface_assignment master embeddedsw.configuration.isPrintableDevice 0
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#
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# connection point slave
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#
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add_interface slave avalon end
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set_interface_property slave addressUnits WORDS
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set_interface_property slave associatedClock clock
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set_interface_property slave associatedReset reset_sink
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set_interface_property slave bitsPerSymbol 8
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set_interface_property slave burstOnBurstBoundariesOnly false
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set_interface_property slave burstcountUnits WORDS
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set_interface_property slave explicitAddressSpan 0
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set_interface_property slave holdTime 0
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set_interface_property slave linewrapBursts false
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set_interface_property slave maximumPendingReadTransactions 0
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set_interface_property slave readLatency 0
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set_interface_property slave readWaitTime 1
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set_interface_property slave setupTime 0
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set_interface_property slave timingUnits Cycles
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set_interface_property slave writeWaitTime 0
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set_interface_property slave ENABLED true
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set_interface_property slave EXPORT_OF ""
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set_interface_property slave PORT_NAME_MAP ""
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set_interface_property slave CMSIS_SVD_VARIABLES ""
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set_interface_property slave SVD_ADDRESS_GROUP ""
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add_interface_port slave slave_address address Input 1
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add_interface_port slave slave_read read Input 1
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add_interface_port slave slave_readdata readdata Output 8
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add_interface_port slave slave_write write Input 1
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add_interface_port slave slave_writedata writedata Input 8
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set_interface_assignment slave embeddedsw.configuration.isFlash 0
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set_interface_assignment slave embeddedsw.configuration.isMemoryDevice 0
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set_interface_assignment slave embeddedsw.configuration.isNonVolatileStorage 0
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set_interface_assignment slave embeddedsw.configuration.isPrintableDevice 0
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#
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# connection point reset_sink
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#
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add_interface reset_sink reset end
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set_interface_property reset_sink associatedClock clock
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set_interface_property reset_sink synchronousEdges DEASSERT
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set_interface_property reset_sink ENABLED true
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set_interface_property reset_sink EXPORT_OF ""
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set_interface_property reset_sink PORT_NAME_MAP ""
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set_interface_property reset_sink CMSIS_SVD_VARIABLES ""
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set_interface_property reset_sink SVD_ADDRESS_GROUP ""
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add_interface_port reset_sink rst_n reset_n Input 1
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#
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# connection point conduit_interrupt
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#
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add_interface conduit_interrupt conduit end
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set_interface_property conduit_interrupt associatedClock clock
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set_interface_property conduit_interrupt associatedReset reset_sink
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set_interface_property conduit_interrupt ENABLED true
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set_interface_property conduit_interrupt EXPORT_OF ""
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set_interface_property conduit_interrupt PORT_NAME_MAP ""
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set_interface_property conduit_interrupt CMSIS_SVD_VARIABLES ""
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set_interface_property conduit_interrupt SVD_ADDRESS_GROUP ""
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add_interface_port conduit_interrupt interrupt_do export Output 1
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add_interface_port conduit_interrupt interrupt_vector export Output 8
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add_interface_port conduit_interrupt interrupt_done export Input 1
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#
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# connection point interrupt_receiver
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#
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add_interface interrupt_receiver interrupt start
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set_interface_property interrupt_receiver associatedAddressablePoint ""
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set_interface_property interrupt_receiver associatedClock clock
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set_interface_property interrupt_receiver associatedReset reset_sink
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set_interface_property interrupt_receiver irqScheme INDIVIDUAL_REQUESTS
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set_interface_property interrupt_receiver ENABLED true
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set_interface_property interrupt_receiver EXPORT_OF ""
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set_interface_property interrupt_receiver PORT_NAME_MAP ""
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set_interface_property interrupt_receiver CMSIS_SVD_VARIABLES ""
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set_interface_property interrupt_receiver SVD_ADDRESS_GROUP ""
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add_interface_port interrupt_receiver interrupt_input irq Input 16
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