Subversion Repositories ao486

# TCL File Generated by Component Editor 14.0

# Mon Aug 18 22:49:43 CEST 2014

# DO NOT MODIFY

# 

# pic "pic" v1.0

#  2014.08.18.22:49:43

# 

# 

# 

# request TCL package from ACDS 14.0

# 

package require -exact qsys 14.0

# 

# module pic

# 

set_module_property DESCRIPTION ""

set_module_property NAME pic

set_module_property VERSION 1.0

set_module_property INTERNAL false

set_module_property OPAQUE_ADDRESS_MAP true

set_module_property GROUP ao486

set_module_property AUTHOR ""

set_module_property DISPLAY_NAME pic

set_module_property INSTANTIATE_IN_SYSTEM_MODULE true

set_module_property EDITABLE true

set_module_property REPORT_TO_TALKBACK false

set_module_property ALLOW_GREYBOX_GENERATION false

set_module_property REPORT_HIERARCHY false

# 

# file sets

# 

add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""

set_fileset_property QUARTUS_SYNTH TOP_LEVEL pic

set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false

set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false

add_fileset_file pic.v VERILOG PATH pic.v TOP_LEVEL_FILE

# 

# parameters

# 

# 

# display items

# 

# 

# connection point clock

# 

add_interface clock clock end

set_interface_property clock clockRate 0

set_interface_property clock ENABLED true

set_interface_property clock EXPORT_OF ""

set_interface_property clock PORT_NAME_MAP ""

set_interface_property clock CMSIS_SVD_VARIABLES ""

set_interface_property clock SVD_ADDRESS_GROUP ""

add_interface_port clock clk clk Input 1

# 

# connection point master

# 

add_interface master avalon end

set_interface_property master addressUnits WORDS

set_interface_property master associatedClock clock

set_interface_property master associatedReset reset_sink

set_interface_property master bitsPerSymbol 8

set_interface_property master burstOnBurstBoundariesOnly false

set_interface_property master burstcountUnits WORDS

set_interface_property master explicitAddressSpan 0

set_interface_property master holdTime 0

set_interface_property master linewrapBursts false

set_interface_property master maximumPendingReadTransactions 0

set_interface_property master maximumPendingWriteTransactions 0

set_interface_property master readLatency 0

set_interface_property master readWaitTime 1

set_interface_property master setupTime 0

set_interface_property master timingUnits Cycles

set_interface_property master writeWaitTime 0

set_interface_property master ENABLED true

set_interface_property master EXPORT_OF ""

set_interface_property master PORT_NAME_MAP ""

set_interface_property master CMSIS_SVD_VARIABLES ""

set_interface_property master SVD_ADDRESS_GROUP ""

add_interface_port master master_address address Input 1

add_interface_port master master_read read Input 1

add_interface_port master master_readdata readdata Output 8

add_interface_port master master_write write Input 1

add_interface_port master master_writedata writedata Input 8

set_interface_assignment master embeddedsw.configuration.isFlash 0

set_interface_assignment master embeddedsw.configuration.isMemoryDevice 0

set_interface_assignment master embeddedsw.configuration.isNonVolatileStorage 0

set_interface_assignment master embeddedsw.configuration.isPrintableDevice 0

# 

# connection point slave

# 

add_interface slave avalon end

set_interface_property slave addressUnits WORDS

set_interface_property slave associatedClock clock

set_interface_property slave associatedReset reset_sink

set_interface_property slave bitsPerSymbol 8

set_interface_property slave burstOnBurstBoundariesOnly false

set_interface_property slave burstcountUnits WORDS

set_interface_property slave explicitAddressSpan 0

set_interface_property slave holdTime 0

set_interface_property slave linewrapBursts false

set_interface_property slave maximumPendingReadTransactions 0

set_interface_property slave maximumPendingWriteTransactions 0

set_interface_property slave readLatency 0

set_interface_property slave readWaitTime 1

set_interface_property slave setupTime 0

set_interface_property slave timingUnits Cycles

set_interface_property slave writeWaitTime 0

set_interface_property slave ENABLED true

set_interface_property slave EXPORT_OF ""

set_interface_property slave PORT_NAME_MAP ""

set_interface_property slave CMSIS_SVD_VARIABLES ""

set_interface_property slave SVD_ADDRESS_GROUP ""

add_interface_port slave slave_address address Input 1

add_interface_port slave slave_read read Input 1

add_interface_port slave slave_readdata readdata Output 8

add_interface_port slave slave_write write Input 1

add_interface_port slave slave_writedata writedata Input 8

set_interface_assignment slave embeddedsw.configuration.isFlash 0

set_interface_assignment slave embeddedsw.configuration.isMemoryDevice 0

set_interface_assignment slave embeddedsw.configuration.isNonVolatileStorage 0

set_interface_assignment slave embeddedsw.configuration.isPrintableDevice 0

# 

# connection point reset_sink

# 

add_interface reset_sink reset end

set_interface_property reset_sink associatedClock clock

set_interface_property reset_sink synchronousEdges DEASSERT

set_interface_property reset_sink ENABLED true

set_interface_property reset_sink EXPORT_OF ""

set_interface_property reset_sink PORT_NAME_MAP ""

set_interface_property reset_sink CMSIS_SVD_VARIABLES ""

set_interface_property reset_sink SVD_ADDRESS_GROUP ""

add_interface_port reset_sink rst_n reset_n Input 1

# 

# connection point conduit_interrupt

# 

add_interface conduit_interrupt conduit end

set_interface_property conduit_interrupt associatedClock clock

set_interface_property conduit_interrupt associatedReset ""

set_interface_property conduit_interrupt ENABLED true

set_interface_property conduit_interrupt EXPORT_OF ""

set_interface_property conduit_interrupt PORT_NAME_MAP ""

set_interface_property conduit_interrupt CMSIS_SVD_VARIABLES ""

set_interface_property conduit_interrupt SVD_ADDRESS_GROUP ""

add_interface_port conduit_interrupt interrupt_vector interrupt_vector Output 8

add_interface_port conduit_interrupt interrupt_done interrupt_done Input 1

add_interface_port conduit_interrupt interrupt_do interrupt_do Output 1

# 

# connection point interrupt_receiver

# 

add_interface interrupt_receiver interrupt start

set_interface_property interrupt_receiver associatedAddressablePoint ""

set_interface_property interrupt_receiver associatedClock clock

set_interface_property interrupt_receiver associatedReset reset_sink

set_interface_property interrupt_receiver irqScheme INDIVIDUAL_REQUESTS

set_interface_property interrupt_receiver ENABLED true

set_interface_property interrupt_receiver EXPORT_OF ""

set_interface_property interrupt_receiver PORT_NAME_MAP ""

set_interface_property interrupt_receiver CMSIS_SVD_VARIABLES ""

set_interface_property interrupt_receiver SVD_ADDRESS_GROUP ""

add_interface_port interrupt_receiver interrupt_input irq Input 16