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alfik |
/*
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* Copyright (c) 2014, Aleksander Osman
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* * Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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module pit_counter(
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input clk,
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input rst_n,
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input clock,
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input gate,
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output reg out,
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input [7:0] data_in,
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input set_control_mode,
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input latch_count,
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input latch_status,
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input write,
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input read,
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output [7:0] data_out
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);
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//------------------------------------------------------------------------------
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reg [2:0] mode;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) mode <= 3'd2;
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else if(set_control_mode) mode <= data_in[3:1];
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end
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reg bcd;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) bcd <= 1'd0;
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else if(set_control_mode) bcd <= data_in[0];
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end
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reg [1:0] rw_mode;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) rw_mode <= 2'd1;
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else if(set_control_mode) rw_mode <= data_in[5:4];
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end
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//------------------------------------------------------------------------------
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reg [7:0] counter_l;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) counter_l <= 8'd0;
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else if(set_control_mode) counter_l <= 8'd0;
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else if(write && rw_mode == 2'd3 && msb_write == 1'b0) counter_l <= data_in;
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else if(write && rw_mode == 2'd1) counter_l <= data_in;
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end
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reg [7:0] counter_m;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) counter_m <= 8'd0;
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else if(set_control_mode) counter_m <= 8'd0;
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else if(write && rw_mode == 2'd3 && msb_write == 1'b1) counter_m <= data_in;
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else if(write && rw_mode == 2'd2) counter_m <= data_in;
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end
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reg [7:0] output_l;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) output_l <= 8'd0;
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else if(latch_count && ~(output_latched)) output_l <= counter[7:0];
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else if(~(output_latched)) output_l <= counter[7:0];
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end
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reg [7:0] output_m;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) output_m <= 8'd0;
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else if(latch_count && ~(output_latched)) output_m <= counter[15:8];
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else if(~(output_latched)) output_m <= counter[15:8];
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end
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reg output_latched;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) output_latched <= 1'b0;
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else if(set_control_mode) output_latched <= 1'b0;
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else if(latch_count) output_latched <= 1'b1;
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else if(read && (rw_mode != 2'd3 || msb_read)) output_latched <= 1'b0;
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end
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reg null_counter;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) null_counter <= 1'b0;
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else if(set_control_mode) null_counter <= 1'b1;
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else if(write && (rw_mode != 2'd3 || msb_write)) null_counter <= 1'b1;
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else if(load) null_counter <= 1'b0;
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end
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reg msb_write;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) msb_write <= 1'b0;
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else if(set_control_mode) msb_write <= 1'b0;
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else if(write && rw_mode == 2'd3) msb_write <= ~(msb_write);
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end
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reg msb_read;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) msb_read <= 1'b0;
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else if(set_control_mode) msb_read <= 1'b0;
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else if(read && rw_mode == 2'd3) msb_read <= ~(msb_read);
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end
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reg [7:0] status;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) status <= 8'd0;
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else if(latch_status && ~(status_latched)) status <= { out, null_counter, rw_mode, mode, bcd };
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end
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reg status_latched;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) status_latched <= 1'b0;
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else if(set_control_mode) status_latched <= 1'b0;
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else if(latch_status) status_latched <= 1'b1;
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else if(read) status_latched <= 1'b0;
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end
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assign data_out =
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(status_latched)? status :
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(rw_mode == 2'd3 && msb_read == 1'b0)? output_l :
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(rw_mode == 2'd3 && msb_read == 1'b1)? output_m :
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(rw_mode == 2'd1)? output_l :
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output_m;
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//------------------------------------------------------------------------------
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reg clock_last;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) clock_last <= 1'b0;
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else clock_last <= clock;
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end
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reg clock_pulse;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) clock_pulse <= 1'b0;
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else if(clock_last == 1'b1 && clock == 1'b0) clock_pulse <= 1'b1;
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else clock_pulse <= 1'b0;
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end
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reg gate_last;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) gate_last <= 1'b1;
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else gate_last <= gate;
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end
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reg gate_sampled;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) gate_sampled <= 1'b0;
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else if(clock_last == 1'b0 && clock == 1'b1) gate_sampled <= gate;
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end
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reg trigger;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) trigger <= 1'b0;
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else if(gate_last == 1'b0 && gate == 1'b1) trigger <= 1'b1;
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else if(clock_last == 1'b0 && clock == 1'b1) trigger <= 1'b0;
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end
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reg trigger_sampled;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) trigger_sampled <= 1'b0;
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else if(clock_last == 1'b0 && clock == 1'b1) trigger_sampled <= trigger;
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end
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//------------------------------------------------------------------------------
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) out <= 1'b1;
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else if(set_control_mode && data_in[3:1] == 3'd0) out <= 1'b0;
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else if(set_control_mode && data_in[3:1] == 3'd1) out <= 1'b1;
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else if(set_control_mode && data_in[2:1] == 2'd2) out <= 1'b1;
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else if(set_control_mode && data_in[2:1] == 2'd3) out <= 1'b1;
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else if(set_control_mode && data_in[3:1] == 3'd4) out <= 1'b1;
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else if(set_control_mode && data_in[3:1] == 3'd5) out <= 1'b1;
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else if(mode == 3'd0 && write && rw_mode == 2'd3 && msb_write == 1'b0) out <= 1'b0;
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else if(mode == 3'd0 && written) out <= 1'b0;
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else if(mode == 3'd0 && counter == 16'd1 && enable) out <= 1'b1;
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else if(mode == 3'd1 && load) out <= 1'b0;
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else if(mode == 3'd1 && counter == 16'd1 && enable) out <= 1'b1;
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else if(mode[1:0] == 2'd2 && gate == 1'b0) out <= 1'b1;
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else if(mode[1:0] == 2'd2 && counter == 16'd2 && enable) out <= 1'b0;
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else if(mode[1:0] == 2'd2 && load) out <= 1'b1;
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else if(mode[1:0] == 2'd3 && gate == 1'b0) out <= 1'b1;
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else if(mode[1:0] == 2'd3 && load && counter == 16'd2 && out && ~(counter_l[0])) out <= 1'b0;
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else if(mode[1:0] == 2'd3 && load && counter == 16'd0 && out && counter_l[0]) out <= 1'b0;
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else if(mode[1:0] == 2'd3 && load) out <= 1'b1;
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else if(mode == 3'd4 && load) out <= 1'b1;
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else if(mode == 3'd4 && counter == 16'd2 && enable) out <= 1'b0;
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else if(mode == 3'd4 && counter == 16'd1 && enable) out <= 1'b1;
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else if(mode == 3'd5 && counter == 16'd2 && enable) out <= 1'b0;
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else if(mode == 3'd5 && counter == 16'd1 && enable) out <= 1'b1;
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end
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//------------------------------------------------------------------------------
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reg written;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) written <= 1'b0;
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else if(set_control_mode) written <= 1'b0;
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else if(write && rw_mode != 2'd3) written <= 1'b1;
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else if(write && rw_mode == 2'd3 && msb_write == 1'b1) written <= 1'b1;
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else if(load) written <= 1'b0;
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end
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reg loaded;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) loaded <= 1'b0;
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else if(set_control_mode) loaded <= 1'b0;
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else if(load) loaded <= 1'b1;
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end
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wire load = clock_pulse && (
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(mode == 3'd0 && written) ||
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(mode == 3'd1 && written && trigger_sampled) ||
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(mode[1:0] == 2'd2 && (written || trigger_sampled || (loaded && gate_sampled && counter == 16'd1))) ||
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(mode[1:0] == 2'd3 && (written || trigger_sampled || (loaded && gate_sampled && ((counter == 16'd2 && (~(counter_l[0]) || ~(out))) || (counter == 16'd0 && counter_l[0] && out))))) ||
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(mode == 3'd4 && written) ||
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(mode == 3'd5 && (written || loaded) && trigger_sampled)
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);
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wire load_even = load && mode[1:0] == 2'd3;
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wire enable = ~(load) && loaded && clock_pulse && (
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(mode == 3'd0 && gate_sampled && msb_write == 1'b0) ||
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(mode == 3'd1) ||
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(mode[1:0] == 2'd2 && gate_sampled) ||
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(mode == 3'd4 && gate_sampled) ||
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(mode == 3'd5)
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);
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wire enable_double = ~(load) && loaded && clock_pulse && mode[1:0] == 2'd3 && gate_sampled;
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//------------------------------------------------------------------------------
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wire [3:0] bcd_3 = counter[15:12] - 4'd1;
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wire [3:0] bcd_2 = counter[11:8] - 4'd1;
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wire [3:0] bcd_1 = counter[7:4] - 4'd1;
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wire [15:0] counter_minus_1 =
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(bcd && counter[15:0] == 16'd0)? 16'h9999 :
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(bcd && counter[11:0] == 12'd0)? { bcd_3, 12'h999 } :
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(bcd && counter[7:0] == 8'd0)? { counter[15:12], bcd_2, 8'h99 } :
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(bcd && counter[3:0] == 4'd0)? { counter[15:8], bcd_1, 4'h9 } :
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counter - 16'd1;
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wire [15:0] counter_minus_2 =
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(bcd && counter[15:0] == 16'd0)? 16'h9998 :
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(bcd && counter[11:0] == 12'd0)? { bcd_3, 12'h998 } :
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(bcd && counter[7:0] == 8'd0)? { counter[15:12], bcd_2, 8'h98 } :
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(bcd && counter[3:0] == 4'd0)? { counter[15:8], bcd_1, 4'h8 } :
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counter - 16'd2;
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reg [15:0] counter;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) counter <= 16'd0;
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else if(load_even) counter <= { counter_m, counter_l[7:1], 1'b0 };
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else if(load) counter <= { counter_m, counter_l };
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else if(enable_double) counter <= counter_minus_2;
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else if(enable) counter <= counter_minus_1;
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end
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//------------------------------------------------------------------------------
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endmodule
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