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[/] [ao486/] [trunk/] [rtl/] [soc/] [soc.v] - Blame information for rev 7

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Line No. Rev Author Line
1 2 alfik
/*
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 * Copyright (c) 2014, Aleksander Osman
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions are met:
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 *
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 * * Redistributions of source code must retain the above copyright notice, this
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 *   list of conditions and the following disclaimer.
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 *
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 * * Redistributions in binary form must reproduce the above copyright notice,
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 *   this list of conditions and the following disclaimer in the documentation
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 *   and/or other materials provided with the distribution.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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module soc(
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    input               CLOCK_50,
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    //SDRAM
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    output      [12:0]  DRAM_ADDR,
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    output      [1:0]   DRAM_BA,
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    output              DRAM_CAS_N,
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    output              DRAM_CKE,
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    output              DRAM_CLK,
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    output              DRAM_CS_N,
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    inout       [31:0]  DRAM_DQ,
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    output      [3:0]   DRAM_DQM,
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    output              DRAM_RAS_N,
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    output              DRAM_WE_N,
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    //PS2 KEYBOARD
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    inout               PS2_CLK,
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    inout               PS2_DAT,
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    //PS2 MOUSE
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    inout               PS2_CLK2,
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    inout               PS2_DAT2,
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    //KEYS
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    input       [3:0]   KEY,
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    //SD
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    output              SD_CLK,
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    inout               SD_CMD,
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    inout       [3:0]   SD_DAT,
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    input               SD_WP_N,
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    //VGA
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    output              VGA_CLK,
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    output              VGA_SYNC_N,
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    output              VGA_BLANK_N,
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    output              VGA_HS,
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    output              VGA_VS,
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    output      [7:0]   VGA_R,
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    output      [7:0]   VGA_G,
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    output      [7:0]   VGA_B,
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    //SOUND
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    output              I2C_SCLK,
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    inout               I2C_SDAT,
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    output              AUD_XCK,
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    output              AUD_BCLK,
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    output              AUD_DACDAT,
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    output              AUD_DACLRCK
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);
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//------------------------------------------------------------------------------
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assign DRAM_CLK = clk_sys;
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//------------------------------------------------------------------------------
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wire clk_sys;
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wire clk_vga;
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wire clk_sound;
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wire rst_n;
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pll pll_inst(
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    .inclk0     (CLOCK_50),
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    .c0         (clk_sys),
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    .c1         (clk_vga),
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    .c2         (clk_sound),
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    .locked     (rst_n)
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);
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//------------------------------------------------------------------------------
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wire [7:0] pio_output;
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wire ps2_a20_enable;
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wire ps2_reset_n;
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//------------------------------------------------------------------------------
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system u0(
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    .clk_sys_clk                       (clk_sys),
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    .reset_sys_reset_n                 (rst_n),
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    .clk_vga_clk                       (clk_vga),
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    .reset_vga_reset_n                 (rst_n),
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    .clk_sound_clk                     (clk_sound),
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    .reset_sound_reset_n               (rst_n),
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    .export_vga_clock                  (VGA_CLK),
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    .export_vga_sync_n                 (VGA_SYNC_N),
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    .export_vga_blank_n                (VGA_BLANK_N),
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    .export_vga_horiz_sync             (VGA_HS),
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    .export_vga_vert_sync              (VGA_VS),
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    .export_vga_r                      (VGA_R),
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    .export_vga_g                      (VGA_G),
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    .export_vga_b                      (VGA_B),
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    .sdram_conduit_end_addr            (DRAM_ADDR),
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    .sdram_conduit_end_ba              (DRAM_BA),
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    .sdram_conduit_end_cas_n           (DRAM_CAS_N),
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    .sdram_conduit_end_cke             (DRAM_CKE),
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    .sdram_conduit_end_cs_n            (DRAM_CS_N),
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    .sdram_conduit_end_dq              (DRAM_DQ),
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    .sdram_conduit_end_dqm             (DRAM_DQM),
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    .sdram_conduit_end_ras_n           (DRAM_RAS_N),
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    .sdram_conduit_end_we_n            (DRAM_WE_N),
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    .export_sound_sclk                 (I2C_SCLK),
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    .export_sound_sdat                 (I2C_SDAT),
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    .export_sound_xclk                 (AUD_XCK),
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    .export_sound_bclk                 (AUD_BCLK),
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    .export_sound_dat                  (AUD_DACDAT),
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    .export_sound_lr                   (AUD_DACLRCK),
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143 7 alfik
    .sd_clk_export                     (SD_CLK),
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    .sd_dat_export                     (SD_DAT),
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    .sd_cmd_export                     (SD_CMD),
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    .export_ps2_out_port_a20_enable    (ps2_a20_enable),
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    .export_ps2_out_port_reset_n       (ps2_reset_n),
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    .export_ps2_kbclk                  (PS2_CLK),
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    .export_ps2_kbdat                  (PS2_DAT),
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    .export_ps2_mouseclk               (PS2_CLK2),
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    .export_ps2_mousedat               (PS2_DAT2),
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    .pio_input_export                  ({ 2'd0, ps2_reset_n, ps2_a20_enable, KEY }),
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    .reset_only_ao486_reset            (pio_output[0] || ~(ps2_reset_n)),
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    .pio_output_export                 (pio_output)
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);
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endmodule

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