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alfik |
/*
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* Copyright (c) 2014, Aleksander Osman
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* * Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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module sound(
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input clk,
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input rst_n,
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output irq,
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//speaker input
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input speaker_enable,
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input speaker_out,
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//io slave 220h-22Fh
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input [3:0] io_address,
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input io_read,
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output reg [7:0] io_readdata,
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input io_write,
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input [7:0] io_writedata,
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//fm music io slave 388h-389h
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input fm_address,
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input fm_read,
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output [7:0] fm_readdata,
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input fm_write,
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input [7:0] fm_writedata,
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//dma
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output dma_soundblaster_req,
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input dma_soundblaster_ack,
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input dma_soundblaster_terminal,
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input [7:0] dma_soundblaster_readdata,
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output [7:0] dma_soundblaster_writedata,
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//sound interface master
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output [2:0] avm_address,
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input avm_waitrequest,
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output avm_write,
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output [31:0] avm_writedata,
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//mgmt slave
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/*
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0-255.[15:0]: cycles in period
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256.[12:0]: cycles in 80us
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257.[9:0]: cycles in 1 sample: 96000 Hz
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*/
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input [8:0] mgmt_address,
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input mgmt_write,
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input [31:0] mgmt_writedata
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);
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------ dsp
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wire [7:0] io_readdata_from_dsp;
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wire sample_from_dsp_disabled;
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wire sample_from_dsp_do;
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wire [7:0] sample_from_dsp_value;
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sound_dsp sound_dsp_inst(
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.clk (clk),
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.rst_n (rst_n),
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.irq (irq), //output
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//io slave 220h-22Fh
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.io_address (io_address), //input [3:0]
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.io_read (io_read), //input
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.io_readdata_from_dsp (io_readdata_from_dsp), //output [7:0]
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.io_write (io_write), //input
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.io_writedata (io_writedata), //input [7:0]
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//dma
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.dma_soundblaster_req (dma_soundblaster_req), //output
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.dma_soundblaster_ack (dma_soundblaster_ack), //input
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.dma_soundblaster_terminal (dma_soundblaster_terminal), //input
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.dma_soundblaster_readdata (dma_soundblaster_readdata), //input [7:0]
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.dma_soundblaster_writedata (dma_soundblaster_writedata), //output [7:0]
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//sample
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.sample_from_dsp_disabled (sample_from_dsp_disabled), //output
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.sample_from_dsp_do (sample_from_dsp_do), //output
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.sample_from_dsp_value (sample_from_dsp_value), //output [7:0] unsigned
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//mgmt slave
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/*
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0-255.[15:0]: cycles in period
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*/
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.mgmt_address (mgmt_address), //input [8:0]
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.mgmt_write (mgmt_write), //input
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.mgmt_writedata (mgmt_writedata) //input [31:0]
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);
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//------------------------------------------------------------------------------ opl2
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wire [7:0] sb_readdata_from_opl2;
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wire sample_from_opl2;
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wire [15:0] sample_from_opl2_value;
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sound_opl2 sound_opl2_inst(
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.clk (clk),
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.rst_n (rst_n),
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//sb slave 220h-22Fh
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.sb_address (io_address), //input [3:0]
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.sb_read (io_read), //input
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.sb_readdata_from_opl2 (sb_readdata_from_opl2), //output [7:0]
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.sb_write (io_write), //input
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.sb_writedata (io_writedata), //input [7:0]
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//fm music io slave 388h-389h
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.fm_address (fm_address), //input
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.fm_read (fm_read), //input
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.fm_readdata (fm_readdata), //output [7:0]
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.fm_write (fm_write), //input
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.fm_writedata (fm_writedata), //input [7:0]
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//sample
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.sample_from_opl2 (sample_from_opl2), //output
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.sample_from_opl2_value (sample_from_opl2_value), //output [15:0]
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//mgmt slave
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/*
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256.[12:0]: cycles in 80us
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257.[9:0]: cycles in 1 sample: 96000 Hz
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*/
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.mgmt_address (mgmt_address), //input [8:0]
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.mgmt_write (mgmt_write), //input
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.mgmt_writedata (mgmt_writedata) //input [31:0]
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);
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//------------------------------------------------------------------------------ io_readdata
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wire [7:0] io_readdata_next =
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(io_address == 4'h8 || io_address == 4'h9)? sb_readdata_from_opl2 :
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io_readdata_from_dsp;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) io_readdata <= 8'd0;
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else io_readdata <= io_readdata_next;
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end
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//------------------------------------------------------------------------------ speaker
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reg [15:0] speaker_value;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) speaker_value <= 16'd0;
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else if(speaker_enable && speaker_out == 1'b0) speaker_value <= 16'd16384;
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else if(speaker_enable && speaker_out == 1'b1) speaker_value <= 16'd49152;
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else speaker_value <= 16'd0;
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end
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//------------------------------------------------------------------------------
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reg [15:0] sample_dsp;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) sample_dsp <= 16'd0;
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else if(sample_from_dsp_disabled) sample_dsp <= 16'd0;
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else if(sample_from_dsp_do) sample_dsp <= { sample_from_dsp_value, 8'd0 } - 16'd32768; //unsigned to signed
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end
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reg [15:0] sample_opl2;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) sample_opl2 <= 16'd0;
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else if(sample_from_opl2) sample_opl2 <= sample_from_opl2_value; //already signed
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end
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wire [15:0] sample_sum_1 = sample_dsp + sample_opl2;
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wire [15:0] sample_next_1 = (sample_dsp[15] == 1'b0 && sample_opl2[15] == 1'b0 && sample_sum_1[15] == 1'b1)? 16'd32767 :
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(sample_dsp[15] == 1'b1 && sample_opl2[15] == 1'b1 && sample_sum_1[15] == 1'b0)? 16'd32768 :
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sample_sum_1[15:0];
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reg [15:0] sample_sum_1_reg;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) sample_sum_1_reg <= 16'd0;
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else if(state == STATE_LOAD_1) sample_sum_1_reg <= sample_next_1;
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end
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wire [15:0] sample_sum_2 = sample_sum_1_reg + speaker_value;
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wire [15:0] sample_next_2 = (sample_sum_1_reg[15] == 1'b0 && speaker_value[15] == 1'b0 && sample_sum_2[15] == 1'b1)? 16'd32767 :
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(sample_sum_1_reg[15] == 1'b1 && speaker_value[15] == 1'b1 && sample_sum_2[15] == 1'b0)? 16'd32768 :
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sample_sum_2[15:0];
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//------------------------------------------------------------------------------
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localparam [1:0] STATE_IDLE = 2'd0;
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localparam [1:0] STATE_LOAD_1 = 2'd1;
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localparam [1:0] STATE_LOAD_2 = 2'd2;
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localparam [1:0] STATE_WRITE = 2'd3;
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reg [1:0] state;
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reg [15:0] sample_sum_2_reg;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) sample_sum_2_reg <= 16'd0;
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else if(state == STATE_LOAD_2) sample_sum_2_reg <= sample_next_2;
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end
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assign avm_address = 3'd0;
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assign avm_writedata = { 16'd0, sample_sum_2_reg }; //signed
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assign avm_write = state == STATE_WRITE;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) state <= STATE_IDLE;
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else if(state == STATE_IDLE && sample_from_opl2) state <= STATE_LOAD_1;
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else if(state == STATE_LOAD_1) state <= STATE_LOAD_2;
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else if(state == STATE_LOAD_2) state <= STATE_WRITE;
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else if(state == STATE_WRITE && ~(avm_waitrequest)) state <= STATE_IDLE;
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end
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//------------------------------------------------------------------------------
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endmodule
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