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[/] [ao486/] [trunk/] [rtl/] [soc/] [sound/] [sound_opl2.v] - Blame information for rev 2

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1 2 alfik
/*
2
 * Copyright (c) 2014, Aleksander Osman
3
 * All rights reserved.
4
 *
5
 * Redistribution and use in source and binary forms, with or without
6
 * modification, are permitted provided that the following conditions are met:
7
 *
8
 * * Redistributions of source code must retain the above copyright notice, this
9
 *   list of conditions and the following disclaimer.
10
 *
11
 * * Redistributions in binary form must reproduce the above copyright notice,
12
 *   this list of conditions and the following disclaimer in the documentation
13
 *   and/or other materials provided with the distribution.
14
 *
15
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
19
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
22
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
23
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
24
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25
 */
26
 
27
module sound_opl2(
28
    input               clk,
29
    input               rst_n,
30
 
31
    //sb slave 220h-22Fh
32
    input       [3:0]   sb_address,
33
    input               sb_read,
34
    output      [7:0]   sb_readdata_from_opl2,
35
    input               sb_write,
36
    input       [7:0]   sb_writedata,
37
 
38
 
39
    //fm music io slave 388h-389h
40
    input               fm_address,
41
    input               fm_read,
42
    output      [7:0]   fm_readdata,
43
    input               fm_write,
44
    input       [7:0]   fm_writedata,
45
 
46
    //sample
47
    output              sample_from_opl2,
48
    output      [15:0]  sample_from_opl2_value,
49
 
50
    //mgmt slave
51
    /*
52
    256.[12:0]:  cycles in 80us
53
    257.[9:0]:   cycles in 1 sample: 96000 Hz
54
    */
55
    input       [8:0]   mgmt_address,
56
    input               mgmt_write,
57
    input       [31:0]  mgmt_writedata
58
);
59
 
60
//------------------------------------------------------------------------------
61
 
62
reg [7:0] io_readdata;
63
always @(posedge clk or negedge rst_n) begin
64
    if(rst_n == 1'b0)   io_readdata <= 8'h06;
65
    else                io_readdata <= { timer1_overflow | timer2_overflow, timer1_overflow, timer2_overflow, 1'b0, 4'h6 };
66
end
67
 
68
assign sb_readdata_from_opl2 = io_readdata;
69
assign fm_readdata           = io_readdata;
70
 
71
//388h reads 06h for OPL2
72
 
73
//------------------------------------------------------------------------------
74
 
75
reg [7:0] index;
76
always @(posedge clk or negedge rst_n) begin
77
    if(rst_n == 1'b0)                                               index <= 8'd0;
78
    else if((sb_address == 4'd0 || sb_address == 4'd8) && sb_write) index <= sb_writedata;
79
    else if(fm_address == 1'd0 && fm_write)                         index <= fm_writedata;
80
end
81
 
82
wire io_write = (((sb_address == 4'd1 || sb_address == 4'd9) && sb_write) || (fm_address == 1'd1 && fm_write));
83
 
84
wire [7:0] io_writedata = (sb_write)? sb_writedata : fm_writedata;
85
 
86
//------------------------------------------------------------------------------ timer 1
87
 
88
reg [7:0] timer1_preset;
89
always @(posedge clk or negedge rst_n) begin
90
    if(rst_n == 1'b0)                   timer1_preset <= 8'd0;
91
    else if(io_write && index == 8'h02) timer1_preset <= io_writedata;
92
end
93
 
94
reg timer1_mask;
95
always @(posedge clk or negedge rst_n) begin
96
    if(rst_n == 1'b0)                                           timer1_mask <= 1'd0;
97
    else if(io_write && index == 8'h04 && ~(io_writedata[7]))   timer1_mask <= io_writedata[6];
98
end
99
 
100
reg timer1_overflow;
101
always @(posedge clk or negedge rst_n) begin
102
    if(rst_n == 1'b0)                                                                   timer1_overflow <= 1'b0;
103
    else if(io_write && index == 8'h04 && io_writedata[7])                              timer1_overflow <= 1'b0;
104
    else if(io_write && index == 8'h04 && ~(io_writedata[7]) && io_writedata[6])        timer1_overflow <= 1'b0;
105
    else if(timer1_active && timer1_sub == 13'd0 && timer1 == 8'hFF && ~(timer1_mask))  timer1_overflow <= 1'b1;
106
end
107
 
108
wire timer1_activate = io_write && index == 8'h04 && ~(io_writedata[7]) && ~(timer1_active) && io_writedata[0];
109
 
110
reg timer1_active;
111
always @(posedge clk or negedge rst_n) begin
112
    if(rst_n == 1'b0)                                                                   timer1_active <= 1'd0;
113
    else if(timer1_activate)                                                            timer1_active <= 1'b1;
114
    else if(io_write && index == 8'h04 && ~(io_writedata[7]) && ~(io_writedata[0]))     timer1_active <= 1'b0;
115
end
116
 
117
reg [7:0] timer1;
118
always @(posedge clk or negedge rst_n) begin
119
    if(rst_n == 1'b0)                                                   timer1 <= 8'd0;
120
    else if(timer1_activate)                                            timer1 <= timer1_preset;
121
    else if(timer1_active && timer1_sub == 13'd0 && timer1 == 8'hFF)    timer1 <= timer1_preset;
122
    else if(timer1_active && timer1_sub == 13'd0)                       timer1 <= timer1 + 8'd1;
123
end
124
 
125
reg [12:0] timer1_sub;
126
always @(posedge clk or negedge rst_n) begin
127
    if(rst_n == 1'b0)                               timer1_sub <= 13'd0;
128
    else if(timer1_activate)                        timer1_sub <= period_80us;
129
    else if(timer1_active && timer1_sub > 13'd0)    timer1_sub <= timer1_sub - 13'd1;
130
    else if(timer1_active && timer1_sub == 13'd0)   timer1_sub <= period_80us;
131
end
132
 
133
//------------------------------------------------------------------------------ timer 2
134
 
135
reg [7:0] timer2_preset;
136
always @(posedge clk or negedge rst_n) begin
137
    if(rst_n == 1'b0)                   timer2_preset <= 8'd0;
138
    else if(io_write && index == 8'h03) timer2_preset <= io_writedata;
139
end
140
 
141
reg timer2_mask;
142
always @(posedge clk or negedge rst_n) begin
143
    if(rst_n == 1'b0)                                           timer2_mask <= 1'd0;
144
    else if(io_write && index == 8'h04 && ~(io_writedata[7]))   timer2_mask <= io_writedata[5];
145
end
146
 
147
reg timer2_overflow;
148
always @(posedge clk or negedge rst_n) begin
149
    if(rst_n == 1'b0)                                                                   timer2_overflow <= 1'b0;
150
    else if(io_write && index == 8'h04 && io_writedata[7])                              timer2_overflow <= 1'b0;
151
    else if(io_write && index == 8'h04 && ~(io_writedata[7]) && io_writedata[5])        timer2_overflow <= 1'b0;
152
    else if(timer2_active && timer2_sub == 15'd0 && timer2 == 8'hFF && ~(timer2_mask))  timer2_overflow <= 1'b1;
153
end
154
 
155
wire timer2_activate = io_write && index == 8'h04 && ~(io_writedata[7]) && ~(timer2_active) && io_writedata[1];
156
 
157
reg timer2_active;
158
always @(posedge clk or negedge rst_n) begin
159
    if(rst_n == 1'b0)                                                                   timer2_active <= 1'd0;
160
    else if(timer2_activate)                                                            timer2_active <= 1'b1;
161
    else if(io_write && index == 8'h04 && ~(io_writedata[7]) && ~(io_writedata[1]))     timer2_active <= 1'b0;
162
end
163
 
164
reg [7:0] timer2;
165
always @(posedge clk or negedge rst_n) begin
166
    if(rst_n == 1'b0)                                                   timer2 <= 8'd0;
167
    else if(timer2_activate)                                            timer2 <= timer2_preset;
168
    else if(timer2_active && timer2_sub == 15'd0 && timer2 == 8'hFF)    timer2 <= timer2_preset;
169
    else if(timer2_active && timer2_sub == 15'd0)                       timer2 <= timer2 + 8'd1;
170
end
171
 
172
reg [14:0] timer2_sub;
173
always @(posedge clk or negedge rst_n) begin
174
    if(rst_n == 1'b0)                               timer2_sub <= 15'd0;
175
    else if(timer2_activate)                        timer2_sub <= { period_80us, 2'b00 };
176
    else if(timer2_active && timer2_sub > 15'd0)    timer2_sub <= timer2_sub - 15'd1;
177
    else if(timer2_active && timer2_sub == 15'd0)   timer2_sub <= { period_80us, 2'b00 };
178
end
179
 
180
//------------------------------------------------------------------------------ mgmt
181
 
182
reg [12:0] period_80us;
183
always @(posedge clk or negedge rst_n) begin
184
    if(rst_n == 1'b0)                               period_80us <= 13'd2400;
185
    else if(mgmt_write && mgmt_address == 9'd256)   period_80us <= mgmt_writedata[12:0];
186
end
187
 
188
reg [9:0] period_sample;
189
always @(posedge clk or negedge rst_n) begin
190
    if(rst_n == 1'b0)                               period_sample <= 10'd347;
191
    else if(mgmt_write && mgmt_address == 9'd257)   period_sample <= mgmt_writedata[9:0];
192
end
193
 
194
//------------------------------------------------------------------------------ register write with immediate reaction
195
 
196
reg await_waveform_select_enable;
197
always @(posedge clk or negedge rst_n) begin
198
    if(rst_n == 1'b0)                       await_waveform_select_enable <= 1'b0;
199
    else if(io_write && index == 8'h01)     await_waveform_select_enable <= io_writedata[5];
200
end
201
 
202
//------------------------------------------------------------------------------ register write with delayed reaction
203
 
204
reg await_keyboard_split;
205
always @(posedge clk or negedge rst_n) begin
206
    if(rst_n == 1'b0)                       await_keyboard_split <= 1'b0;
207
    else if(io_write && index == 8'h08)     await_keyboard_split <= io_writedata[6];
208
end
209
 
210
reg await_tremolo_depth;
211
always @(posedge clk or negedge rst_n) begin
212
    if(rst_n == 1'b0)                       await_tremolo_depth <= 1'b0;
213
    else if(io_write && index == 8'hBD)     await_tremolo_depth <= io_writedata[7];
214
end
215
 
216
reg await_vibrato_depth;
217
always @(posedge clk or negedge rst_n) begin
218
    if(rst_n == 1'b0)                       await_vibrato_depth <= 1'b0;
219
    else if(io_write && index == 8'hBD)     await_vibrato_depth <= io_writedata[6];
220
end
221
 
222
reg await_rythm;
223
always @(posedge clk or negedge rst_n) begin
224
    if(rst_n == 1'b0)                       await_rythm <= 1'b0;
225
    else if(io_write && index == 8'hBD)     await_rythm <= io_writedata[5];
226
end
227
 
228
//------------------------------------------------------------------------------
229
 
230
//waveform_select_enable
231
 
232
//composite_sine_wave
233
 
234
//enable_bass_drum
235
//enable_snare_drum
236
//enable_tom_tom
237
//enable_cymbal
238
//enable_hi_hat
239
 
240
reg keyboard_split;
241
always @(posedge clk or negedge rst_n) begin
242
    if(rst_n == 1'b0)               keyboard_split <= 1'b0;
243
    else if(prepare_cnt_load_regs)  keyboard_split <= await_keyboard_split;
244
end
245
 
246
reg tremolo_depth;
247
always @(posedge clk or negedge rst_n) begin
248
    if(rst_n == 1'b0)               tremolo_depth <= 1'b0;
249
    else if(prepare_cnt_load_regs)  tremolo_depth <= await_tremolo_depth;
250
end
251
 
252
reg vibrato_depth;
253
always @(posedge clk or negedge rst_n) begin
254
    if(rst_n == 1'b0)               vibrato_depth <= 1'b0;
255
    else if(prepare_cnt_load_regs)  vibrato_depth <= await_vibrato_depth;
256
end
257
 
258
reg rythm;
259
always @(posedge clk or negedge rst_n) begin
260
    if(rst_n == 1'b0)               rythm <= 1'b0;
261
    else if(prepare_cnt_load_regs)  rythm <= await_rythm;
262
end
263
 
264
//------------------------------------------------------------------------------
265
 
266
wire prepare_cnt_load_regs = prepare_cnt == 7'd2;
267
 
268
wire prepare_cnt_sample_1 = prepare_cnt == 7'd114;
269
wire prepare_cnt_sample_2 = prepare_cnt == 7'd115;
270
wire prepare_cnt_sample_3 = prepare_cnt == 7'd116;
271
wire prepare_cnt_sample_4 = prepare_cnt == 7'd117;
272
wire prepare_cnt_sample_5 = prepare_cnt == 7'd118;
273
wire prepare_cnt_sample_6 = prepare_cnt == 7'd119;
274
wire prepare_cnt_sample_7 = prepare_cnt == 7'd120;
275
wire prepare_cnt_sample_8 = prepare_cnt == 7'd121;
276
wire prepare_cnt_sample_9 = prepare_cnt == 7'd122;
277
 
278
wire prepare_cnt_sample_10= prepare_cnt == 7'd123;
279
wire prepare_cnt_sample_11= prepare_cnt == 7'd124;
280
 
281
//------------------------------------------------------------------------------
282
 
283
reg [9:0] sample_cnt;
284
always @(posedge clk or negedge rst_n) begin
285
    if(rst_n == 1'b0)               sample_cnt <= 10'd0;
286
    else if(sample_cnt == 10'd0)    sample_cnt <= period_sample - 10'd1;
287
    else                            sample_cnt <= sample_cnt - 10'd1;
288
end
289
 
290
//------------------------------------------------------------------------------
291
 
292
reg [6:0] prepare_cnt;
293
always @(posedge clk or negedge rst_n) begin
294
    if(rst_n == 1'b0)               prepare_cnt <= 7'd0;
295
    else if(sample_cnt == 10'd1)    prepare_cnt <= 7'd1;
296
    else if(prepare_cnt != 7'd0)    prepare_cnt <= prepare_cnt + 7'd1;
297
end
298
 
299
reg [22:0] lfsr;
300
always @(posedge clk or negedge rst_n) begin
301
    if(rst_n == 1'b0)               lfsr <= 23'd1;
302
    else if(prepare_cnt_load_regs)  lfsr <= { lfsr[22] ^ lfsr[15] ^ lfsr[14] ^ lfsr[0], lfsr[22:1] };
303
end
304
 
305
//cliping
306
//wire [15:0] sample_next = (sample[25] == 1'b0 && sample > 26'h0007FFF)? 26'h0007FFF : (sample[25] == 1'b1 && sample < 26'h3FF8000)? 26'h3FF8000 : sample;
307
 
308
wire [15:0] sample_next =
309
    (sample[25] == 1'b0 && sample[24] == 1'b1)? sample[25:10] :
310
    (sample[25] == 1'b0 && sample[23] == 1'b1)? sample[24:9] :
311
    (sample[25] == 1'b0 && sample[22] == 1'b1)? sample[23:8] :
312
    (sample[25] == 1'b0 && sample[21] == 1'b1)? sample[22:7] :
313
    (sample[25] == 1'b0 && sample[20] == 1'b1)? sample[21:6] :
314
    (sample[25] == 1'b0 && sample[19] == 1'b1)? sample[20:5] :
315
    (sample[25] == 1'b0 && sample[18] == 1'b1)? sample[19:4] :
316
    (sample[25] == 1'b0 && sample[17] == 1'b1)? sample[18:3] :
317
    (sample[25] == 1'b0 && sample[16] == 1'b1)? sample[17:2] :
318
    (sample[25] == 1'b0 && sample[15] == 1'b1)? sample[16:1] :
319
    (sample[25] == 1'b1 && sample[24] == 1'b0)? sample[25:10] :
320
    (sample[25] == 1'b1 && sample[23] == 1'b0)? sample[24:9] :
321
    (sample[25] == 1'b1 && sample[22] == 1'b0)? sample[23:8] :
322
    (sample[25] == 1'b1 && sample[21] == 1'b0)? sample[22:7] :
323
    (sample[25] == 1'b1 && sample[20] == 1'b0)? sample[21:6] :
324
    (sample[25] == 1'b1 && sample[19] == 1'b0)? sample[20:5] :
325
    (sample[25] == 1'b1 && sample[18] == 1'b0)? sample[19:4] :
326
    (sample[25] == 1'b1 && sample[17] == 1'b0)? sample[18:3] :
327
    (sample[25] == 1'b1 && sample[16] == 1'b0)? sample[17:2] :
328
    (sample[25] == 1'b1 && sample[15] == 1'b0)? sample[16:1] :
329
                                                sample[15:0];
330
 
331
reg [25:0] sample;
332
always @(posedge clk or negedge rst_n) begin
333
    if(rst_n == 1'b0)               sample <= 26'd0;
334
    else if(prepare_cnt_sample_1)   sample <=          { {10{chanval_0[15]}}, chanval_0 };
335
    else if(prepare_cnt_sample_2)   sample <= sample + { {10{chanval_1[15]}}, chanval_1 };
336
    else if(prepare_cnt_sample_3)   sample <= sample + { {10{chanval_2[15]}}, chanval_2 };
337
    else if(prepare_cnt_sample_4)   sample <= sample + { {10{chanval_3[15]}}, chanval_3 };
338
    else if(prepare_cnt_sample_5)   sample <= sample + { {10{chanval_4[15]}}, chanval_4 };
339
    else if(prepare_cnt_sample_6)   sample <= sample + { {10{chanval_5[15]}}, chanval_5 };
340
    else if(prepare_cnt_sample_7)   sample <= sample + { {10{chanval_6[15]}}, chanval_6 };
341
    else if(prepare_cnt_sample_8)   sample <= sample + { {10{chanval_7[15]}}, chanval_7 };
342
    else if(prepare_cnt_sample_9)   sample <= sample + { {10{chanval_8[15]}}, chanval_8 };
343
 
344
    else if(prepare_cnt_sample_10)  sample <= sample_next;
345
end
346
 
347
assign sample_from_opl2_value = sample[15:0];
348
assign sample_from_opl2       = prepare_cnt_sample_11;
349
 
350
//------------------------------------------------------------------------------
351
 
352
wire rythm_c1;
353
wire rythm_c3;
354
 
355
wire [15:0] chanval_0;
356
wire [15:0] chanval_1;
357
wire [15:0] chanval_2;
358
wire [15:0] chanval_3;
359
wire [15:0] chanval_4;
360
wire [15:0] chanval_5;
361
wire [15:0] chanval_6;
362
wire [15:0] chanval_7;
363
wire [15:0] chanval_8;
364
 
365
sound_opl2_channel channel_0_inst(
366
    .clk                    (clk),
367
    .rst_n                  (rst_n),
368
 
369
    .write_20h_35h_op1      (io_write && index == 8'h20),  //input
370
    .write_40h_55h_op1      (io_write && index == 8'h40),  //input
371
    .write_60h_75h_op1      (io_write && index == 8'h60),  //input
372
    .write_80h_95h_op1      (io_write && index == 8'h80),  //input
373
    .write_E0h_F5h_op1      (io_write && index == 8'hE0),  //input
374
 
375
    .write_20h_35h_op2      (io_write && index == 8'h23),  //input
376
    .write_40h_55h_op2      (io_write && index == 8'h43),  //input
377
    .write_60h_75h_op2      (io_write && index == 8'h63),  //input
378
    .write_80h_95h_op2      (io_write && index == 8'h83),  //input
379
    .write_E0h_F5h_op2      (io_write && index == 8'hE3),  //input
380
 
381
    .write_A0h_A8h          (io_write && index == 8'hA0),  //input
382
    .write_B0h_B8h          (io_write && index == 8'hB0),  //input
383
    .write_C0h_C8h          (io_write && index == 8'hC0),  //input
384
 
385
    .writedata              (io_writedata),  //input [7:0]
386
 
387
    .vibrato_depth          (vibrato_depth),    //input
388
    .tremolo_depth          (tremolo_depth),    //input
389
    .waveform_select_enable (await_waveform_select_enable),   //input
390
    .keyboard_split         (keyboard_split),           //input
391
 
392
    .prepare_cnt            (prepare_cnt),  //input [6:0]
393
 
394
    .rythm_enable           (1'b0), //input
395
    .rythm_write            (1'b0), //input
396
    .rythm_bass_drum        (1'b0), //input
397
    .rythm_snare_drum       (1'b0), //input
398
    .rythm_tom_tom          (1'b0), //input
399
    .rythm_cymbal           (1'b0), //input
400
    .rythm_hi_hat           (1'b0), //input
401
 
402
    .channel_6              (1'b0), //input
403
    .channel_7              (1'b0), //input
404
    .channel_8              (1'b0), //input
405
 
406
    /* verilator lint_off PINNOCONNECT */
407
    .rythm_c1               (),     //output / not used
408
    .rythm_c3               (),     //output / not used
409
    /* verilator lint_on PINNOCONNECT */
410
 
411
    .rythm_phasebit         (1'b0), //input
412
    .rythm_noisebit         (1'b0), //input
413
 
414
    .chanval                (chanval_0)    //output [15:0]
415
);
416
 
417
sound_opl2_channel channel_1_inst(
418
    .clk                    (clk),
419
    .rst_n                  (rst_n),
420
 
421
    .write_20h_35h_op1      (io_write && index == 8'h21),  //input
422
    .write_40h_55h_op1      (io_write && index == 8'h41),  //input
423
    .write_60h_75h_op1      (io_write && index == 8'h61),  //input
424
    .write_80h_95h_op1      (io_write && index == 8'h81),  //input
425
    .write_E0h_F5h_op1      (io_write && index == 8'hE1),  //input
426
 
427
    .write_20h_35h_op2      (io_write && index == 8'h24),  //input
428
    .write_40h_55h_op2      (io_write && index == 8'h44),  //input
429
    .write_60h_75h_op2      (io_write && index == 8'h64),  //input
430
    .write_80h_95h_op2      (io_write && index == 8'h84),  //input
431
    .write_E0h_F5h_op2      (io_write && index == 8'hE4),  //input
432
 
433
    .write_A0h_A8h          (io_write && index == 8'hA1),  //input
434
    .write_B0h_B8h          (io_write && index == 8'hB1),  //input
435
    .write_C0h_C8h          (io_write && index == 8'hC1),  //input
436
 
437
    .writedata              (io_writedata),  //input [7:0]
438
 
439
    .vibrato_depth          (vibrato_depth),    //input
440
    .tremolo_depth          (tremolo_depth),    //input
441
    .waveform_select_enable (await_waveform_select_enable),   //input
442
    .keyboard_split         (keyboard_split),           //input
443
 
444
    .prepare_cnt            (prepare_cnt),  //input [6:0]
445
 
446
    .rythm_enable           (1'b0), //input
447
    .rythm_write            (1'b0), //input
448
    .rythm_bass_drum        (1'b0), //input
449
    .rythm_snare_drum       (1'b0), //input
450
    .rythm_tom_tom          (1'b0), //input
451
    .rythm_cymbal           (1'b0), //input
452
    .rythm_hi_hat           (1'b0), //input
453
 
454
    .channel_6              (1'b0), //input
455
    .channel_7              (1'b0), //input
456
    .channel_8              (1'b0), //input
457
 
458
    /* verilator lint_off PINNOCONNECT */
459
    .rythm_c1               (),     //output / not used
460
    .rythm_c3               (),     //output / not used
461
    /* verilator lint_on PINNOCONNECT */
462
 
463
    .rythm_phasebit         (1'b0), //input
464
    .rythm_noisebit         (1'b0), //input
465
 
466
    .chanval                (chanval_1)   //output [15:0]
467
);
468
 
469
sound_opl2_channel channel_2_inst(
470
    .clk                    (clk),
471
    .rst_n                  (rst_n),
472
 
473
    .write_20h_35h_op1      (io_write && index == 8'h22),  //input
474
    .write_40h_55h_op1      (io_write && index == 8'h42),  //input
475
    .write_60h_75h_op1      (io_write && index == 8'h62),  //input
476
    .write_80h_95h_op1      (io_write && index == 8'h82),  //input
477
    .write_E0h_F5h_op1      (io_write && index == 8'hE2),  //input
478
 
479
    .write_20h_35h_op2      (io_write && index == 8'h25),  //input
480
    .write_40h_55h_op2      (io_write && index == 8'h45),  //input
481
    .write_60h_75h_op2      (io_write && index == 8'h65),  //input
482
    .write_80h_95h_op2      (io_write && index == 8'h85),  //input
483
    .write_E0h_F5h_op2      (io_write && index == 8'hE5),  //input
484
 
485
    .write_A0h_A8h          (io_write && index == 8'hA2),  //input
486
    .write_B0h_B8h          (io_write && index == 8'hB2),  //input
487
    .write_C0h_C8h          (io_write && index == 8'hC2),  //input
488
 
489
    .writedata              (io_writedata),  //input [7:0]
490
 
491
    .vibrato_depth          (vibrato_depth),    //input
492
    .tremolo_depth          (tremolo_depth),    //input
493
    .waveform_select_enable (await_waveform_select_enable),   //input
494
    .keyboard_split         (keyboard_split),           //input
495
 
496
    .prepare_cnt            (prepare_cnt),  //input [6:0]
497
 
498
    .rythm_enable           (1'b0), //input
499
    .rythm_write            (1'b0), //input
500
    .rythm_bass_drum        (1'b0), //input
501
    .rythm_snare_drum       (1'b0), //input
502
    .rythm_tom_tom          (1'b0), //input
503
    .rythm_cymbal           (1'b0), //input
504
    .rythm_hi_hat           (1'b0), //input
505
 
506
    .channel_6              (1'b0), //input
507
    .channel_7              (1'b0), //input
508
    .channel_8              (1'b0), //input
509
 
510
    /* verilator lint_off PINNOCONNECT */
511
    .rythm_c1               (),     //output / not used
512
    .rythm_c3               (),     //output / not used
513
    /* verilator lint_on PINNOCONNECT */
514
 
515
    .rythm_phasebit         (1'b0), //input
516
    .rythm_noisebit         (1'b0), //input
517
 
518
    .chanval                (chanval_2)    //output [15:0]
519
);
520
 
521
sound_opl2_channel channel_3_inst(
522
    .clk                    (clk),
523
    .rst_n                  (rst_n),
524
 
525
    .write_20h_35h_op1      (io_write && index == 8'h28),  //input
526
    .write_40h_55h_op1      (io_write && index == 8'h48),  //input
527
    .write_60h_75h_op1      (io_write && index == 8'h68),  //input
528
    .write_80h_95h_op1      (io_write && index == 8'h88),  //input
529
    .write_E0h_F5h_op1      (io_write && index == 8'hE8),  //input
530
 
531
    .write_20h_35h_op2      (io_write && index == 8'h2B),  //input
532
    .write_40h_55h_op2      (io_write && index == 8'h4B),  //input
533
    .write_60h_75h_op2      (io_write && index == 8'h6B),  //input
534
    .write_80h_95h_op2      (io_write && index == 8'h8B),  //input
535
    .write_E0h_F5h_op2      (io_write && index == 8'hEB),  //input
536
 
537
    .write_A0h_A8h          (io_write && index == 8'hA3),  //input
538
    .write_B0h_B8h          (io_write && index == 8'hB3),  //input
539
    .write_C0h_C8h          (io_write && index == 8'hC3),  //input
540
 
541
    .writedata              (io_writedata),  //input [7:0]
542
 
543
    .vibrato_depth          (vibrato_depth),    //input
544
    .tremolo_depth          (tremolo_depth),    //input
545
    .waveform_select_enable (await_waveform_select_enable),   //input
546
    .keyboard_split         (keyboard_split),           //input
547
 
548
    .prepare_cnt            (prepare_cnt),  //input [6:0]
549
 
550
    .rythm_enable           (1'b0), //input
551
    .rythm_write            (1'b0), //input
552
    .rythm_bass_drum        (1'b0), //input
553
    .rythm_snare_drum       (1'b0), //input
554
    .rythm_tom_tom          (1'b0), //input
555
    .rythm_cymbal           (1'b0), //input
556
    .rythm_hi_hat           (1'b0), //input
557
 
558
    .channel_6              (1'b0), //input
559
    .channel_7              (1'b0), //input
560
    .channel_8              (1'b0), //input
561
 
562
    /* verilator lint_off PINNOCONNECT */
563
    .rythm_c1               (),     //output / not used
564
    .rythm_c3               (),     //output / not used
565
    /* verilator lint_on PINNOCONNECT */
566
 
567
    .rythm_phasebit         (1'b0), //input
568
    .rythm_noisebit         (1'b0), //input
569
 
570
    .chanval                (chanval_3)    //output [15:0]
571
);
572
 
573
sound_opl2_channel channel_4_inst(
574
    .clk                    (clk),
575
    .rst_n                  (rst_n),
576
 
577
    .write_20h_35h_op1      (io_write && index == 8'h29),  //input
578
    .write_40h_55h_op1      (io_write && index == 8'h49),  //input
579
    .write_60h_75h_op1      (io_write && index == 8'h69),  //input
580
    .write_80h_95h_op1      (io_write && index == 8'h89),  //input
581
    .write_E0h_F5h_op1      (io_write && index == 8'hE9),  //input
582
 
583
    .write_20h_35h_op2      (io_write && index == 8'h2C),  //input
584
    .write_40h_55h_op2      (io_write && index == 8'h4C),  //input
585
    .write_60h_75h_op2      (io_write && index == 8'h6C),  //input
586
    .write_80h_95h_op2      (io_write && index == 8'h8C),  //input
587
    .write_E0h_F5h_op2      (io_write && index == 8'hEC),  //input
588
 
589
    .write_A0h_A8h          (io_write && index == 8'hA4),  //input
590
    .write_B0h_B8h          (io_write && index == 8'hB4),  //input
591
    .write_C0h_C8h          (io_write && index == 8'hC4),  //input
592
 
593
    .writedata              (io_writedata),  //input [7:0]
594
 
595
    .vibrato_depth          (vibrato_depth),    //input
596
    .tremolo_depth          (tremolo_depth),    //input
597
    .waveform_select_enable (await_waveform_select_enable),   //input
598
    .keyboard_split         (keyboard_split),           //input
599
 
600
    .prepare_cnt            (prepare_cnt),  //input [6:0]
601
 
602
    .rythm_enable           (1'b0), //input
603
    .rythm_write            (1'b0), //input
604
    .rythm_bass_drum        (1'b0), //input
605
    .rythm_snare_drum       (1'b0), //input
606
    .rythm_tom_tom          (1'b0), //input
607
    .rythm_cymbal           (1'b0), //input
608
    .rythm_hi_hat           (1'b0), //input
609
 
610
    .channel_6              (1'b0), //input
611
    .channel_7              (1'b0), //input
612
    .channel_8              (1'b0), //input
613
 
614
    /* verilator lint_off PINNOCONNECT */
615
    .rythm_c1               (),     //output / not used
616
    .rythm_c3               (),     //output / not used
617
    /* verilator lint_on PINNOCONNECT */
618
 
619
    .rythm_phasebit         (1'b0), //input
620
    .rythm_noisebit         (1'b0), //input
621
 
622
    .chanval                (chanval_4)    //output [15:0]
623
);
624
 
625
sound_opl2_channel channel_5_inst(
626
    .clk                    (clk),
627
    .rst_n                  (rst_n),
628
 
629
    .write_20h_35h_op1      (io_write && index == 8'h2A),  //input
630
    .write_40h_55h_op1      (io_write && index == 8'h4A),  //input
631
    .write_60h_75h_op1      (io_write && index == 8'h6A),  //input
632
    .write_80h_95h_op1      (io_write && index == 8'h8A),  //input
633
    .write_E0h_F5h_op1      (io_write && index == 8'hEA),  //input
634
 
635
    .write_20h_35h_op2      (io_write && index == 8'h2D),  //input
636
    .write_40h_55h_op2      (io_write && index == 8'h4D),  //input
637
    .write_60h_75h_op2      (io_write && index == 8'h6D),  //input
638
    .write_80h_95h_op2      (io_write && index == 8'h8D),  //input
639
    .write_E0h_F5h_op2      (io_write && index == 8'hED),  //input
640
 
641
    .write_A0h_A8h          (io_write && index == 8'hA5),  //input
642
    .write_B0h_B8h          (io_write && index == 8'hB5),  //input
643
    .write_C0h_C8h          (io_write && index == 8'hC5),  //input
644
 
645
    .writedata              (io_writedata),  //input [7:0]
646
 
647
    .vibrato_depth          (vibrato_depth),    //input
648
    .tremolo_depth          (tremolo_depth),    //input
649
    .waveform_select_enable (await_waveform_select_enable),   //input
650
    .keyboard_split         (keyboard_split),           //input
651
 
652
    .prepare_cnt            (prepare_cnt),  //input [6:0]
653
 
654
    .rythm_enable           (1'b0), //input
655
    .rythm_write            (1'b0), //input
656
    .rythm_bass_drum        (1'b0), //input
657
    .rythm_snare_drum       (1'b0), //input
658
    .rythm_tom_tom          (1'b0), //input
659
    .rythm_cymbal           (1'b0), //input
660
    .rythm_hi_hat           (1'b0), //input
661
 
662
    .channel_6              (1'b0), //input
663
    .channel_7              (1'b0), //input
664
    .channel_8              (1'b0), //input
665
 
666
    /* verilator lint_off PINNOCONNECT */
667
    .rythm_c1               (),     //output / not used
668
    .rythm_c3               (),     //output / not used
669
    /* verilator lint_on PINNOCONNECT */
670
 
671
    .rythm_phasebit         (1'b0), //input
672
    .rythm_noisebit         (1'b0), //input
673
 
674
    .chanval                (chanval_5)    //output [15:0]
675
);
676
 
677
sound_opl2_channel channel_6_inst(
678
    .clk                    (clk),
679
    .rst_n                  (rst_n),
680
 
681
    .write_20h_35h_op1      (io_write && index == 8'h30),  //input
682
    .write_40h_55h_op1      (io_write && index == 8'h50),  //input
683
    .write_60h_75h_op1      (io_write && index == 8'h70),  //input
684
    .write_80h_95h_op1      (io_write && index == 8'h90),  //input
685
    .write_E0h_F5h_op1      (io_write && index == 8'hF0),  //input
686
 
687
    .write_20h_35h_op2      (io_write && index == 8'h33),  //input
688
    .write_40h_55h_op2      (io_write && index == 8'h53),  //input
689
    .write_60h_75h_op2      (io_write && index == 8'h73),  //input
690
    .write_80h_95h_op2      (io_write && index == 8'h93),  //input
691
    .write_E0h_F5h_op2      (io_write && index == 8'hF3),  //input
692
 
693
    .write_A0h_A8h          (io_write && index == 8'hA6),  //input
694
    .write_B0h_B8h          (io_write && index == 8'hB6),  //input
695
    .write_C0h_C8h          (io_write && index == 8'hC6),  //input
696
 
697
    .writedata              (io_writedata),  //input [7:0]
698
 
699
    .vibrato_depth          (vibrato_depth),    //input
700
    .tremolo_depth          (tremolo_depth),    //input
701
    .waveform_select_enable (await_waveform_select_enable),   //input
702
    .keyboard_split         (keyboard_split),           //input
703
 
704
    .prepare_cnt            (prepare_cnt),  //input [6:0]
705
 
706
    .rythm_enable           (rythm),                                //input
707
    .rythm_write            (io_write && index == 8'hBD),           //input
708
    .rythm_bass_drum        (io_writedata[5] && io_writedata[4]),   //input
709
    .rythm_snare_drum       (1'b0),                                 //input
710
    .rythm_tom_tom          (1'b0),                                 //input
711
    .rythm_cymbal           (1'b0),                                 //input
712
    .rythm_hi_hat           (1'b0),                                 //input
713
 
714
    .channel_6              (1'b1), //input
715
    .channel_7              (1'b0), //input
716
    .channel_8              (1'b0), //input
717
 
718
    /* verilator lint_off PINNOCONNECT */
719
    .rythm_c1               (),     //output / not used
720
    .rythm_c3               (),     //output / not used
721
    /* verilator lint_on PINNOCONNECT */
722
 
723
    .rythm_phasebit         (1'b0), //input
724
    .rythm_noisebit         (1'b0), //input
725
 
726
    .chanval                (chanval_6)    //output [15:0]
727
);
728
 
729
sound_opl2_channel channel_7_inst(
730
    .clk                    (clk),
731
    .rst_n                  (rst_n),
732
 
733
    .write_20h_35h_op1      (io_write && index == 8'h31),  //input
734
    .write_40h_55h_op1      (io_write && index == 8'h51),  //input
735
    .write_60h_75h_op1      (io_write && index == 8'h71),  //input
736
    .write_80h_95h_op1      (io_write && index == 8'h91),  //input
737
    .write_E0h_F5h_op1      (io_write && index == 8'hF1),  //input
738
 
739
    .write_20h_35h_op2      (io_write && index == 8'h34),  //input
740
    .write_40h_55h_op2      (io_write && index == 8'h54),  //input
741
    .write_60h_75h_op2      (io_write && index == 8'h74),  //input
742
    .write_80h_95h_op2      (io_write && index == 8'h94),  //input
743
    .write_E0h_F5h_op2      (io_write && index == 8'hF4),  //input
744
 
745
    .write_A0h_A8h          (io_write && index == 8'hA7),  //input
746
    .write_B0h_B8h          (io_write && index == 8'hB7),  //input
747
    .write_C0h_C8h          (io_write && index == 8'hC7),  //input
748
 
749
    .writedata              (io_writedata),  //input [7:0]
750
 
751
    .vibrato_depth          (vibrato_depth),    //input
752
    .tremolo_depth          (tremolo_depth),    //input
753
    .waveform_select_enable (await_waveform_select_enable),   //input
754
    .keyboard_split         (keyboard_split),           //input
755
 
756
    .prepare_cnt            (prepare_cnt),  //input [6:0]
757
 
758
    .rythm_enable           (rythm),                                //input
759
    .rythm_write            (io_write && index == 8'hBD),           //input
760
    .rythm_bass_drum        (1'b0),                                 //input
761
    .rythm_snare_drum       (io_writedata[5] && io_writedata[3]),   //input
762
    .rythm_tom_tom          (1'b0),                                 //input
763
    .rythm_cymbal           (1'b0),                                 //input
764
    .rythm_hi_hat           (io_writedata[5] && io_writedata[0]),   //input
765
 
766
    .channel_6              (1'b0), //input
767
    .channel_7              (1'b1), //input
768
    .channel_8              (1'b0), //input
769
 
770
    .rythm_c1               (rythm_c1),             //output
771
    /* verilator lint_off PINNOCONNECT */
772
    .rythm_c3               (),                     //output / not used
773
    /* verilator lint_on PINNOCONNECT */
774
    .rythm_phasebit         (rythm_c1 | rythm_c3),  //input
775
    .rythm_noisebit         (lfsr[22]),             //input
776
 
777
    .chanval                (chanval_7)    //output [15:0]
778
);
779
 
780
sound_opl2_channel channel_8_inst(
781
    .clk                    (clk),
782
    .rst_n                  (rst_n),
783
 
784
    .write_20h_35h_op1      (io_write && index == 8'h32),  //input
785
    .write_40h_55h_op1      (io_write && index == 8'h52),  //input
786
    .write_60h_75h_op1      (io_write && index == 8'h72),  //input
787
    .write_80h_95h_op1      (io_write && index == 8'h92),  //input
788
    .write_E0h_F5h_op1      (io_write && index == 8'hF2),  //input
789
 
790
    .write_20h_35h_op2      (io_write && index == 8'h35),  //input
791
    .write_40h_55h_op2      (io_write && index == 8'h55),  //input
792
    .write_60h_75h_op2      (io_write && index == 8'h75),  //input
793
    .write_80h_95h_op2      (io_write && index == 8'h95),  //input
794
    .write_E0h_F5h_op2      (io_write && index == 8'hF5),  //input
795
 
796
    .write_A0h_A8h          (io_write && index == 8'hA8),  //input
797
    .write_B0h_B8h          (io_write && index == 8'hB8),  //input
798
    .write_C0h_C8h          (io_write && index == 8'hC8),  //input
799
 
800
    .writedata              (io_writedata),  //input [7:0]
801
 
802
    .vibrato_depth          (vibrato_depth),    //input
803
    .tremolo_depth          (tremolo_depth),    //input
804
    .waveform_select_enable (await_waveform_select_enable),   //input
805
    .keyboard_split         (keyboard_split),           //input
806
 
807
    .prepare_cnt            (prepare_cnt),  //input [6:0]
808
 
809
    .rythm_enable           (rythm),                                //input
810
    .rythm_write            (io_write && index == 8'hBD),           //input
811
    .rythm_bass_drum        (1'b0),                                 //input
812
    .rythm_snare_drum       (1'b0),                                 //input
813
    .rythm_tom_tom          (io_writedata[5] && io_writedata[2]),   //input
814
    .rythm_cymbal           (io_writedata[5] && io_writedata[1]),   //input
815
    .rythm_hi_hat           (1'b0),                                 //input
816
 
817
    .channel_6              (1'b0), //input
818
    .channel_7              (1'b0), //input
819
    .channel_8              (1'b1), //input
820
 
821
    /* verilator lint_off PINNOCONNECT */
822
    .rythm_c1               (),                     //output / not used
823
    /* verilator lint_on PINNOCONNECT */
824
    .rythm_c3               (rythm_c3),             //output
825
    .rythm_phasebit         (rythm_c1 | rythm_c3),  //input
826
    .rythm_noisebit         (1'b0),                 //input
827
 
828
    .chanval                (chanval_8)    //output [15:0]
829
);
830
 
831
//------------------------------------------------------------------------------
832
 
833
// synthesis translate_off
834
wire _unused_ok = &{ 1'b0, sb_read, fm_read, mgmt_writedata[31:13], 1'b0 };
835
// synthesis translate_on
836
 
837
//------------------------------------------------------------------------------
838
 
839
endmodule

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